[Subzero][MIPS32] Add LowerStore implementation

src/IceTargetLoweringMIPS32.cpp

 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost
@@ skipping 353 matching lines @@
   // There aren't any 64-bit integer registers for Mips32.
   assert(Type != IceType_i64);
   Variable *Reg = Func->makeVariable(Type);
   if (RegNum.hasValue())
     Reg->setRegNum(RegNum);
   else
     Reg->setMustHaveReg();
   return Reg;
 }
 
+OperandMIPS32Mem *TargetMIPS32::formMemoryOperand(Operand *Operand, Type Ty) {
+  // It may be the case that address mode optimization already creates an
+  // OperandMIPS32Mem, so in that case it wouldn't need another level of
+  // transformation.
+  if (llvm::isa<OperandMIPS32Mem>(Operand)) {

[Jim Stichnoth, 2016/05/31 18:18:52]

Sorry, I was a bit off in my previous comment.  This should look more like the
following instead:

  if (auto *Mem = llvm::dyn_cast<OperandMIPS32Mem>(Operand)) {
    return Mem;
  }

(I went ahead and made the change to avoid another round of reviews just for
this.)

+    return llvm::cast<OperandMIPS32Mem>(Operand);
+  }
+
+  // If we didn't do address mode optimization, then we only have a base/offset
+  // to work with. MIPS always requires a base register, so just use that to
+  // hold the operand.
+  auto *Base = llvm::cast<Variable>(legalize(Operand, Legal_Reg));
+  return OperandMIPS32Mem::create(
+      Func, Ty, Base,
+      llvm::cast<ConstantInteger32>(Ctx->getConstantZero(IceType_i32)));
+}
+
 void TargetMIPS32::emitVariable(const Variable *Var) const {
   if (!BuildDefs::dump())
     return;
   Ostream &Str = Ctx->getStrEmit();
   const Type FrameSPTy = IceType_i32;
   if (Var->hasReg()) {
     Str << '$' << getRegName(Var->getRegNum(), Var->getType());
     return;
   } else {
     int32_t Offset = Var->getStackOffset();
@@ skipping 936 matching lines @@
 
 void TargetMIPS32::lowerSelect(const InstSelect *Instr) {
   UnimplementedLoweringError(this, Instr);
 }
 
 void TargetMIPS32::lowerShuffleVector(const InstShuffleVector *Instr) {
   UnimplementedLoweringError(this, Instr);
 }
 
 void TargetMIPS32::lowerStore(const InstStore *Instr) {
-  UnimplementedLoweringError(this, Instr);
+  Operand *Value = Instr->getData();
+  Operand *Addr = Instr->getAddr();
+  OperandMIPS32Mem *NewAddr = formMemoryOperand(Addr, Value->getType());
+  Type Ty = NewAddr->getType();
+
+  if (Ty == IceType_i64) {
+    Value = legalizeUndef(Value);
+    Variable *ValueHi = legalizeToReg(hiOperand(Value));
+    Variable *ValueLo = legalizeToReg(loOperand(Value));
+    _sw(ValueHi, llvm::cast<OperandMIPS32Mem>(hiOperand(NewAddr)));
+    _sw(ValueLo, llvm::cast<OperandMIPS32Mem>(loOperand(NewAddr)));
+  } else {
+    Variable *ValueR = legalizeToReg(Value);
+    _sw(ValueR, NewAddr);
+  }
 }
 
 void TargetMIPS32::doAddressOptStore() { UnimplementedError(getFlags()); }
 
 void TargetMIPS32::lowerSwitch(const InstSwitch *Instr) {
   UnimplementedLoweringError(this, Instr);
 }
 
 void TargetMIPS32::lowerBreakpoint(const InstBreakpoint *Instr) {
   UnimplementedLoweringError(this, Instr);
@@ skipping 161 matching lines @@
   Str << "\t.set\t"
       << "nomips16\n";
 }
 
 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
 
 } // end of namespace MIPS32
 } // end of namespace Ice