Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(49)

Unified Diff: src/IceTargetLoweringMIPS32.h

Issue 1993993004: Subzero, MIPS32: Introduction of floating point registers (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Register allocation works, some code is removed Created 4 years, 7 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View side-by-side diff with in-line comments
Download patch
Index: src/IceTargetLoweringMIPS32.h
diff --git a/src/IceTargetLoweringMIPS32.h b/src/IceTargetLoweringMIPS32.h
index a90311a2f0d76cb046027b2c9d78a8bd23d11aca..8ea2923b9d468408a764cb7aea3fa3bee42a1041 100644
--- a/src/IceTargetLoweringMIPS32.h
+++ b/src/IceTargetLoweringMIPS32.h
@@ -184,6 +184,10 @@ public:
}
}
+ void _mfc1(Variable *Dest, Variable *Src) {
+ Context.insert<InstMIPS32Mfc1>(Dest, Src);
+ }
+
void _mfhi(Variable *Dest, Operand *Src) {
Context.insert<InstMIPS32Mfhi>(Dest, Src);
}
@@ -192,6 +196,10 @@ public:
Context.insert<InstMIPS32Mflo>(Dest, Src);
}
+ void _mtc1(Variable *Dest, Variable *Src) {
+ Context.insert<InstMIPS32Mtc1>(Dest, Src);
+ }
+
void _mthi(Variable *Dest, Operand *Src) {
Context.insert<InstMIPS32Mthi>(Dest, Src);
}

Powered by Google App Engine
This is Rietveld 408576698