Subzero, MIPS32: Introduction of floating point registers

src/IceRegistersMIPS32.h

Index: src/IceRegistersMIPS32.h
diff --git a/src/IceRegistersMIPS32.h b/src/IceRegistersMIPS32.h
index 4e14387039e50429a97012ab31c4f72aa48622d0..023132c233e7f30cdd9a8b2485a0c1dfc97b7492 100644
--- a/src/IceRegistersMIPS32.h
+++ b/src/IceRegistersMIPS32.h
@@ -50,6 +50,18 @@ enum GPRRegister {
       Encoded_Not_GPR = -1
 };
 
+/// An enum of FPR Registers. The enum value does match the encoding used
+/// to binary encode register operands in instructions.
+enum FPRRegister {
+#define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt,    \
+          isI64Pair, isFP32, isFP64, isVec128, alias_init)                     \
+                                                                               \
+  Encoded_##val = encode,
+  REGMIPS32_FPR_TABLE
+#undef X
+      Encoded_Not_FPR = -1
+};
+
 // TODO(jvoung): Floating point and vector registers...
 // Need to model overlap and difference in encoding too.
 
@@ -59,6 +71,22 @@ static inline GPRRegister getEncodedGPR(RegNumT RegNum) {
   return GPRRegister(RegNum - Reg_GPR_First);
 }
 
+static inline bool isGPRReg(RegNumT RegNum) {
+  return (int(Reg_GPR_First) <= int(RegNum)) && 
+         (unsigned(RegNum) <= Reg_GPR_Last);
+}
+
+static inline FPRRegister getEncodedFPR(RegNumT RegNum) {
+  assert(int(Reg_FPR_First) <= int(RegNum));
+  assert(unsigned(RegNum) <= Reg_FPR_Last);
+  return FPRRegister(RegNum - Reg_FPR_First);
+}
+
+static inline bool isFPRReg(RegNumT RegNum) {
+  return (int(Reg_FPR_First) <= int(RegNum)) && 
+         (unsigned(RegNum) <= Reg_FPR_Last);
+}
+
 const char *getRegName(RegNumT RegNum);
 
 } // end of namespace RegMIPS32