Subzero, MIPS32: Introduction of floating point registers

src/IceTargetLoweringMIPS32.cpp

 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost
@@ skipping 377 matching lines @@
   UnimplementedError(getFlags());
 }
 
 void TargetMIPS32::lowerArguments() {
   VarList &Args = Func->getArgs();
   // We are only handling integer registers for now. The Mips o32 ABI is
   // somewhat complex but will be implemented in its totality through follow
   // on patches.
   //
   unsigned NumGPRRegsUsed = 0;
+
   // For each register argument, replace Arg in the argument list with the
   // home register.  Then generate an instruction in the prolog to copy the
   // home register to the assigned location of Arg.
   Context.init(Func->getEntryNode());
   Context.setInsertPoint(Context.getCur());
   for (SizeT I = 0, E = Args.size(); I < E; ++I) {
     Variable *Arg = Args[I];
     Type Ty = Arg->getType();
     // TODO(rkotler): handle float/vector types.
     if (isVectorType(Ty)) {
       UnimplementedError(getFlags());
       continue;
     }
+
     if (isFloatingType(Ty)) {
+      assert(Ty = IceType_f32);

[Jim Stichnoth, 2016/05/19 23:12:25]

Is this really necessary, given the UnimplementedError that comes next?

[obucinac, 2016/05/27 11:13:18]

Done.

       UnimplementedError(getFlags());
       continue;
     }
+
     if (Ty == IceType_i64) {
       if (NumGPRRegsUsed >= MIPS32_MAX_GPR_ARG)
         continue;
       auto RegLo = RegNumT::fixme(RegMIPS32::Reg_A0 + NumGPRRegsUsed);
       auto RegHi = RegNumT::fixme(RegLo + 1);
       ++NumGPRRegsUsed;
       // Always start i64 registers at an even register, so this may end
       // up padding away a register.
       if (RegLo % 2 != 0) {
         RegLo = RegNumT::fixme(RegLo + 1);
@@ skipping 844 matching lines @@
 
 void TargetMIPS32::lowerPhi(const InstPhi * /*Instr*/) {
   Func->setError("Phi found in regular instruction list");
 }
 
 void TargetMIPS32::lowerRet(const InstRet *Instr) {
   Variable *Reg = nullptr;
   if (Instr->hasRetValue()) {
     Operand *Src0 = Instr->getRetValue();
     switch (Src0->getType()) {
+    case IceType_f32: {
+      Operand *Src0F = legalize(Src0, Legal_Reg);
+      Reg = makeReg(Src0F->getType(), RegMIPS32::Reg_V0);

[Jim Stichnoth, 2016/05/19 23:12:25]

Should this be Reg_F0 instead?

[obucinac, 2016/05/27 11:13:18]

We need to rework this to o32 convention. Leaving as is for now. o32 is our next
step.

+      _mov(Reg, Src0F);
+      break;
+    }
     case IceType_i1:
     case IceType_i8:
     case IceType_i16:
     case IceType_i32: {
       // Reg = legalizeToReg(Src0, RegMIPS32::Reg_V0);
       Operand *Src0F = legalize(Src0, Legal_Reg);
       Reg = makeReg(Src0F->getType(), RegMIPS32::Reg_V0);
       _mov(Reg, Src0F);
       break;
     }
@@ skipping 107 matching lines @@
   if (getFlags().getDisableTranslation())
     return;
   UnimplementedError(getFlags());
 }
 
 // Helper for legalize() to emit the right code to lower an operand to a
 // register of the appropriate type.
 Variable *TargetMIPS32::copyToReg(Operand *Src, RegNumT RegNum) {
   Type Ty = Src->getType();
   Variable *Reg = makeReg(Ty, RegNum);
-  if (isVectorType(Ty) || isFloatingType(Ty)) {
+  if (isVectorType(Ty)) {
+    UnimplementedError(getFlags());
+  } else if (isFloatingType(Ty)) {
     UnimplementedError(getFlags());
   } else {
     // Mov's Src operand can really only be the flexible second operand type
     // or a register. Users should guarantee that.
     _mov(Reg, Src);
   }
   return Reg;
 }
 
 Operand *TargetMIPS32::legalize(Operand *From, LegalMask Allowed,
                                 RegNumT RegNum) {
   Type Ty = From->getType();
   // Assert that a physical register is allowed.  To date, all calls
   // to legalize() allow a physical register. Legal_Flex converts
   // registers to the right type OperandMIPS32FlexReg as needed.
   assert(Allowed & Legal_Reg);
   // Go through the various types of operands:
   // OperandMIPS32Mem, Constant, and Variable.
   // Given the above assertion, if type of operand is not legal
   // (e.g., OperandMIPS32Mem and !Legal_Mem), we can always copy
   // to a register.
   if (auto *C = llvm::dyn_cast<ConstantRelocatable>(From)) {
     (void)C;
     // TODO(reed kotler): complete this case for proper implementation
     Variable *Reg = makeReg(Ty, RegNum);
     Context.insert<InstFakeDef>(Reg);
     return Reg;
+  } else if (auto *C32 = llvm::dyn_cast<ConstantFloat>(From)) {
+    const float Value = C32->getValue();
+    // Check if the immediate will fit in a Flexible second operand,
+    // if a Flexible second operand is allowed. We need to know the exact
+    // value, so that rules out relocatable constants.
+    // Also try the inverse and use MVN if possible.
+    // Do a movw/movt to a register.
+    Variable *Reg;
+    if (RegNum.hasValue())
+      Reg = getPhysicalRegister(RegNum);

[Jim Stichnoth, 2016/05/19 23:12:25]

I'm very nervous about this use of getPhysicalRegister (as well as the place
below where this one was copied from).

getPhysicalRegister is supposed to be used just for "special" registers like
stack pointer, frame pointer, zero.  These are ones that aren't normally tracked
during liveness analysis and aren't assigned during register allocation.  I
suspect that using it here may cause liveness validation problems on larger
examples.

Can you just use makeReg(Ty, RegNum) regardless of RegNum.hasValue()?

[obucinac, 2016/05/27 11:13:18]

We need to rework this to o32 convention. Leaving as is for now. o32 is our next
step.

+    else
+      Reg = makeReg(Ty, RegNum);
+
+    const uint32_t UIntValue = llvm::FloatToBits(Value);
+
+    if (isInt<16>(int32_t(UIntValue))) {
+      Variable *Zero = getPhysicalRegister(RegMIPS32::Reg_ZERO, Ty);
+      Context.insert<InstFakeDef>(Zero);
+      _addiu(Reg, Zero, UIntValue);
+    } else {
+      uint32_t UpperBits = (UIntValue >> 16) & 0xFFFF;
+      (void)UpperBits;

[Jim Stichnoth, 2016/05/19 23:12:25]

Remove this

[obucinac, 2016/05/27 11:13:18]

Done.

+      uint32_t LowerBits = UIntValue & 0xFFFF;
+      Variable *TReg = makeReg(Ty, RegNum);
+      _lui(TReg, UpperBits);
+      _ori(Reg, TReg, LowerBits);
+    }
+    return Reg;
   } else if (auto *C32 = llvm::dyn_cast<ConstantInteger32>(From)) {
     const uint32_t Value = C32->getValue();
     // Check if the immediate will fit in a Flexible second operand,
     // if a Flexible second operand is allowed. We need to know the exact
     // value, so that rules out relocatable constants.
     // Also try the inverse and use MVN if possible.
     // Do a movw/movt to a register.
     Variable *Reg;
     if (RegNum.hasValue())
       Reg = getPhysicalRegister(RegNum);
@@ skipping 42 matching lines @@
   Str << "\t.set\t"
       << "nomips16\n";
 }
 
 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
 
 } // end of namespace MIPS32
 } // end of namespace Ice