Subzero, MIPS32: Introduction of floating point registers

src/IceRegistersMIPS32.h

 //===- subzero/src/IceRegistersMIPS32.h - Register information --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 32 matching lines @@
 enum GPRRegister {
 #define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt,    \
           isI64Pair, isFP32, isFP64, isVec128, alias_init)                     \
                                                                                \
   Encoded_##val = encode,
   REGMIPS32_GPR_TABLE
 #undef X
       Encoded_Not_GPR = -1
 };
 
+/// An enum of FPR Registers. The enum value does match the encoding used
+/// to binary encode register operands in instructions.
+enum FPRRegister {
+#define X(val, encode, name, scratch, preserved, stackptr, frameptr, isInt,    \
+          isI64Pair, isFP32, isFP64, isVec128, alias_init)                     \
+                                                                               \
+  Encoded_##val = encode,
+  REGMIPS32_FPR_TABLE
+#undef X
+      Encoded_Not_FPR = -1
+};
+
 // TODO(jvoung): Floating point and vector registers...

[Jim Stichnoth, 2016/05/19 23:12:25]

Probably this TODO should be someone else's. :)

[obucinac, 2016/05/27 11:13:18]

Acknowledged.

 // Need to model overlap and difference in encoding too.
 
 static inline GPRRegister getEncodedGPR(RegNumT RegNum) {
   assert(int(Reg_GPR_First) <= int(RegNum));

[Jim Stichnoth, 2016/05/21 21:02:25]

There is a subtle problem with the use of *_First and *_Last in these
calculations, here and below.

Specifically in the getEncoded*() functions, there is a built-in assumption that
our register enum values start with the register with the lowest encoded value,
and end with that with the highest encoded value.  This means that if we
change/reverse the order of register enum values, we have to know to make actual
code changes in the getEncoded*() functions.

Why would we bother changing the register enum order?  For ARM, John did just
that for float versus double FP registers.  All things equal, the register
allocator chooses the register with the lowest enum value.  Since float and
double registers alias each other, John choose to list float registers from low
to high encoding, and double register from high to low, to (hopefully) reduce
the incidence of conflicts.

Ultimately the x86 and ARM code was redone to use a table-based approach.  The
MIPS target was left alone, in part because only GPRs were represented to date. 
You don't need to do the same now, but I think a TODO should be added, to at
least consider that in the future.  May be best to defer that until some cross
tests are running.

   assert(unsigned(RegNum) <= Reg_GPR_Last);
   return GPRRegister(RegNum - Reg_GPR_First);
 }
 
+static inline bool isGPRReg(RegNumT RegNum) {
+  return (int(Reg_GPR_First) <= int(RegNum)) && 
+         (unsigned(RegNum) <= Reg_GPR_Last);
+}
+
+static inline FPRRegister getEncodedFPR(RegNumT RegNum) {
+  assert(int(Reg_FPR_First) <= int(RegNum));
+  assert(unsigned(RegNum) <= Reg_FPR_Last);
+  return FPRRegister(RegNum - Reg_FPR_First);
+}
+
+static inline bool isFPRReg(RegNumT RegNum) {
+  return (int(Reg_FPR_First) <= int(RegNum)) && 
+         (unsigned(RegNum) <= Reg_FPR_Last);
+}
+
 const char *getRegName(RegNumT RegNum);
 
 } // end of namespace RegMIPS32
 
 // Extend enum RegClass with MIPS32-specific register classes (if any).
 enum RegClassMIPS32 : uint8_t { RCMIPS32_NUM = RC_Target };
 
 } // end of namespace MIPS32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEREGISTERSMIPS32_H