Subzero, MIPS32: Introduction of floating point registers

src/IceTargetLoweringMIPS32.h

 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 159 matching lines @@
 
   void _br(CfgNode *TargetTrue, CfgNode *TargetFalse, Operand *Src0,
            CondMIPS32::Cond Condition) {
     Context.insert<InstMIPS32Br>(TargetTrue, TargetFalse, Src0, Condition);
   }
 
   void _ret(Variable *RA, Variable *Src0 = nullptr) {
     Context.insert<InstMIPS32Ret>(RA, Src0);
   }
 
+  void _add_d(Variable *Dest, Variable *Src0, Variable *Src1) {
+    Context.insert<InstMIPS32Add_d>(Dest, Src0, Src1);
+  }
+
+  void _add_s(Variable *Dest, Variable *Src0, Variable *Src1) {
+    Context.insert<InstMIPS32Add_s>(Dest, Src0, Src1);
+  }
+
   void _addiu(Variable *Dest, Variable *Src, uint32_t Imm) {
     Context.insert<InstMIPS32Addiu>(Dest, Src, Imm);
   }
 
   void _div(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32Div>(Dest, Src0, Src1);
   }
 
+  void _div_d(Variable *Dest, Variable *Src0, Variable *Src1) {
+    Context.insert<InstMIPS32Div_d>(Dest, Src0, Src1);
+  }
+
+  void _div_s(Variable *Dest, Variable *Src0, Variable *Src1) {
+    Context.insert<InstMIPS32Div_s>(Dest, Src0, Src1);
+  }
+
   void _divu(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32Divu>(Dest, Src0, Src1);
   }
 
   void _lui(Variable *Dest, uint32_t Imm) {
     Context.insert<InstMIPS32Lui>(Dest, Imm);
   }
 
   void _mov(Variable *Dest, Operand *Src0) {
     assert(Dest != nullptr);
     // Variable* Src0_ = llvm::dyn_cast<Variable>(Src0);
     if (llvm::isa<ConstantRelocatable>(Src0)) {
       Context.insert<InstMIPS32La>(Dest, Src0);
     } else {
       auto *Instr = Context.insert<InstMIPS32Mov>(Dest, Src0);
       if (Instr->isMultiDest()) {
         // If Instr is multi-dest, then Dest must be a Variable64On32. We add a
         // fake-def for Instr.DestHi here.
         assert(llvm::isa<Variable64On32>(Dest));
         Context.insert<InstFakeDef>(Instr->getDestHi());
       }
     }
   }
 
+  void _mov_d(Variable *Dest, Variable *Src) {
+    Context.insert<InstMIPS32Mov_d>(Dest, Src);
+  }
+
+  void _mov_s(Variable *Dest, Variable *Src) {
+    Context.insert<InstMIPS32Mov_s>(Dest, Src);
+  }
+
+  void _mfc1(Variable *Dest, Variable *Src) {
+    Context.insert<InstMIPS32Mfc1>(Dest, Src);
+  }
+
   void _mfhi(Variable *Dest, Operand *Src) {
     Context.insert<InstMIPS32Mfhi>(Dest, Src);
   }
 
   void _mflo(Variable *Dest, Operand *Src) {
     Context.insert<InstMIPS32Mflo>(Dest, Src);
   }
 
+  void _mtc1(Variable *Dest, Variable *Src) {
+    Context.insert<InstMIPS32Mtc1>(Dest, Src);
+  }
+
   void _mthi(Variable *Dest, Operand *Src) {
     Context.insert<InstMIPS32Mthi>(Dest, Src);
   }
 
   void _mtlo(Variable *Dest, Operand *Src) {
     Context.insert<InstMIPS32Mtlo>(Dest, Src);
   }
 
   void _mul(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32Mul>(Dest, Src0, Src1);
   }
 
+  void _mul_d(Variable *Dest, Variable *Src0, Variable *Src1) {
+    Context.insert<InstMIPS32Mul_d>(Dest, Src0, Src1);
+  }
+
+  void _mul_s(Variable *Dest, Variable *Src0, Variable *Src1) {
+    Context.insert<InstMIPS32Mul_s>(Dest, Src0, Src1);
+  }
+
   void _mult(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32Mult>(Dest, Src0, Src1);
   }
 
   void _multu(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32Multu>(Dest, Src0, Src1);
   }
 
   void _or(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32Or>(Dest, Src0, Src1);
@@ skipping 40 matching lines @@
   }
 
   void _srlv(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32Srlv>(Dest, Src0, Src1);
   }
 
   void _sub(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32Sub>(Dest, Src0, Src1);
   }
 
+  void _sub_d(Variable *Dest, Variable *Src0, Variable *Src1) {
+    Context.insert<InstMIPS32Sub_d>(Dest, Src0, Src1);
+  }
+
+  void _sub_s(Variable *Dest, Variable *Src0, Variable *Src1) {
+    Context.insert<InstMIPS32Sub_s>(Dest, Src0, Src1);
+  }
+
   void _subu(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32Subu>(Dest, Src0, Src1);
   }
 
   void _xor(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32Xor>(Dest, Src0, Src1);
   }
 
   void _xori(Variable *Dest, Variable *Src, uint32_t Imm) {
     Context.insert<InstMIPS32Xori>(Dest, Src, Imm);
@@ skipping 203 matching lines @@
   explicit TargetHeaderMIPS32(GlobalContext *Ctx);
 
 private:
   ~TargetHeaderMIPS32() = default;
 };
 
 } // end of namespace MIPS32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H