Subzero, MIPS32: Introduction of floating point registers

src/IceInstMIPS32.h

 //===- subzero/src/IceInstMIPS32.h - MIPS32 machine instrs --*- C++ -*-===    //
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 101 matching lines @@
 /// Base class for Mips instructions.
 class InstMIPS32 : public InstTarget {
   InstMIPS32() = delete;
   InstMIPS32(const InstMIPS32 &) = delete;
   InstMIPS32 &operator=(const InstMIPS32 &) = delete;
 
 public:
   enum InstKindMIPS32 {
     k__Start = Inst::Target,
     Add,
+    Add_d,
+    Add_s,
     Addiu,
     Addu,
     And,
     Andi,
     Br,
     Call,
     Div,
+    Div_d,
+    Div_s,
     Divu,
     La,
     Label,
     Lui,
+    Mfc1,
     Mfhi,
     Mflo,
     Mov, // actually a pseudo op for addi rd, rs, 0
+    Mov_d,
+    Mov_s,
+    Mtc1,
     Mthi,
     Mtlo,
     Mul,
+    Mul_d,
+    Mul_s,
     Mult,
     Multu,
     Or,
     Ori,
     Ret,
     Sll,
     Sllv,
     Slt,
     Slti,
     Sltiu,
     Sltu,
     Sra,
     Srav,
     Srl,
     Srlv,
     Sub,
+    Sub_d,
+    Sub_s,
     Subu,
     Xor,
     Xori
   };
 
   static const char *getWidthString(Type Ty);
 
   void dump(const Cfg *Func) const override;
 
   void dumpOpcode(Ostream &Str, const char *Opcode, Type Ty) const {
     Str << Opcode << "." << Ty;
   }
 
   // TODO(rkotler): while branching is not implemented
   bool repointEdges(CfgNode *, CfgNode *) override { return true; }
 
   /// Shared emit routines for common forms of instructions.
   static void emitUnaryopGPR(const char *Opcode, const InstMIPS32 *Inst,
                              const Cfg *Func);
   static void emitUnaryopGPRFLoHi(const char *Opcode, const InstMIPS32 *Inst,
                                   const Cfg *Func);
   static void emitUnaryopGPRTLoHi(const char *Opcode, const InstMIPS32 *Inst,
                                   const Cfg *Func);
+  static void emitTwoAddr(const char *Opcode, const InstMIPS32 *Inst,
+                          const Cfg *Func);
   static void emitThreeAddr(const char *Opcode, const InstMIPS32 *Inst,
                             const Cfg *Func);
   static void emitThreeAddrLoHi(const char *Opcode, const InstMIPS32 *Inst,
                                 const Cfg *Func);
 
 protected:
   InstMIPS32(Cfg *Func, InstKindMIPS32 Kind, SizeT Maxsrcs, Variable *Dest)
       : InstTarget(Func, static_cast<InstKind>(Kind), Maxsrcs, Dest) {}
   static bool isClassof(const Inst *Inst, InstKindMIPS32 MyKind) {
     return Inst->getKind() == static_cast<InstKind>(MyKind);
@@ skipping 64 matching lines @@
 protected:
   InstMIPS32UnaryopGPR(Cfg *Func, Variable *Dest, Operand *Src)
       : InstMIPS32(Func, K, 1, Dest) {
     addSource(Src);
   }
 
 private:
   static const char *Opcode;
 };
 
+/// Instructions of the form opcode reg, reg.
+template <InstMIPS32::InstKindMIPS32 K>
+class InstMIPS32TwoAddrFPR : public InstMIPS32 {
+  InstMIPS32TwoAddrFPR() = delete;
+  InstMIPS32TwoAddrFPR(const InstMIPS32TwoAddrFPR &) = delete;
+  InstMIPS32TwoAddrFPR &operator=(const InstMIPS32TwoAddrFPR &) = delete;
+
+public:
+  static InstMIPS32TwoAddrFPR *create(Cfg *Func, Variable *Dest,
+                                        Variable *Src0) {
+    return new (Func->allocate<InstMIPS32TwoAddrFPR>())
+        InstMIPS32TwoAddrFPR(Func, Dest, Src0);
+  }
+  void emit(const Cfg *Func) const override {
+    if (!BuildDefs::dump())
+      return;
+    emitTwoAddr(Opcode, this, Func);
+  }
+  void emitIAS(const Cfg *Func) const override {
+    (void)Func;
+    llvm_unreachable("Not yet implemented");
+  }
+
+  void dump(const Cfg *Func) const override {
+    if (!BuildDefs::dump())
+      return;
+    Ostream &Str = Func->getContext()->getStrDump();
+    dumpDest(Func);
+    Str << " = ";
+    dumpOpcode(Str, Opcode, getDest()->getType());
+    Str << " ";
+    dumpSources(Func);
+  }
+  static bool classof(const Inst *Inst) { return isClassof(Inst, K); }
+
+private:
+  InstMIPS32TwoAddrFPR(Cfg *Func, Variable *Dest, Variable *Src0)
+      : InstMIPS32(Func, K, 1, Dest) {
+    addSource(Src0);
+  }
+
+  static const char *Opcode;
+};
+
+/// Instructions of the form opcode reg, reg.
+template <InstMIPS32::InstKindMIPS32 K>
+class InstMIPS32TwoAddrGPR : public InstMIPS32 {
+  InstMIPS32TwoAddrGPR() = delete;
+  InstMIPS32TwoAddrGPR(const InstMIPS32TwoAddrGPR &) = delete;
+  InstMIPS32TwoAddrGPR &operator=(const InstMIPS32TwoAddrGPR &) = delete;
+
+public:
+  static InstMIPS32TwoAddrGPR *create(Cfg *Func, Variable *Dest,
+                                        Variable *Src0) {
+    return new (Func->allocate<InstMIPS32TwoAddrGPR>())
+        InstMIPS32TwoAddrGPR(Func, Dest, Src0);
+  }
+  void emit(const Cfg *Func) const override {
+    if (!BuildDefs::dump())
+      return;
+    emitTwoAddr(Opcode, this, Func);
+  }
+  void emitIAS(const Cfg *Func) const override {
+    (void)Func;
+    llvm_unreachable("Not yet implemented");
+  }
+
+  void dump(const Cfg *Func) const override {
+    if (!BuildDefs::dump())
+      return;
+    Ostream &Str = Func->getContext()->getStrDump();
+    dumpDest(Func);
+    Str << " = ";
+    dumpOpcode(Str, Opcode, getDest()->getType());
+    Str << " ";
+    dumpSources(Func);
+  }
+  static bool classof(const Inst *Inst) { return isClassof(Inst, K); }
+
+private:
+  InstMIPS32TwoAddrGPR(Cfg *Func, Variable *Dest, Variable *Src0)
+      : InstMIPS32(Func, K, 1, Dest) {
+    addSource(Src0);
+  }
+
+  static const char *Opcode;
+};
+
 /// Instructions of the form x := y op z. May have the side-effect of setting
 /// status flags.
 template <InstMIPS32::InstKindMIPS32 K>
+class InstMIPS32ThreeAddrFPR : public InstMIPS32 {
+  InstMIPS32ThreeAddrFPR() = delete;
+  InstMIPS32ThreeAddrFPR(const InstMIPS32ThreeAddrFPR &) = delete;
+  InstMIPS32ThreeAddrFPR &operator=(const InstMIPS32ThreeAddrFPR &) = delete;
+
+public:
+  /// Create an ordinary binary-op instruction like add, and sub. Dest and Src1
+  /// must be registers.
+  static InstMIPS32ThreeAddrFPR *create(Cfg *Func, Variable *Dest,
+                                        Variable *Src0, Variable *Src1) {
+    return new (Func->allocate<InstMIPS32ThreeAddrFPR>())
+        InstMIPS32ThreeAddrFPR(Func, Dest, Src0, Src1);
+  }
+  void emit(const Cfg *Func) const override {
+    if (!BuildDefs::dump())
+      return;
+    emitThreeAddr(Opcode, this, Func);
+  }
+  void emitIAS(const Cfg *Func) const override {
+    (void)Func;
+    llvm_unreachable("Not yet implemented");
+  }
+
+  void dump(const Cfg *Func) const override {
+    if (!BuildDefs::dump())
+      return;
+    Ostream &Str = Func->getContext()->getStrDump();
+    dumpDest(Func);
+    Str << " = ";
+    dumpOpcode(Str, Opcode, getDest()->getType());
+    Str << " ";
+    dumpSources(Func);
+  }
+  static bool classof(const Inst *Inst) { return isClassof(Inst, K); }
+
+private:
+  InstMIPS32ThreeAddrFPR(Cfg *Func, Variable *Dest, Variable *Src0,
+                         Variable *Src1)
+      : InstMIPS32(Func, K, 2, Dest) {
+    addSource(Src0);
+    addSource(Src1);
+  }
+
+  static const char *Opcode;
+};
+
+/// Instructions of the form x := y op z. May have the side-effect of setting
+/// status flags.
+template <InstMIPS32::InstKindMIPS32 K>
 class InstMIPS32ThreeAddrGPR : public InstMIPS32 {
   InstMIPS32ThreeAddrGPR() = delete;
   InstMIPS32ThreeAddrGPR(const InstMIPS32ThreeAddrGPR &) = delete;
   InstMIPS32ThreeAddrGPR &operator=(const InstMIPS32ThreeAddrGPR &) = delete;
 
 public:
   /// Create an ordinary binary-op instruction like add, and sub. Dest and Src1
   /// must be registers.
   static InstMIPS32ThreeAddrGPR *create(Cfg *Func, Variable *Dest,
                                         Variable *Src0, Variable *Src1) {
@@ skipping 216 matching lines @@
 
   InstMIPS32Imm16(Cfg *Func, Variable *Dest, uint32_t Imm)
       : InstMIPS32(Func, K, 0, Dest), Imm(Imm) {}
 
   static const char *Opcode;
 
   const uint32_t Imm;
 };
 
 using InstMIPS32Add = InstMIPS32ThreeAddrGPR<InstMIPS32::Add>;
+using InstMIPS32Add_d = InstMIPS32ThreeAddrFPR<InstMIPS32::Add_d>;
+using InstMIPS32Add_s = InstMIPS32ThreeAddrFPR<InstMIPS32::Add_s>;
 using InstMIPS32Addu = InstMIPS32ThreeAddrGPR<InstMIPS32::Addu>;
 using InstMIPS32Addiu = InstMIPS32Imm16<InstMIPS32::Addiu, true>;
 using InstMIPS32And = InstMIPS32ThreeAddrGPR<InstMIPS32::And>;
 using InstMIPS32Andi = InstMIPS32Imm16<InstMIPS32::Andi>;
 using InstMIPS32Div = InstMIPS32ThreeAddrGPR<InstMIPS32::Div>;
+using InstMIPS32Div_d = InstMIPS32ThreeAddrFPR<InstMIPS32::Div_d>;
+using InstMIPS32Div_s = InstMIPS32ThreeAddrFPR<InstMIPS32::Div_s>;
 using InstMIPS32Divu = InstMIPS32ThreeAddrGPR<InstMIPS32::Divu>;
 using InstMIPS32Lui = InstMIPS32Imm16<InstMIPS32::Lui>;
 using InstMIPS32La = InstMIPS32UnaryopGPR<InstMIPS32::La>;
+using InstMIPS32Mfc1 = InstMIPS32TwoAddrGPR<InstMIPS32::Mfc1>;
 using InstMIPS32Mfhi = InstMIPS32UnaryopGPR<InstMIPS32::Mfhi>;
 using InstMIPS32Mflo = InstMIPS32UnaryopGPR<InstMIPS32::Mflo>;
+using InstMIPS32Mov_d = InstMIPS32TwoAddrFPR<InstMIPS32::Mov_d>;
+using InstMIPS32Mov_s = InstMIPS32TwoAddrFPR<InstMIPS32::Mov_s>;
+using InstMIPS32Mtc1 = InstMIPS32TwoAddrGPR<InstMIPS32::Mtc1>;
 using InstMIPS32Mthi = InstMIPS32UnaryopGPR<InstMIPS32::Mthi>;
 using InstMIPS32Mtlo = InstMIPS32UnaryopGPR<InstMIPS32::Mtlo>;
 using InstMIPS32Mul = InstMIPS32ThreeAddrGPR<InstMIPS32::Mul>;
+using InstMIPS32Mul_d = InstMIPS32ThreeAddrFPR<InstMIPS32::Mul_d>;
+using InstMIPS32Mul_s = InstMIPS32ThreeAddrFPR<InstMIPS32::Mul_s>;
 using InstMIPS32Mult = InstMIPS32ThreeAddrGPR<InstMIPS32::Mult>;
 using InstMIPS32Multu = InstMIPS32ThreeAddrGPR<InstMIPS32::Multu>;
 using InstMIPS32Or = InstMIPS32ThreeAddrGPR<InstMIPS32::Or>;
 using InstMIPS32Ori = InstMIPS32Imm16<InstMIPS32::Ori>;
 using InstMIPS32Sll = InstMIPS32Imm16<InstMIPS32::Sll>;
 using InstMIPS32Sllv = InstMIPS32ThreeAddrGPR<InstMIPS32::Sllv>;
 using InstMIPS32Slt = InstMIPS32ThreeAddrGPR<InstMIPS32::Slt>;
 using InstMIPS32Slti = InstMIPS32Imm16<InstMIPS32::Slti>;
 using InstMIPS32Sltiu = InstMIPS32Imm16<InstMIPS32::Sltiu>;
 using InstMIPS32Sltu = InstMIPS32ThreeAddrGPR<InstMIPS32::Sltu>;
 using InstMIPS32Sra = InstMIPS32Imm16<InstMIPS32::Sra>;
 using InstMIPS32Srav = InstMIPS32ThreeAddrGPR<InstMIPS32::Srav>;
 using InstMIPS32Srl = InstMIPS32Imm16<InstMIPS32::Srl>;
 using InstMIPS32Srlv = InstMIPS32ThreeAddrGPR<InstMIPS32::Srlv>;
 using InstMIPS32Sub = InstMIPS32ThreeAddrGPR<InstMIPS32::Sub>;
+using InstMIPS32Sub_d = InstMIPS32ThreeAddrFPR<InstMIPS32::Sub_d>;
+using InstMIPS32Sub_s = InstMIPS32ThreeAddrFPR<InstMIPS32::Sub_s>;
 using InstMIPS32Subu = InstMIPS32ThreeAddrGPR<InstMIPS32::Subu>;
 using InstMIPS32Ori = InstMIPS32Imm16<InstMIPS32::Ori>;
 using InstMIPS32Xor = InstMIPS32ThreeAddrGPR<InstMIPS32::Xor>;
 using InstMIPS32Xori = InstMIPS32Imm16<InstMIPS32::Xori>;
 
 /// Handles (some of) vmov's various formats.
 class InstMIPS32Mov final : public InstMIPS32 {
   InstMIPS32Mov() = delete;
   InstMIPS32Mov(const InstMIPS32Mov &) = delete;
   InstMIPS32Mov &operator=(const InstMIPS32Mov &) = delete;
@@ skipping 39 matching lines @@
 template <> void InstMIPS32Mfhi::emit(const Cfg *Func) const;
 template <> void InstMIPS32Mtlo::emit(const Cfg *Func) const;
 template <> void InstMIPS32Mthi::emit(const Cfg *Func) const;
 template <> void InstMIPS32Mult::emit(const Cfg *Func) const;
 template <> void InstMIPS32Multu::emit(const Cfg *Func) const;
 
 } // end of namespace MIPS32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTMIPS32_H