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Side by Side Diff: src/IceInstMIPS32.cpp

Issue 1993993004: Subzero, MIPS32: Introduction of floating point registers (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Added floating point register pairs Created 4 years, 6 months ago
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1 //===- subzero/src/IceInstMips32.cpp - Mips32 instruction implementation --===// 1 //===- subzero/src/IceInstMips32.cpp - Mips32 instruction implementation --===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 /// \file 10 /// \file
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58 const char *InstMIPS32::getWidthString(Type Ty) { 58 const char *InstMIPS32::getWidthString(Type Ty) {
59 (void)Ty; 59 (void)Ty;
60 return "TBD"; 60 return "TBD";
61 } 61 }
62 62
63 template <> const char *InstMIPS32Addiu::Opcode = "addiu"; 63 template <> const char *InstMIPS32Addiu::Opcode = "addiu";
64 template <> const char *InstMIPS32Lui::Opcode = "lui"; 64 template <> const char *InstMIPS32Lui::Opcode = "lui";
65 template <> const char *InstMIPS32La::Opcode = "la"; 65 template <> const char *InstMIPS32La::Opcode = "la";
66 // Three-addr ops 66 // Three-addr ops
67 template <> const char *InstMIPS32Add::Opcode = "add"; 67 template <> const char *InstMIPS32Add::Opcode = "add";
68 template <> const char *InstMIPS32Add_d::Opcode = "add.d";
69 template <> const char *InstMIPS32Add_s::Opcode = "add.s";
68 template <> const char *InstMIPS32Addu::Opcode = "addu"; 70 template <> const char *InstMIPS32Addu::Opcode = "addu";
69 template <> const char *InstMIPS32And::Opcode = "and"; 71 template <> const char *InstMIPS32And::Opcode = "and";
70 template <> const char *InstMIPS32Andi::Opcode = "andi"; 72 template <> const char *InstMIPS32Andi::Opcode = "andi";
71 template <> const char *InstMIPS32Div::Opcode = "div"; 73 template <> const char *InstMIPS32Div::Opcode = "div";
74 template <> const char *InstMIPS32Div_d::Opcode = "div.d";
75 template <> const char *InstMIPS32Div_s::Opcode = "div.s";
72 template <> const char *InstMIPS32Divu::Opcode = "divu"; 76 template <> const char *InstMIPS32Divu::Opcode = "divu";
77 template <> const char *InstMIPS32Mfc1::Opcode = "mfc1";
73 template <> const char *InstMIPS32Mfhi::Opcode = "mfhi"; 78 template <> const char *InstMIPS32Mfhi::Opcode = "mfhi";
74 template <> const char *InstMIPS32Mflo::Opcode = "mflo"; 79 template <> const char *InstMIPS32Mflo::Opcode = "mflo";
80 template <> const char *InstMIPS32Mov_d::Opcode = "mov.d";
81 template <> const char *InstMIPS32Mov_s::Opcode = "mov.s";
82 template <> const char *InstMIPS32Mtc1::Opcode = "mtc1";
75 template <> const char *InstMIPS32Mthi::Opcode = "mthi"; 83 template <> const char *InstMIPS32Mthi::Opcode = "mthi";
76 template <> const char *InstMIPS32Mtlo::Opcode = "mtlo"; 84 template <> const char *InstMIPS32Mtlo::Opcode = "mtlo";
77 template <> const char *InstMIPS32Mul::Opcode = "mul"; 85 template <> const char *InstMIPS32Mul::Opcode = "mul";
86 template <> const char *InstMIPS32Mul_d::Opcode = "mul.d";
87 template <> const char *InstMIPS32Mul_s::Opcode = "mul.s";
78 template <> const char *InstMIPS32Mult::Opcode = "mult"; 88 template <> const char *InstMIPS32Mult::Opcode = "mult";
79 template <> const char *InstMIPS32Multu::Opcode = "multu"; 89 template <> const char *InstMIPS32Multu::Opcode = "multu";
80 template <> const char *InstMIPS32Or::Opcode = "or"; 90 template <> const char *InstMIPS32Or::Opcode = "or";
81 template <> const char *InstMIPS32Ori::Opcode = "ori"; 91 template <> const char *InstMIPS32Ori::Opcode = "ori";
82 template <> const char *InstMIPS32Sll::Opcode = "sll"; 92 template <> const char *InstMIPS32Sll::Opcode = "sll";
83 template <> const char *InstMIPS32Sllv::Opcode = "sllv"; 93 template <> const char *InstMIPS32Sllv::Opcode = "sllv";
84 template <> const char *InstMIPS32Slt::Opcode = "slt"; 94 template <> const char *InstMIPS32Slt::Opcode = "slt";
85 template <> const char *InstMIPS32Slti::Opcode = "slti"; 95 template <> const char *InstMIPS32Slti::Opcode = "slti";
86 template <> const char *InstMIPS32Sltiu::Opcode = "sltiu"; 96 template <> const char *InstMIPS32Sltiu::Opcode = "sltiu";
87 template <> const char *InstMIPS32Sltu::Opcode = "sltu"; 97 template <> const char *InstMIPS32Sltu::Opcode = "sltu";
88 template <> const char *InstMIPS32Sra::Opcode = "sra"; 98 template <> const char *InstMIPS32Sra::Opcode = "sra";
89 template <> const char *InstMIPS32Srav::Opcode = "srav"; 99 template <> const char *InstMIPS32Srav::Opcode = "srav";
90 template <> const char *InstMIPS32Srl::Opcode = "srl"; 100 template <> const char *InstMIPS32Srl::Opcode = "srl";
91 template <> const char *InstMIPS32Srlv::Opcode = "srlv"; 101 template <> const char *InstMIPS32Srlv::Opcode = "srlv";
92 template <> const char *InstMIPS32Sub::Opcode = "sub"; 102 template <> const char *InstMIPS32Sub::Opcode = "sub";
103 template <> const char *InstMIPS32Sub_d::Opcode = "sub.d";
104 template <> const char *InstMIPS32Sub_s::Opcode = "sub.s";
93 template <> const char *InstMIPS32Subu::Opcode = "subu"; 105 template <> const char *InstMIPS32Subu::Opcode = "subu";
94 template <> const char *InstMIPS32Xor::Opcode = "xor"; 106 template <> const char *InstMIPS32Xor::Opcode = "xor";
95 template <> const char *InstMIPS32Xori::Opcode = "xori"; 107 template <> const char *InstMIPS32Xori::Opcode = "xori";
96 108
97 template <> void InstMIPS32Mflo::emit(const Cfg *Func) const { 109 template <> void InstMIPS32Mflo::emit(const Cfg *Func) const {
98 if (!BuildDefs::dump()) 110 if (!BuildDefs::dump())
99 return; 111 return;
100 emitUnaryopGPRFLoHi(Opcode, this, Func); 112 emitUnaryopGPRFLoHi(Opcode, this, Func);
101 } 113 }
102 114
(...skipping 168 matching lines...) Expand 10 before | Expand all | Expand 10 after
271 Ostream &Str = Func->getContext()->getStrEmit(); 283 Ostream &Str = Func->getContext()->getStrEmit();
272 assert(Inst->getSrcSize() == 2); 284 assert(Inst->getSrcSize() == 2);
273 Str << "\t" << Opcode << "\t"; 285 Str << "\t" << Opcode << "\t";
274 Inst->getDest()->emit(Func); 286 Inst->getDest()->emit(Func);
275 Str << ", "; 287 Str << ", ";
276 Inst->getSrc(0)->emit(Func); 288 Inst->getSrc(0)->emit(Func);
277 Str << ", "; 289 Str << ", ";
278 Inst->getSrc(1)->emit(Func); 290 Inst->getSrc(1)->emit(Func);
279 } 291 }
280 292
293 void InstMIPS32::emitTwoAddr(const char *Opcode, const InstMIPS32 *Inst,
294 const Cfg *Func) {
295 if (!BuildDefs::dump())
296 return;
297 Ostream &Str = Func->getContext()->getStrEmit();
298 assert(Inst->getSrcSize() == 1);
299 Str << "\t" << Opcode << "\t";
300 Inst->getDest()->emit(Func);
301 Str << ", ";
302 Inst->getSrc(0)->emit(Func);
303 }
304
281 void InstMIPS32::emitThreeAddrLoHi(const char *Opcode, const InstMIPS32 *Inst, 305 void InstMIPS32::emitThreeAddrLoHi(const char *Opcode, const InstMIPS32 *Inst,
282 const Cfg *Func) { 306 const Cfg *Func) {
283 if (!BuildDefs::dump()) 307 if (!BuildDefs::dump())
284 return; 308 return;
285 Ostream &Str = Func->getContext()->getStrEmit(); 309 Ostream &Str = Func->getContext()->getStrEmit();
286 assert(Inst->getSrcSize() == 2); 310 assert(Inst->getSrcSize() == 2);
287 Str << "\t" << Opcode << "\t"; 311 Str << "\t" << Opcode << "\t";
288 Inst->getSrc(0)->emit(Func); 312 Inst->getSrc(0)->emit(Func);
289 Str << ", "; 313 Str << ", ";
290 Inst->getSrc(1)->emit(Func); 314 Inst->getSrc(1)->emit(Func);
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530 } 554 }
531 555
532 Str << "\t"; 556 Str << "\t";
533 getDest()->emit(Func); 557 getDest()->emit(Func);
534 Str << ", "; 558 Str << ", ";
535 getSrc(0)->emit(Func); 559 getSrc(0)->emit(Func);
536 } 560 }
537 561
538 } // end of namespace MIPS32 562 } // end of namespace MIPS32
539 } // end of namespace Ice 563 } // end of namespace Ice
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