[Subzero][MIPS32] Addition of bool folding machinery and implementation of conditional branches

tests_lit/llvm2ice_tests/cond-branch.ll

Index: tests_lit/llvm2ice_tests/cond-branch.ll
diff --git a/tests_lit/llvm2ice_tests/cond-branch.ll b/tests_lit/llvm2ice_tests/cond-branch.ll
new file mode 100644
index 0000000000000000000000000000000000000000..f9978a86d81d719f487da1130dfa2824dbb74877
--- /dev/null
+++ b/tests_lit/llvm2ice_tests/cond-branch.ll
@@ -0,0 +1,167 @@
+; Tests for conditional branch instructions
+
+; RUN: %if --need=allow_dump --need=target_MIPS32 --command %p2i \
+; RUN:   --filetype=asm --target mips32 -i %s --args -O2 --skip-unimplemented \
+; RUN:   -allow-externally-defined-symbols \
+; RUN:   | %if --need=allow_dump --need=target_MIPS32 --command FileCheck %s \
+; RUN:   --check-prefix=MIPS32
+
+; RUN: %if --need=allow_dump --need=target_MIPS32 --command %p2i \
+; RUN:   --filetype=asm --target mips32 -i %s --args -Om1 --skip-unimplemented \
+; RUN:   -allow-externally-defined-symbols \
+; RUN:   | %if --need=allow_dump --need=target_MIPS32 --command FileCheck %s \
+; RUN:   --check-prefix=MIPS32-OM1
+
+define internal i32 @cond_br_eq(i32 %arg1, i32 %arg2) {
+entry:
+  %cmp1 = icmp eq i32 %arg1, %arg2
+  br i1 %cmp1, label %branch1, label %branch2
+branch1:
+  ret i32 1
+branch2:
+  ret i32 2
+}
+; MIPS32-LABEL: cond_br_eq
+; MIPS32: bne $a0, $a1, .Lcond_br_eq$branch2
+; MIPS32-OM1: xor $v0, $v0, $v1

[Jim Stichnoth, 2016/05/23 19:53:06]

You'll want to do something like:

; MIPS32-OM1-LABEL: cond_br_eq

here and below, to guarantee the same level of test synchronization as the O2
tests.

Another approach is to use two --check-prefix options for each test, one for the
common patterns and one for this tests's specific patterns.  E.g.:

; RUN: ... --check-prefix=COMMON --check-prefix=MIPS32
; RUN: ... --check-prefix=COMMON --check-prefix=MIPS32-OM1

; COMMON-LABEL: cond_br_eq
; MIPS32: bne ...
; MIPS32-OM1: xor ...

[sagar.thakur, 2016/05/24 05:44:36]

Done.

+; MIPS32-OM1: sltiu $v0, $v0, 1
+; MIPS32-OM1: beqz $v0, .Lcond_br_eq$branch2
+
+define internal i32 @cond_br_ne(i32 %arg1, i32 %arg2) {
+entry:
+  %cmp1 = icmp ne i32 %arg1, %arg2
+  br i1 %cmp1, label %branch1, label %branch2
+branch1:
+  ret i32 1
+branch2:
+  ret i32 2
+}
+; MIPS32-LABEL: cond_br_ne
+; MIPS32: beq $a0, $a1, .Lcond_br_ne$branch2
+; MIPS32-OM1: xor $v0, $v0, $v1

[Jim Stichnoth, 2016/05/23 19:53:05]

Looking ahead, you may not want to hard-code register values quite so much into
the tests.  The issue is that if something later changes in the target lowering
or in the register allocator, the register assignments might change and then you
have to go and fix a bunch of "broken" tests.

In tests like this on other targets, we often just limit checking to the opcode,
unless perhaps there's a particular immediate value of interest.

[sagar.thakur, 2016/05/24 05:44:36]

Done.

+; MIPS32-OM1: sltu $v0, $zero, $v0
+; MIPS32-OM1: beqz $v0, .Lcond_br_ne$branch2
+
+define internal i32 @cond_br_slt(i32 %arg1, i32 %arg2) {
+entry:
+  %cmp1 = icmp slt i32 %arg1, %arg2
+  br i1 %cmp1, label %branch1, label %branch2
+branch1:
+  ret i32 1
+branch2:
+  ret i32 2
+}
+; MIPS32-LABEL: cond_br_slt
+; MIPS32: slt $a0, $a0, $a1
+; MIPS32: beqz $a0, .Lcond_br_slt$branch2
+; MIPS32-OM1: slt $v0, $v0, $v1
+; MIPS32-OM1: beqz $v0, .Lcond_br_slt$branch2
+
+define internal i32 @cond_br_sle(i32 %arg1, i32 %arg2) {
+entry:
+  %cmp1 = icmp sle i32 %arg1, %arg2
+  br i1 %cmp1, label %branch1, label %branch2
+branch1:
+  ret i32 1
+branch2:
+  ret i32 2
+}
+; MIPS32-LABEL: cond_br_sle
+; MIPS32: slt $a1, $a1, $a0
+; MIPS32: bnez $a1, .Lcond_br_sle$branch2
+; MIPS32-OM1: slt $v0, $v1, $v0
+; MIPS32-OM1: xori $v0, $v0, 1
+; MIPS32-OM1: beqz $v0, .Lcond_br_sle$branch2
+
+define internal i32 @cond_br_sgt(i32 %arg1, i32 %arg2) {
+entry:
+  %cmp1 = icmp sgt i32 %arg1, %arg2
+  br i1 %cmp1, label %branch1, label %branch2
+branch1:
+  ret i32 1
+branch2:
+  ret i32 2
+}
+; MIPS32-LABEL: cond_br_sgt
+; MIPS32: slt $a1, $a1, $a0
+; MIPS32: beqz $a1, .Lcond_br_sgt$branch2
+; MIPS32-OM1: slt $v0, $v1, $v0
+; MIPS32-OM1: beqz $v0, .Lcond_br_sgt$branch2
+
+define internal i32 @cond_br_sge(i32 %arg1, i32 %arg2) {
+entry:
+  %cmp1 = icmp sge i32 %arg1, %arg2
+  br i1 %cmp1, label %branch1, label %branch2
+branch1:
+  ret i32 1
+branch2:
+  ret i32 2
+}
+; MIPS32-LABEL: cond_br_sge
+; MIPS32: slt $a0, $a0, $a1
+; MIPS32: bnez $a0, .Lcond_br_sge$branch2
+; MIPS32-OM1: slt $v0, $v0, $v1
+; MIPS32-OM1: xori $v0, $v0, 1
+; MIPS32-OM1: beqz $v0, .Lcond_br_sge$branch2
+
+define internal i32 @cond_br_ugt(i32 %arg1, i32 %arg2) {
+entry:
+  %cmp1 = icmp ugt i32 %arg1, %arg2
+  br i1 %cmp1, label %branch1, label %branch2
+branch1:
+  ret i32 1
+branch2:
+  ret i32 2
+}
+; MIPS32-LABEL: cond_br_ugt
+; MIPS32: sltu $a1, $a1, $a0
+; MIPS32: beqz $a1, .Lcond_br_ugt$branch2
+; MIPS32-OM1: sltu $v0, $v1, $v0
+; MIPS32-OM1: beqz $v0, .Lcond_br_ugt$branch2
+
+define internal i32 @cond_br_uge(i32 %arg1, i32 %arg2) {
+entry:
+  %cmp1 = icmp uge i32 %arg1, %arg2
+  br i1 %cmp1, label %branch1, label %branch2
+branch1:
+  ret i32 1
+branch2:
+  ret i32 2
+}
+; MIPS32-LABEL: cond_br_uge
+; MIPS32: sltu $a0, $a0, $a1
+; MIPS32: bnez $a0, .Lcond_br_uge$branch2
+; MIPS32-OM1: sltu $v0, $v0, $v1
+; MIPS32-OM1: xori $v0, $v0, 1
+; MIPS32-OM1: beqz $v0, .Lcond_br_uge$branch2
+
+define internal i32 @cond_br_ult(i32 %arg1, i32 %arg2) {
+entry:
+  %cmp1 = icmp ult i32 %arg1, %arg2
+  br i1 %cmp1, label %branch1, label %branch2
+branch1:
+  ret i32 1
+branch2:
+  ret i32 2
+}
+; MIPS32-LABEL: cond_br_ult
+; MIPS32: sltu $a0, $a0, $a1
+; MIPS32: beqz $a0, .Lcond_br_ult$branch2
+; MIPS32-OM1: sltu $v0, $v0, $v1
+; MIPS32-OM1: beqz $v0, .Lcond_br_ult$branch2
+
+define internal i32 @cond_br_ule(i32 %arg1, i32 %arg2) {
+entry:
+  %cmp1 = icmp ule i32 %arg1, %arg2
+  br i1 %cmp1, label %branch1, label %branch2
+branch1:
+  ret i32 1
+branch2:
+  ret i32 2
+}
+; MIPS32-LABEL: cond_br_ule
+; MIPS32: sltu $a1, $a1, $a0
+; MIPS32: bnez $a1, .Lcond_br_ule$branch2
+; MIPS32-OM1: sltu $v0, $v1, $v0
+; MIPS32-OM1: xori $v0, $v0, 1
+; MIPS32-OM1: beqz $v0, .Lcond_br_ule$branch2