[Subzero][MIPS32] Addition of bool folding machinery and implementation of conditional branches

tests_lit/llvm2ice_tests/cond-branch.ll

+; Tests for conditional branch instructions
+
+; RUN: %if --need=allow_dump --need=target_MIPS32 --command %p2i --filetype=asm \

[John, 2016/05/19 14:59:59]

80-col

[Jim Stichnoth, 2016/05/19 15:03:41]

80-col

+; RUN:   --target mips32 -i %s --args -O2 --skip-unimplemented \
+; RUN:   -allow-externally-defined-symbols \
+; RUN:   | %if --need=allow_dump --need=target_MIPS32 --command FileCheck %s \
+; RUN:   --check-prefix=MIPS32
+
+define internal i32 @cond_br_eq(i32 %arg1, i32 %arg2) {
+entry:
+  %cmp1 = icmp eq i32 %arg1, %arg2
+  br i1 %cmp1, label %branch1, label %branch2
+branch1:
+  ret i32 1
+branch2:
+  ret i32 2
+}
+; MIPS32-LABEL: cond_br_eq
+; MIPS32: bne $a0, $a1, .Lcond_br_eq$branch2

[Jim Stichnoth, 2016/05/19 15:03:41]

I think you also need tests where branch folding is *not* done.  E.g., this
happens when the LLVM br instruction is not known to be the last use of the
instruction's i1 operand.

An easy way to trigger this is to do another RUN with -Om1 instead of -O2,
because then liveness analysis is not run and so last-use info is not computed.

Actually, it seems to me that the whole bool-folding prepass should be
suppressed with Om1, but neither of the other targets are doing that, so it can
be addressed separately.

+
+define internal i32 @cond_br_ne(i32 %arg1, i32 %arg2) {
+entry:
+  %cmp1 = icmp ne i32 %arg1, %arg2
+  br i1 %cmp1, label %branch1, label %branch2
+branch1:
+  ret i32 1
+branch2:
+  ret i32 2
+}
+; MIPS32-LABEL: cond_br_ne
+; MIPS32: beq $a0, $a1, .Lcond_br_ne$branch2
+
+define internal i32 @cond_br_slt(i32 %arg1, i32 %arg2) {
+entry:
+  %cmp1 = icmp slt i32 %arg1, %arg2
+  br i1 %cmp1, label %branch1, label %branch2
+branch1:
+  ret i32 1
+branch2:
+  ret i32 2
+}
+; MIPS32-LABEL: cond_br_slt
+; MIPS32: slt $a0, $a0, $a1
+; MIPS32: beqz $a0, .Lcond_br_slt$branch2
+
+define internal i32 @cond_br_sle(i32 %arg1, i32 %arg2) {
+entry:
+  %cmp1 = icmp sle i32 %arg1, %arg2
+  br i1 %cmp1, label %branch1, label %branch2
+branch1:
+  ret i32 1
+branch2:
+  ret i32 2
+}
+; MIPS32-LABEL: cond_br_sle
+; MIPS32: slt $a1, $a1, $a0
+; MIPS32: bnez $a1, .Lcond_br_sle$branch2
+
+define internal i32 @cond_br_sgt(i32 %arg1, i32 %arg2) {
+entry:
+  %cmp1 = icmp sgt i32 %arg1, %arg2
+  br i1 %cmp1, label %branch1, label %branch2
+branch1:
+  ret i32 1
+branch2:
+  ret i32 2
+}
+; MIPS32-LABEL: cond_br_sgt
+; MIPS32: slt $a1, $a1, $a0
+; MIPS32: beqz $a1, .Lcond_br_sgt$branch2
+
+define internal i32 @cond_br_sge(i32 %arg1, i32 %arg2) {
+entry:
+  %cmp1 = icmp sge i32 %arg1, %arg2
+  br i1 %cmp1, label %branch1, label %branch2
+branch1:
+  ret i32 1
+branch2:
+  ret i32 2
+}
+; MIPS32-LABEL: cond_br_sge
+; MIPS32: slt $a0, $a0, $a1
+; MIPS32: bnez $a0, .Lcond_br_sge$branch2
+
+define internal i32 @cond_br_ugt(i32 %arg1, i32 %arg2) {
+entry:
+  %cmp1 = icmp ugt i32 %arg1, %arg2
+  br i1 %cmp1, label %branch1, label %branch2
+branch1:
+  ret i32 1
+branch2:
+  ret i32 2
+}
+; MIPS32-LABEL: cond_br_ugt
+; MIPS32: sltu $a1, $a1, $a0
+; MIPS32: beqz $a1, .Lcond_br_ugt$branch2
+
+define internal i32 @cond_br_uge(i32 %arg1, i32 %arg2) {
+entry:
+  %cmp1 = icmp uge i32 %arg1, %arg2
+  br i1 %cmp1, label %branch1, label %branch2
+branch1:
+  ret i32 1
+branch2:
+  ret i32 2
+}
+; MIPS32-LABEL: cond_br_uge
+; MIPS32: sltu $a0, $a0, $a1
+; MIPS32: bnez $a0, .Lcond_br_uge$branch2
+
+define internal i32 @cond_br_ult(i32 %arg1, i32 %arg2) {
+entry:
+  %cmp1 = icmp ult i32 %arg1, %arg2
+  br i1 %cmp1, label %branch1, label %branch2
+branch1:
+  ret i32 1
+branch2:
+  ret i32 2
+}
+; MIPS32-LABEL: cond_br_ult
+; MIPS32: sltu $a0, $a0, $a1
+; MIPS32: beqz $a0, .Lcond_br_ult$branch2
+
+define internal i32 @cond_br_ule(i32 %arg1, i32 %arg2) {
+entry:
+  %cmp1 = icmp ule i32 %arg1, %arg2
+  br i1 %cmp1, label %branch1, label %branch2
+branch1:
+  ret i32 1
+branch2:
+  ret i32 2
+}
+; MIPS32-LABEL: cond_br_ule
+; MIPS32: sltu $a1, $a1, $a0
+; MIPS32: bnez $a1, .Lcond_br_ule$branch2