Enable optimizer pipeline for DBC.

runtime/vm/flow_graph_allocator.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/flow_graph_allocator.h"
 
 #include "vm/bit_vector.h"
 #include "vm/intermediate_language.h"
 #include "vm/il_printer.h"
 #include "vm/flow_graph.h"
@@ skipping 134 matching lines @@
 
     BitVector* kill = kill_[i];
     BitVector* live_in = live_in_[i];
 
     // Iterate backwards starting at the last instruction.
     for (BackwardInstructionIterator it(block); !it.Done(); it.Advance()) {
       Instruction* current = it.Current();
 
       // Initialize location summary for instruction.
       current->InitializeLocationSummary(zone(), true);  // opt
+#if defined(TARGET_ARCH_DBC)
+      // TODO(vegorov) remove this once we have ported all necessary
+      // instructions to DBC.
+      if (!current->HasLocs()) {
+        graph_entry_->parsed_function().Bailout("SSALivenessAnalysis",
+                                                current->ToCString());
+      }
+#endif
+
       LocationSummary* locs = current->locs();
 #if defined(DEBUG)
       locs->DiscoverWritableInputs();
 #endif
 
       // Handle definitions.
       Definition* current_def = current->AsDefinition();
       if ((current_def != NULL) && current_def->HasSSATemp()) {
         kill->Add(current_def->ssa_temp_index());
         live_in->Remove(current_def->ssa_temp_index());
@@ skipping 426 matching lines @@
           range->MarkHasOnlyUnconstrainedUsesInLoop(block_info->loop_id());
         }
       }
     }
 
     if (block->IsJoinEntry()) {
       ConnectIncomingPhiMoves(block->AsJoinEntry());
     } else if (block->IsCatchBlockEntry()) {
       // Process initial definitions.
       CatchBlockEntryInstr* catch_entry = block->AsCatchBlockEntry();
+#if defined(TARGET_ARCH_DBC)
+      // TODO(vegorov) support try-catch/finally for DBC.
+      flow_graph_.parsed_function().Bailout("FlowGraphAllocator", "Catch");
+#endif
       for (intptr_t i = 0;
            i < catch_entry->initial_definitions()->length();
            i++) {
         Definition* defn = (*catch_entry->initial_definitions())[i];
         LiveRange* range = GetLiveRange(defn->ssa_temp_index());
         range->DefineAt(catch_entry->start_pos());  // Defined at block entry.
         ProcessInitialDefinition(defn, range, catch_entry);
       }
       // Block the two fixed registers used by CatchBlockEntryInstr from the
       // block start to until the end of the instruction so that they are
@@ skipping 34 matching lines @@
     ASSERT((flow_graph_.num_copied_params() == 0) ||
            (flow_graph_.num_non_copied_params() == 0));
     intptr_t slot_index = param->index();
     ASSERT((param->base_reg() == FPREG) || (param->base_reg() == SPREG));
     if (param->base_reg() == FPREG) {
       // Slot index for the leftmost copied parameter is 0.
       // Slot index for the rightmost fixed parameter is -1.
       slot_index -= flow_graph_.num_non_copied_params();
     }
 
+#if defined(TARGET_ARCH_DBC)
+    ASSERT(param->base_reg() == FPREG);
+    if (slot_index >= 0) {
+      AssignSafepoints(defn, range);
+      range->finger()->Initialize(range);
+      range->set_assigned_location(Location::RegisterLocation(slot_index));
+      if (range->End() > kNormalEntryPos) {
+        LiveRange* tail = range->SplitAt(kNormalEntryPos);
+        CompleteRange(tail, Location::kRegister);
+      }
+      ConvertAllUses(range);
+      return;
+    }
+#endif  // defined(TARGET_ARCH_DBC)
     range->set_assigned_location(Location::StackSlot(slot_index,
                                                      param->base_reg()));
     range->set_spill_slot(Location::StackSlot(slot_index,
                                               param->base_reg()));
+
   } else if (defn->IsCurrentContext()) {
+#if !defined(TARGET_ARCH_DBC)
+    const Register context_reg = CTX;
+#else
+    const intptr_t context_reg = flow_graph_.num_copied_params();
+#endif
+
     AssignSafepoints(defn, range);
     range->finger()->Initialize(range);
-    range->set_assigned_location(Location::RegisterLocation(CTX));
+    range->set_assigned_location(Location::RegisterLocation(context_reg));
     if (range->End() > kNormalEntryPos) {
       LiveRange* tail = range->SplitAt(kNormalEntryPos);
       CompleteRange(tail, Location::kRegister);
     }
     ConvertAllUses(range);
     return;
   } else {
     ConstantInstr* constant = defn->AsConstant();
     ASSERT(constant != NULL);
     range->set_assigned_location(Location::Constant(constant));
@@ skipping 643 matching lines @@
     } else if (temp.IsUnallocated()) {
       LiveRange* range = MakeLiveRangeForTemporary();
       range->AddUseInterval(pos, pos + 1);
       range->AddUse(pos, locs->temp_slot(j));
       CompleteRange(range, RegisterKindFromPolicy(temp));
     } else {
       UNREACHABLE();
     }
   }
 
-  // Block all allocatable registers for calls and record the stack bitmap.
+  // Block all allocatable registers for calls.
+  // Note that on DBC registers are always essentially spilled so
+  // we don't need to block anything.
+#if !defined(TARGET_ARCH_DBC)
   if (locs->always_calls()) {
     // Expected shape of live range:
     //
     //              i  i'
     //              [--)
     //
     // The stack bitmap describes the position i.
     for (intptr_t reg = 0; reg < kNumberOfCpuRegisters; reg++) {
       BlockLocation(Location::RegisterLocation(static_cast<Register>(reg)),
                     pos,
@@ skipping 29 matching lines @@
 
     if (locs->out(0).IsPairLocation()) {
       PairLocation* pair = locs->out_slot(0)->AsPairLocation();
       ASSERT(!pair->At(0).IsUnallocated());
       ASSERT(!pair->At(1).IsUnallocated());
     } else {
       ASSERT(!locs->out(0).IsUnallocated());
     }
 #endif
   }
+#endif
 
   if (locs->can_call()) {
     safepoints_.Add(current);
   }
 
   if (def == NULL) {
     ASSERT(locs->out(0).IsInvalid());
     return;
   }
 
@@ skipping 513 matching lines @@
                             from));
     }
   }
 
   LiveRange* tail = range->SplitAt(from);
   Spill(tail);
 }
 
 
 void FlowGraphAllocator::AllocateSpillSlotFor(LiveRange* range) {
+#if defined(TARGET_ARCH_DBC)
+  // There is no need to support spilling on DBC because we have a lot of
+  // registers and registers and spill-slots have the same performance
+  // characteristics.
+  flow_graph_.parsed_function().Bailout("FlowGraphAllocator", "SPILL");
+  UNREACHABLE();
+#endif
+
   ASSERT(range->spill_slot().IsInvalid());
 
   // Compute range start and end.
   LiveRange* last_sibling = range;
   while (last_sibling->next_sibling() != NULL) {
     last_sibling = last_sibling->next_sibling();
   }
 
   const intptr_t start = range->Start();
   const intptr_t end = last_sibling->End();
@@ skipping 316 matching lines @@
 
   if (free_until != kMaxPosition) {
     // There was an intersection. Split unallocated.
     TRACE_ALLOC(THR_Print("  splitting at %" Pd "\n", free_until));
     LiveRange* tail = unallocated->SplitAt(free_until);
     AddToUnallocated(tail);
   }
 
   registers_[candidate]->Add(unallocated);
   unallocated->set_assigned_location(MakeRegisterLocation(candidate));
+#if defined(TARGET_ARCH_DBC)
+  last_used_register_ = Utils::Maximum(last_used_register_, candidate);
+#endif
 
   return true;
 }
 
 
 bool FlowGraphAllocator::RangeHasOnlyUnconstrainedUsesInLoop(LiveRange* range,
                                                              intptr_t loop_id) {
   if (range->vreg() >= 0) {
     LiveRange* parent = GetLiveRange(range->vreg());
     return parent->HasOnlyUnconstrainedUsesInLoop(loop_id);
@@ skipping 179 matching lines @@
       (*registers_[reg])[i] = NULL;
       first_evicted = i;
     }
   }
 
   // Remove evicted ranges from the array.
   if (first_evicted != -1) RemoveEvicted(reg, first_evicted);
 
   registers_[reg]->Add(unallocated);
   unallocated->set_assigned_location(MakeRegisterLocation(reg));
+#if defined(TARGET_ARCH_DBC)
+  last_used_register_ = Utils::Maximum(last_used_register_, reg);
+#endif
 }
 
 
 bool FlowGraphAllocator::EvictIntersection(LiveRange* allocated,
                                            LiveRange* unallocated) {
   UseInterval* first_unallocated =
       unallocated->finger()->first_pending_use_interval();
   const intptr_t intersection = FirstIntersection(
       allocated->finger()->first_pending_use_interval(),
       first_unallocated);
@@ skipping 69 matching lines @@
   for (UsePosition* use = range->first_use(); use != NULL; use = use->next()) {
     ConvertUseTo(use, loc);
   }
 
   // Add live registers at all safepoints for instructions with slow-path
   // code.
   if (loc.IsMachineRegister()) {
     for (SafepointPosition* safepoint = range->first_safepoint();
          safepoint != NULL;
          safepoint = safepoint->next()) {
+#if !defined(TARGET_ARCH_DBC)
       if (!safepoint->locs()->always_calls()) {
         ASSERT(safepoint->locs()->can_call());
         safepoint->locs()->live_registers()->Add(loc, range->representation());
       }
+#else
+      if (range->representation() == kTagged) {
+        safepoint->locs()->SetStackBit(loc.reg());
+      }
+#endif  // !defined(TARGET_ARCH_DBC)
     }
   }
 }
 
 
 void FlowGraphAllocator::AdvanceActiveIntervals(const intptr_t start) {
   for (intptr_t reg = 0; reg < NumberOfRegisters(); reg++) {
     if (registers_[reg]->is_empty()) continue;
 
     intptr_t first_evicted = -1;
@@ skipping 129 matching lines @@
   for (intptr_t reg = 0; reg < number_of_registers; reg++) {
     blocked_registers_[reg] = blocked_registers[reg];
     ASSERT(registers_[reg]->is_empty());
 
     LiveRange* range = blocking_ranges[reg];
     if (range != NULL) {
       range->finger()->Initialize(range);
       registers_[reg]->Add(range);
     }
   }
+
+#if defined(TARGET_ARCH_DBC)
+  last_used_register_ = -1;
+#endif
 }
 
 
 void FlowGraphAllocator::AllocateUnallocatedRanges() {
 #if defined(DEBUG)
   ASSERT(UnallocatedIsSorted());
 #endif
 
   while (!unallocated_.is_empty()) {
     LiveRange* range = unallocated_.RemoveLast();
@@ skipping 246 matching lines @@
   CollectRepresentations();
 
   liveness_.Analyze();
 
   NumberInstructions();
 
   DiscoverLoops();
 
   BuildLiveRanges();
 
-  if (FLAG_print_ssa_liveness) {
-    liveness_.Dump();
-  }
-
   if (FLAG_print_ssa_liveranges) {
     const Function& function = flow_graph_.function();
     THR_Print("-- [before ssa allocator] ranges [%s] ---------\n",
               function.ToFullyQualifiedCString());
     PrintLiveRanges();
     THR_Print("----------------------------------------------\n");
 
     THR_Print("-- [before ssa allocator] ir [%s] -------------\n",
               function.ToFullyQualifiedCString());
     if (FLAG_support_il_printer) {
 #ifndef PRODUCT
       FlowGraphPrinter printer(flow_graph_, true);
       printer.PrintBlocks();
 #endif
     }
     THR_Print("----------------------------------------------\n");
   }
 
   PrepareForAllocation(Location::kRegister,
                        kNumberOfCpuRegisters,
                        unallocated_cpu_,
                        cpu_regs_,
                        blocked_cpu_registers_);
   AllocateUnallocatedRanges();
+#if defined(TARGET_ARCH_DBC)
+  const intptr_t last_used_cpu_register = last_used_register_;
+#endif
 
   cpu_spill_slot_count_ = spill_slots_.length();
   spill_slots_.Clear();
   quad_spill_slots_.Clear();
   untagged_spill_slots_.Clear();
 
   PrepareForAllocation(Location::kFpuRegister,
                        kNumberOfFpuRegisters,
                        unallocated_xmm_,
                        fpu_regs_,
                        blocked_fpu_registers_);
   AllocateUnallocatedRanges();
+#if defined(TARGET_ARCH_DBC)
+  const intptr_t last_used_fpu_register = last_used_register_;
+  ASSERT(last_used_fpu_register == -1);  // Not supported right now.
+#endif
 
   ResolveControlFlow();
 
   GraphEntryInstr* entry = block_order_[0]->AsGraphEntry();
   ASSERT(entry != NULL);
   intptr_t double_spill_slot_count = spill_slots_.length() * kDoubleSpillFactor;
   entry->set_spill_slot_count(cpu_spill_slot_count_ + double_spill_slot_count);
 
+#if defined(TARGET_ARCH_DBC)
+  // Spilling is unsupported on DBC.
+  if (entry->spill_slot_count() != 0) {
+    UNREACHABLE();
+  }
+
+  // We store number of used DBC registers in the spill slot count to avoid
+  // introducing a separate field. It has roughly the same meaning:
+  // number of used registers determines how big of a frame to reserve for
+  // this function on DBC stack.
+  entry->set_spill_slot_count(Utils::Maximum((last_used_cpu_register + 1) +
+                                             (last_used_fpu_register + 1),
+                                             flow_graph_.num_copied_params()));
+#endif
+
   if (FLAG_print_ssa_liveranges) {
     const Function& function = flow_graph_.function();
 
     THR_Print("-- [after ssa allocator] ranges [%s] ---------\n",
               function.ToFullyQualifiedCString());
     PrintLiveRanges();
     THR_Print("----------------------------------------------\n");
 
     THR_Print("-- [after ssa allocator] ir [%s] -------------\n",
               function.ToFullyQualifiedCString());
     if (FLAG_support_il_printer) {
 #ifndef PRODUCT
       FlowGraphPrinter printer(flow_graph_, true);
       printer.PrintBlocks();
 #endif
     }
     THR_Print("----------------------------------------------\n");
   }
 }
 
 
 }  // namespace dart