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Side by Side Diff: src/ia32/assembler-ia32.h

Issue 1991713002: Adding ia32 simd assembler changes. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: cleanup Created 4 years, 7 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are 5 // modification, are permitted provided that the following conditions are
6 // met: 6 // met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
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215 215
216 // aliases 216 // aliases
217 carry = below, 217 carry = below,
218 not_carry = above_equal, 218 not_carry = above_equal,
219 zero = equal, 219 zero = equal,
220 not_zero = not_equal, 220 not_zero = not_equal,
221 sign = negative, 221 sign = negative,
222 not_sign = positive 222 not_sign = positive
223 }; 223 };
224 224
225
226 // Returns the equivalent of !cc. 225 // Returns the equivalent of !cc.
227 // Negation of the default no_condition (-1) results in a non-default 226 // Negation of the default no_condition (-1) results in a non-default
228 // no_condition value (-2). As long as tests for no_condition check 227 // no_condition value (-2). As long as tests for no_condition check
229 // for condition < 0, this will work as expected. 228 // for condition < 0, this will work as expected.
230 inline Condition NegateCondition(Condition cc) { 229 inline Condition NegateCondition(Condition cc) {
231 return static_cast<Condition>(cc ^ 1); 230 return static_cast<Condition>(cc ^ 1);
232 } 231 }
233 232
234 233
235 // Commute a condition such that {a cond b == b cond' a}. 234 // Commute a condition such that {a cond b == b cond' a}.
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351 explicit Operand(Register index, 350 explicit Operand(Register index,
352 ScaleFactor scale, 351 ScaleFactor scale,
353 int32_t disp, 352 int32_t disp,
354 RelocInfo::Mode rmode = RelocInfo::NONE32); 353 RelocInfo::Mode rmode = RelocInfo::NONE32);
355 354
356 static Operand JumpTable(Register index, ScaleFactor scale, Label* table) { 355 static Operand JumpTable(Register index, ScaleFactor scale, Label* table) {
357 return Operand(index, scale, reinterpret_cast<int32_t>(table), 356 return Operand(index, scale, reinterpret_cast<int32_t>(table),
358 RelocInfo::INTERNAL_REFERENCE); 357 RelocInfo::INTERNAL_REFERENCE);
359 } 358 }
360 359
360 // Offset from existing memory operand.
361 // The offset is added to existing displacement as 32-bit signed value.
362 // The caller must ensure overflow does not occur.
363 Operand(const Operand& base, int32_t offset);
364
361 static Operand StaticVariable(const ExternalReference& ext) { 365 static Operand StaticVariable(const ExternalReference& ext) {
362 return Operand(reinterpret_cast<int32_t>(ext.address()), 366 return Operand(reinterpret_cast<int32_t>(ext.address()),
363 RelocInfo::EXTERNAL_REFERENCE); 367 RelocInfo::EXTERNAL_REFERENCE);
364 } 368 }
365 369
366 static Operand StaticArray(Register index, 370 static Operand StaticArray(Register index,
367 ScaleFactor scale, 371 ScaleFactor scale,
368 const ExternalReference& arr) { 372 const ExternalReference& arr) {
369 return Operand(index, scale, reinterpret_cast<int32_t>(arr.address()), 373 return Operand(index, scale, reinterpret_cast<int32_t>(arr.address()),
370 RelocInfo::EXTERNAL_REFERENCE); 374 RelocInfo::EXTERNAL_REFERENCE);
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956 void mulss(XMMRegister dst, const Operand& src); 960 void mulss(XMMRegister dst, const Operand& src);
957 void divss(XMMRegister dst, XMMRegister src) { divss(dst, Operand(src)); } 961 void divss(XMMRegister dst, XMMRegister src) { divss(dst, Operand(src)); }
958 void divss(XMMRegister dst, const Operand& src); 962 void divss(XMMRegister dst, const Operand& src);
959 void sqrtss(XMMRegister dst, XMMRegister src) { sqrtss(dst, Operand(src)); } 963 void sqrtss(XMMRegister dst, XMMRegister src) { sqrtss(dst, Operand(src)); }
960 void sqrtss(XMMRegister dst, const Operand& src); 964 void sqrtss(XMMRegister dst, const Operand& src);
961 965
962 void ucomiss(XMMRegister dst, XMMRegister src) { ucomiss(dst, Operand(src)); } 966 void ucomiss(XMMRegister dst, XMMRegister src) { ucomiss(dst, Operand(src)); }
963 void ucomiss(XMMRegister dst, const Operand& src); 967 void ucomiss(XMMRegister dst, const Operand& src);
964 void movaps(XMMRegister dst, XMMRegister src); 968 void movaps(XMMRegister dst, XMMRegister src);
965 void shufps(XMMRegister dst, XMMRegister src, byte imm8); 969 void shufps(XMMRegister dst, XMMRegister src, byte imm8);
970 void movups(XMMRegister dst, const Operand& src);
971 void movups(const Operand& dst, XMMRegister src);
966 972
967 void maxss(XMMRegister dst, XMMRegister src) { maxss(dst, Operand(src)); } 973 void maxss(XMMRegister dst, XMMRegister src) { maxss(dst, Operand(src)); }
968 void maxss(XMMRegister dst, const Operand& src); 974 void maxss(XMMRegister dst, const Operand& src);
969 void minss(XMMRegister dst, XMMRegister src) { minss(dst, Operand(src)); } 975 void minss(XMMRegister dst, XMMRegister src) { minss(dst, Operand(src)); }
970 void minss(XMMRegister dst, const Operand& src); 976 void minss(XMMRegister dst, const Operand& src);
971 977
972 void andps(XMMRegister dst, const Operand& src); 978 void andps(XMMRegister dst, const Operand& src);
973 void andps(XMMRegister dst, XMMRegister src) { andps(dst, Operand(src)); } 979 void andps(XMMRegister dst, XMMRegister src) { andps(dst, Operand(src)); }
974 void xorps(XMMRegister dst, const Operand& src); 980 void xorps(XMMRegister dst, const Operand& src);
975 void xorps(XMMRegister dst, XMMRegister src) { xorps(dst, Operand(src)); } 981 void xorps(XMMRegister dst, XMMRegister src) { xorps(dst, Operand(src)); }
976 void orps(XMMRegister dst, const Operand& src); 982 void orps(XMMRegister dst, const Operand& src);
977 void orps(XMMRegister dst, XMMRegister src) { orps(dst, Operand(src)); } 983 void orps(XMMRegister dst, XMMRegister src) { orps(dst, Operand(src)); }
978 984
979 void addps(XMMRegister dst, const Operand& src); 985 void addps(XMMRegister dst, const Operand& src);
980 void addps(XMMRegister dst, XMMRegister src) { addps(dst, Operand(src)); } 986 void addps(XMMRegister dst, XMMRegister src) { addps(dst, Operand(src)); }
981 void subps(XMMRegister dst, const Operand& src); 987 void subps(XMMRegister dst, const Operand& src);
982 void subps(XMMRegister dst, XMMRegister src) { subps(dst, Operand(src)); } 988 void subps(XMMRegister dst, XMMRegister src) { subps(dst, Operand(src)); }
983 void mulps(XMMRegister dst, const Operand& src); 989 void mulps(XMMRegister dst, const Operand& src);
984 void mulps(XMMRegister dst, XMMRegister src) { mulps(dst, Operand(src)); } 990 void mulps(XMMRegister dst, XMMRegister src) { mulps(dst, Operand(src)); }
985 void divps(XMMRegister dst, const Operand& src); 991 void divps(XMMRegister dst, const Operand& src);
986 void divps(XMMRegister dst, XMMRegister src) { divps(dst, Operand(src)); } 992 void divps(XMMRegister dst, XMMRegister src) { divps(dst, Operand(src)); }
993 void minps(XMMRegister dst, XMMRegister src) { minps(dst, Operand(src)); }
994 void minps(XMMRegister dst, const Operand& src);
995 void maxps(XMMRegister dst, XMMRegister src) { maxps(dst, Operand(src)); }
996 void maxps(XMMRegister dst, const Operand& src);
997 void rcpps(XMMRegister dst, XMMRegister src) { rcpps(dst, Operand(src)); }
998 void rcpps(XMMRegister dst, const Operand& src);
999 void rsqrtps(XMMRegister dst, XMMRegister src) { rsqrtps(dst, Operand(src)); }
1000 void rsqrtps(XMMRegister dst, const Operand& src);
1001 void sqrtps(XMMRegister dst, XMMRegister src) { sqrtps(dst, Operand(src)); }
1002 void sqrtps(XMMRegister dst, const Operand& src);
1003
1004 void cmpps(XMMRegister dst, XMMRegister src, int8_t cmp);
1005 void cmpeqps(XMMRegister dst, XMMRegister src);
1006 void cmpltps(XMMRegister dst, XMMRegister src);
1007 void cmpleps(XMMRegister dst, XMMRegister src);
1008 void cmpneqps(XMMRegister dst, XMMRegister src);
1009 void cmpnltps(XMMRegister dst, XMMRegister src);
1010 void cmpnleps(XMMRegister dst, XMMRegister src);
987 1011
988 // SSE2 instructions 1012 // SSE2 instructions
989 void cvttss2si(Register dst, const Operand& src); 1013 void cvttss2si(Register dst, const Operand& src);
990 void cvttss2si(Register dst, XMMRegister src) { 1014 void cvttss2si(Register dst, XMMRegister src) {
991 cvttss2si(dst, Operand(src)); 1015 cvttss2si(dst, Operand(src));
992 } 1016 }
993 void cvttsd2si(Register dst, const Operand& src); 1017 void cvttsd2si(Register dst, const Operand& src);
994 void cvttsd2si(Register dst, XMMRegister src) { 1018 void cvttsd2si(Register dst, XMMRegister src) {
995 cvttsd2si(dst, Operand(src)); 1019 cvttsd2si(dst, Operand(src));
996 } 1020 }
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1083 void pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle); 1107 void pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle);
1084 void pextrd(Register dst, XMMRegister src, int8_t offset) { 1108 void pextrd(Register dst, XMMRegister src, int8_t offset) {
1085 pextrd(Operand(dst), src, offset); 1109 pextrd(Operand(dst), src, offset);
1086 } 1110 }
1087 void pextrd(const Operand& dst, XMMRegister src, int8_t offset); 1111 void pextrd(const Operand& dst, XMMRegister src, int8_t offset);
1088 void pinsrd(XMMRegister dst, Register src, int8_t offset) { 1112 void pinsrd(XMMRegister dst, Register src, int8_t offset) {
1089 pinsrd(dst, Operand(src), offset); 1113 pinsrd(dst, Operand(src), offset);
1090 } 1114 }
1091 void pinsrd(XMMRegister dst, const Operand& src, int8_t offset); 1115 void pinsrd(XMMRegister dst, const Operand& src, int8_t offset);
1092 1116
1117 void paddd(XMMRegister dst, XMMRegister src) { paddd(dst, Operand(src)); }
1118 void paddd(XMMRegister dst, const Operand& src);
1119 void psubd(XMMRegister dst, XMMRegister src) { psubd(dst, Operand(src)); }
1120 void psubd(XMMRegister dst, const Operand& src);
1121 void pmuludq(XMMRegister dst, XMMRegister src) { pmuludq(dst, Operand(src)); }
1122 void pmuludq(XMMRegister dst, const Operand& src);
1123 void punpackldq(XMMRegister dst, XMMRegister src) {
1124 punpackldq(dst, Operand(src));
1125 }
1126 void punpackldq(XMMRegister dst, const Operand& src);
1127 void cvtps2dq(XMMRegister dst, XMMRegister src) {
1128 cvtps2dq(dst, Operand(src));
1129 }
1130 void cvtps2dq(XMMRegister dst, const Operand& src);
1131 void cvtdq2ps(XMMRegister dst, XMMRegister src) {
1132 cvtdq2ps(dst, Operand(src));
1133 }
1134 void cvtdq2ps(XMMRegister dst, const Operand& src);
1135
1136 // SSE4.1 instructions
1137 void insertps(XMMRegister dst, XMMRegister src, byte imm8);
1138 void pmulld(XMMRegister dst, XMMRegister src) { pmulld(dst, Operand(src)); }
1139 void pmulld(XMMRegister dst, const Operand& src);
1140
1093 // AVX instructions 1141 // AVX instructions
1094 void vfmadd132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1142 void vfmadd132sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1095 vfmadd132sd(dst, src1, Operand(src2)); 1143 vfmadd132sd(dst, src1, Operand(src2));
1096 } 1144 }
1097 void vfmadd213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1145 void vfmadd213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1098 vfmadd213sd(dst, src1, Operand(src2)); 1146 vfmadd213sd(dst, src1, Operand(src2));
1099 } 1147 }
1100 void vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) { 1148 void vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
1101 vfmadd231sd(dst, src1, Operand(src2)); 1149 vfmadd231sd(dst, src1, Operand(src2));
1102 } 1150 }
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1607 Assembler* assembler_; 1655 Assembler* assembler_;
1608 #ifdef DEBUG 1656 #ifdef DEBUG
1609 int space_before_; 1657 int space_before_;
1610 #endif 1658 #endif
1611 }; 1659 };
1612 1660
1613 } // namespace internal 1661 } // namespace internal
1614 } // namespace v8 1662 } // namespace v8
1615 1663
1616 #endif // V8_IA32_ASSEMBLER_IA32_H_ 1664 #endif // V8_IA32_ASSEMBLER_IA32_H_
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