Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(417)

Issues Search
    My Issues | Starred     Open | Closed | All

Side by Side Diff: src/arm64/constants-arm64.h

Issue 1990073002: Add {lda,stl}x?r{,b,h} instructions to ARM64 assembler/disassembler (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: typo Created 4 years, 7 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « src/arm64/assembler-arm64.cc ('k') | src/arm64/decoder-arm64.h » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 // Copyright 2013 the V8 project authors. All rights reserved. 1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_ARM64_CONSTANTS_ARM64_H_ 5 #ifndef V8_ARM64_CONSTANTS_ARM64_H_
6 #define V8_ARM64_CONSTANTS_ARM64_H_ 6 #define V8_ARM64_CONSTANTS_ARM64_H_
7 7
8 #include "src/base/macros.h" 8 #include "src/base/macros.h"
9 #include "src/globals.h" 9 #include "src/globals.h"
10 10
(...skipping 99 matching lines...) Expand 10 before | Expand all | Expand 10 after
110 const unsigned kDoubleWordSizeInBytes = kDoubleWordSize >> 3; 110 const unsigned kDoubleWordSizeInBytes = kDoubleWordSize >> 3;
111 const unsigned kQuadWordSize = 128; 111 const unsigned kQuadWordSize = 128;
112 const unsigned kQuadWordSizeInBytes = kQuadWordSize >> 3; 112 const unsigned kQuadWordSizeInBytes = kQuadWordSize >> 3;
113 // AArch64 floating-point specifics. These match IEEE-754. 113 // AArch64 floating-point specifics. These match IEEE-754.
114 const unsigned kDoubleMantissaBits = 52; 114 const unsigned kDoubleMantissaBits = 52;
115 const unsigned kDoubleExponentBits = 11; 115 const unsigned kDoubleExponentBits = 11;
116 const unsigned kDoubleExponentBias = 1023; 116 const unsigned kDoubleExponentBias = 1023;
117 const unsigned kFloatMantissaBits = 23; 117 const unsigned kFloatMantissaBits = 23;
118 const unsigned kFloatExponentBits = 8; 118 const unsigned kFloatExponentBits = 8;
119 119
120 #define INSTRUCTION_FIELDS_LIST(V_) \ 120 #define INSTRUCTION_FIELDS_LIST(V_) \
121 /* Register fields */ \ 121 /* Register fields */ \
122 V_(Rd, 4, 0, Bits) /* Destination register. */ \ 122 V_(Rd, 4, 0, Bits) /* Destination register. */ \
123 V_(Rn, 9, 5, Bits) /* First source register. */ \ 123 V_(Rn, 9, 5, Bits) /* First source register. */ \
124 V_(Rm, 20, 16, Bits) /* Second source register. */ \ 124 V_(Rm, 20, 16, Bits) /* Second source register. */ \
125 V_(Ra, 14, 10, Bits) /* Third source register. */ \ 125 V_(Ra, 14, 10, Bits) /* Third source register. */ \
126 V_(Rt, 4, 0, Bits) /* Load dest / store source. */ \ 126 V_(Rt, 4, 0, Bits) /* Load dest / store source. */ \
127 V_(Rt2, 14, 10, Bits) /* Load second dest / */ \ 127 V_(Rt2, 14, 10, Bits) /* Load second dest / */ \
128 /* store second source. */ \ 128 /* store second source. */ \
129 V_(PrefetchMode, 4, 0, Bits) \ 129 V_(Rs, 20, 16, Bits) /* Store-exclusive status */ \
130 \ 130 V_(PrefetchMode, 4, 0, Bits) \
131 /* Common bits */ \ 131 \
132 V_(SixtyFourBits, 31, 31, Bits) \ 132 /* Common bits */ \
133 V_(FlagsUpdate, 29, 29, Bits) \ 133 V_(SixtyFourBits, 31, 31, Bits) \
134 \ 134 V_(FlagsUpdate, 29, 29, Bits) \
135 /* PC relative addressing */ \ 135 \
136 V_(ImmPCRelHi, 23, 5, SignedBits) \ 136 /* PC relative addressing */ \
137 V_(ImmPCRelLo, 30, 29, Bits) \ 137 V_(ImmPCRelHi, 23, 5, SignedBits) \
138 \ 138 V_(ImmPCRelLo, 30, 29, Bits) \
139 /* Add/subtract/logical shift register */ \ 139 \
140 V_(ShiftDP, 23, 22, Bits) \ 140 /* Add/subtract/logical shift register */ \
141 V_(ImmDPShift, 15, 10, Bits) \ 141 V_(ShiftDP, 23, 22, Bits) \
142 \ 142 V_(ImmDPShift, 15, 10, Bits) \
143 /* Add/subtract immediate */ \ 143 \
144 V_(ImmAddSub, 21, 10, Bits) \ 144 /* Add/subtract immediate */ \
145 V_(ShiftAddSub, 23, 22, Bits) \ 145 V_(ImmAddSub, 21, 10, Bits) \
146 \ 146 V_(ShiftAddSub, 23, 22, Bits) \
147 /* Add/substract extend */ \ 147 \
148 V_(ImmExtendShift, 12, 10, Bits) \ 148 /* Add/substract extend */ \
149 V_(ExtendMode, 15, 13, Bits) \ 149 V_(ImmExtendShift, 12, 10, Bits) \
150 \ 150 V_(ExtendMode, 15, 13, Bits) \
151 /* Move wide */ \ 151 \
152 V_(ImmMoveWide, 20, 5, Bits) \ 152 /* Move wide */ \
153 V_(ShiftMoveWide, 22, 21, Bits) \ 153 V_(ImmMoveWide, 20, 5, Bits) \
154 \ 154 V_(ShiftMoveWide, 22, 21, Bits) \
155 /* Logical immediate, bitfield and extract */ \ 155 \
156 V_(BitN, 22, 22, Bits) \ 156 /* Logical immediate, bitfield and extract */ \
157 V_(ImmRotate, 21, 16, Bits) \ 157 V_(BitN, 22, 22, Bits) \
158 V_(ImmSetBits, 15, 10, Bits) \ 158 V_(ImmRotate, 21, 16, Bits) \
159 V_(ImmR, 21, 16, Bits) \ 159 V_(ImmSetBits, 15, 10, Bits) \
160 V_(ImmS, 15, 10, Bits) \ 160 V_(ImmR, 21, 16, Bits) \
161 \ 161 V_(ImmS, 15, 10, Bits) \
162 /* Test and branch immediate */ \ 162 \
163 V_(ImmTestBranch, 18, 5, SignedBits) \ 163 /* Test and branch immediate */ \
164 V_(ImmTestBranchBit40, 23, 19, Bits) \ 164 V_(ImmTestBranch, 18, 5, SignedBits) \
165 V_(ImmTestBranchBit5, 31, 31, Bits) \ 165 V_(ImmTestBranchBit40, 23, 19, Bits) \
166 \ 166 V_(ImmTestBranchBit5, 31, 31, Bits) \
167 /* Conditionals */ \ 167 \
168 V_(Condition, 15, 12, Bits) \ 168 /* Conditionals */ \
169 V_(ConditionBranch, 3, 0, Bits) \ 169 V_(Condition, 15, 12, Bits) \
170 V_(Nzcv, 3, 0, Bits) \ 170 V_(ConditionBranch, 3, 0, Bits) \
171 V_(ImmCondCmp, 20, 16, Bits) \ 171 V_(Nzcv, 3, 0, Bits) \
172 V_(ImmCondBranch, 23, 5, SignedBits) \ 172 V_(ImmCondCmp, 20, 16, Bits) \
173 \ 173 V_(ImmCondBranch, 23, 5, SignedBits) \
174 /* Floating point */ \ 174 \
175 V_(FPType, 23, 22, Bits) \ 175 /* Floating point */ \
176 V_(ImmFP, 20, 13, Bits) \ 176 V_(FPType, 23, 22, Bits) \
177 V_(FPScale, 15, 10, Bits) \ 177 V_(ImmFP, 20, 13, Bits) \
178 \ 178 V_(FPScale, 15, 10, Bits) \
179 /* Load Store */ \ 179 \
180 V_(ImmLS, 20, 12, SignedBits) \ 180 /* Load Store */ \
181 V_(ImmLSUnsigned, 21, 10, Bits) \ 181 V_(ImmLS, 20, 12, SignedBits) \
182 V_(ImmLSPair, 21, 15, SignedBits) \ 182 V_(ImmLSUnsigned, 21, 10, Bits) \
183 V_(SizeLS, 31, 30, Bits) \ 183 V_(ImmLSPair, 21, 15, SignedBits) \
184 V_(ImmShiftLS, 12, 12, Bits) \ 184 V_(SizeLS, 31, 30, Bits) \
185 \ 185 V_(ImmShiftLS, 12, 12, Bits) \
186 /* Other immediates */ \ 186 \
187 V_(ImmUncondBranch, 25, 0, SignedBits) \ 187 /* Other immediates */ \
188 V_(ImmCmpBranch, 23, 5, SignedBits) \ 188 V_(ImmUncondBranch, 25, 0, SignedBits) \
189 V_(ImmLLiteral, 23, 5, SignedBits) \ 189 V_(ImmCmpBranch, 23, 5, SignedBits) \
190 V_(ImmException, 20, 5, Bits) \ 190 V_(ImmLLiteral, 23, 5, SignedBits) \
191 V_(ImmHint, 11, 5, Bits) \ 191 V_(ImmException, 20, 5, Bits) \
192 V_(ImmBarrierDomain, 11, 10, Bits) \ 192 V_(ImmHint, 11, 5, Bits) \
193 V_(ImmBarrierType, 9, 8, Bits) \ 193 V_(ImmBarrierDomain, 11, 10, Bits) \
194 \ 194 V_(ImmBarrierType, 9, 8, Bits) \
195 /* System (MRS, MSR) */ \ 195 \
196 V_(ImmSystemRegister, 19, 5, Bits) \ 196 /* System (MRS, MSR) */ \
197 V_(SysO0, 19, 19, Bits) \ 197 V_(ImmSystemRegister, 19, 5, Bits) \
198 V_(SysOp1, 18, 16, Bits) \ 198 V_(SysO0, 19, 19, Bits) \
199 V_(SysOp2, 7, 5, Bits) \ 199 V_(SysOp1, 18, 16, Bits) \
200 V_(CRn, 15, 12, Bits) \ 200 V_(SysOp2, 7, 5, Bits) \
201 V_(CRm, 11, 8, Bits) \ 201 V_(CRn, 15, 12, Bits) \
202 202 V_(CRm, 11, 8, Bits)
203 203
204 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \ 204 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \
205 /* NZCV */ \ 205 /* NZCV */ \
206 V_(Flags, 31, 28, Bits, uint32_t) \ 206 V_(Flags, 31, 28, Bits, uint32_t) \
207 V_(N, 31, 31, Bits, bool) \ 207 V_(N, 31, 31, Bits, bool) \
208 V_(Z, 30, 30, Bits, bool) \ 208 V_(Z, 30, 30, Bits, bool) \
209 V_(C, 29, 29, Bits, bool) \ 209 V_(C, 29, 29, Bits, bool) \
210 V_(V, 28, 28, Bits, uint32_t) \ 210 V_(V, 28, 28, Bits, uint32_t) \
211 M_(NZCV, Flags_mask) \ 211 M_(NZCV, Flags_mask) \
212 \ 212 \
(...skipping 637 matching lines...) Expand 10 before | Expand all | Expand 10 after
850 LoadStoreRegisterOffsetFixed = 0x38200800, 850 LoadStoreRegisterOffsetFixed = 0x38200800,
851 LoadStoreRegisterOffsetFMask = 0x3B200C00, 851 LoadStoreRegisterOffsetFMask = 0x3B200C00,
852 LoadStoreRegisterOffsetMask = 0xFFE00C00, 852 LoadStoreRegisterOffsetMask = 0xFFE00C00,
853 PRFM_reg = LoadStoreRegisterOffsetFixed | PRFM, 853 PRFM_reg = LoadStoreRegisterOffsetFixed | PRFM,
854 #define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \ 854 #define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \
855 A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D 855 A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D
856 LOAD_STORE_OP_LIST(LOAD_STORE_REGISTER_OFFSET) 856 LOAD_STORE_OP_LIST(LOAD_STORE_REGISTER_OFFSET)
857 #undef LOAD_STORE_REGISTER_OFFSET 857 #undef LOAD_STORE_REGISTER_OFFSET
858 }; 858 };
859 859
860 // Load/store acquire/release
861 enum LoadStoreAcquireReleaseOp {
862 LoadStoreAcquireReleaseFixed = 0x08000000,
863 LoadStoreAcquireReleaseFMask = 0x3F000000,
864 LoadStoreAcquireReleaseMask = 0xCFC08000,
865 STLXR_b = LoadStoreAcquireReleaseFixed | 0x00008000,
866 LDAXR_b = LoadStoreAcquireReleaseFixed | 0x00408000,
867 STLR_b = LoadStoreAcquireReleaseFixed | 0x00808000,
868 LDAR_b = LoadStoreAcquireReleaseFixed | 0x00C08000,
869 STLXR_h = LoadStoreAcquireReleaseFixed | 0x40008000,
870 LDAXR_h = LoadStoreAcquireReleaseFixed | 0x40408000,
871 STLR_h = LoadStoreAcquireReleaseFixed | 0x40808000,
872 LDAR_h = LoadStoreAcquireReleaseFixed | 0x40C08000,
873 STLXR_w = LoadStoreAcquireReleaseFixed | 0x80008000,
874 LDAXR_w = LoadStoreAcquireReleaseFixed | 0x80408000,
875 STLR_w = LoadStoreAcquireReleaseFixed | 0x80808000,
876 LDAR_w = LoadStoreAcquireReleaseFixed | 0x80C08000,
877 STLXR_x = LoadStoreAcquireReleaseFixed | 0xC0008000,
878 LDAXR_x = LoadStoreAcquireReleaseFixed | 0xC0408000,
879 STLR_x = LoadStoreAcquireReleaseFixed | 0xC0808000,
880 LDAR_x = LoadStoreAcquireReleaseFixed | 0xC0C08000,
881 };
882
860 // Conditional compare. 883 // Conditional compare.
861 enum ConditionalCompareOp { 884 enum ConditionalCompareOp {
862 ConditionalCompareMask = 0x60000000, 885 ConditionalCompareMask = 0x60000000,
863 CCMN = 0x20000000, 886 CCMN = 0x20000000,
864 CCMP = 0x60000000 887 CCMP = 0x60000000
865 }; 888 };
866 889
867 // Conditional compare register. 890 // Conditional compare register.
868 enum ConditionalCompareRegisterOp { 891 enum ConditionalCompareRegisterOp {
869 ConditionalCompareRegisterFixed = 0x1A400000, 892 ConditionalCompareRegisterFixed = 0x1A400000,
(...skipping 357 matching lines...) Expand 10 before | Expand all | Expand 10 after
1227 1250
1228 enum UnallocatedOp { 1251 enum UnallocatedOp {
1229 UnallocatedFixed = 0x00000000, 1252 UnallocatedFixed = 0x00000000,
1230 UnallocatedFMask = 0x00000000 1253 UnallocatedFMask = 0x00000000
1231 }; 1254 };
1232 1255
1233 } // namespace internal 1256 } // namespace internal
1234 } // namespace v8 1257 } // namespace v8
1235 1258
1236 #endif // V8_ARM64_CONSTANTS_ARM64_H_ 1259 #endif // V8_ARM64_CONSTANTS_ARM64_H_
OLDNEW
« no previous file with comments | « src/arm64/assembler-arm64.cc ('k') | src/arm64/decoder-arm64.h » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698