Subzero, MIPS32: Implements integer division instructions sdiv, udiv, srem, urem

src/IceTargetLoweringMIPS32.cpp

 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// \brief Implements the TargetLoweringMIPS32 class, which consists almost
@@ skipping 674 matching lines @@
     lowerInt64Arithmetic(Instr, Instr->getDest(), Src0, Src1);
     return;
   }
   if (isVectorType(Dest->getType())) {
     UnimplementedLoweringError(this, Instr);
     return;
   }
   switch (Instr->getOp()) {
   default:
     break;
-  case InstArithmetic::Udiv:
-  case InstArithmetic::Sdiv:
-  case InstArithmetic::Urem:
-  case InstArithmetic::Srem:
   case InstArithmetic::Fadd:
   case InstArithmetic::Fsub:
   case InstArithmetic::Fmul:
   case InstArithmetic::Fdiv:
   case InstArithmetic::Frem:
     UnimplementedLoweringError(this, Instr);
     return;
   }
 
   // At this point Dest->getType() is non-i64 scalar
@@ skipping 38 matching lines @@
   case InstArithmetic::Lshr: {
     _srlv(T, Src0R, Src1R);
     _mov(Dest, T);
     return;
   }
   case InstArithmetic::Ashr: {
     _srav(T, Src0R, Src1R);
     _mov(Dest, T);
     return;
   }
-  case InstArithmetic::Udiv:
-    break;
-  case InstArithmetic::Sdiv:
-    break;
-  case InstArithmetic::Urem:
-    break;
-  case InstArithmetic::Srem:
-    break;
+  case InstArithmetic::Udiv: {
+    auto *T_Zero = I32Reg(RegMIPS32::Reg_ZERO);
+    _divu(T_Zero, Src0R, Src1R);
+    _mflo(T, T_Zero);
+    _mov(Dest, T);
+    return;
+  }
+  case InstArithmetic::Sdiv: {
+    auto *T_Zero = I32Reg(RegMIPS32::Reg_ZERO);
+    _div(T_Zero, Src0R, Src1R);
+    _mflo(T, T_Zero);
+    _mov(Dest, T);
+    return;
+  }
+  case InstArithmetic::Urem: {
+    auto *T_Zero = I32Reg(RegMIPS32::Reg_ZERO);
+    _divu(T_Zero, Src0R, Src1R);
+    _mfhi(T, T_Zero);
+    _mov(Dest, T);
+    return;
+  }
+  case InstArithmetic::Srem: {
+    auto *T_Zero = I32Reg(RegMIPS32::Reg_ZERO);
+    _div(T_Zero, Src0R, Src1R);
+    _mfhi(T, T_Zero);
+    _mov(Dest, T);
+    return;
+  }
   case InstArithmetic::Fadd:
     break;
   case InstArithmetic::Fsub:
     break;
   case InstArithmetic::Fmul:
     break;
   case InstArithmetic::Fdiv:
     break;
   case InstArithmetic::Frem:
     break;
@@ skipping 711 matching lines @@
   Str << "\t.set\t"
       << "nomips16\n";
 }
 
 SmallBitVector TargetMIPS32::TypeToRegisterSet[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
 SmallBitVector TargetMIPS32::RegisterAliases[RegMIPS32::Reg_NUM];
 
 } // end of namespace MIPS32
 } // end of namespace Ice