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Issue 19875002: Adds reciprocal squre root SIMD instructions for ARM. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 7 years, 5 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/disassembler.h" 5 #include "vm/disassembler.h"
6 6
7 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM. 7 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM.
8 #if defined(TARGET_ARCH_ARM) 8 #if defined(TARGET_ARCH_ARM)
9 #include "platform/assert.h" 9 #include "platform/assert.h"
10 10
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1341 } else if ((instr->Bits(8, 4) == 15) && (instr->Bit(4) == 0) && 1341 } else if ((instr->Bits(8, 4) == 15) && (instr->Bit(4) == 0) &&
1342 (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 0)) { 1342 (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 0)) {
1343 Format(instr, "vmaxqs 'qd, 'qn, 'qm"); 1343 Format(instr, "vmaxqs 'qd, 'qn, 'qm");
1344 } else if ((instr->Bits(7, 5) == 10) && (instr->Bit(4) == 0) && 1344 } else if ((instr->Bits(7, 5) == 10) && (instr->Bit(4) == 0) &&
1345 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) && 1345 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) &&
1346 (instr->Bits(16, 4) == 11)) { 1346 (instr->Bits(16, 4) == 11)) {
1347 Format(instr, "vrecpeqs 'qd, 'qm"); 1347 Format(instr, "vrecpeqs 'qd, 'qm");
1348 } else if ((instr->Bits(8, 4) == 15) && (instr->Bit(4) == 1) && 1348 } else if ((instr->Bits(8, 4) == 15) && (instr->Bit(4) == 1) &&
1349 (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 0)) { 1349 (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 0)) {
1350 Format(instr, "vrecpsqs 'qd, 'qn, 'qm"); 1350 Format(instr, "vrecpsqs 'qd, 'qn, 'qm");
1351 } else if ((instr->Bits(8, 4) == 5) && (instr->Bit(4) == 0) &&
1352 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) &&
1353 (instr->Bit(7) == 1) && (instr->Bits(16, 4) == 11)) {
1354 Format(instr, "vrsqrteqs 'qd, 'qm");
1355 } else if ((instr->Bits(8, 4) == 15) && (instr->Bit(4) == 1) &&
1356 (instr->Bits(20, 2) == 2) && (instr->Bits(23, 2) == 0)) {
1357 Format(instr, "vrsqrtsqs 'qd, 'qn, 'qm");
1351 } else if ((instr->Bits(8, 4) == 12) && (instr->Bit(4) == 0) && 1358 } else if ((instr->Bits(8, 4) == 12) && (instr->Bit(4) == 0) &&
1352 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) && 1359 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) &&
1353 (instr->Bit(7) == 0)) { 1360 (instr->Bit(7) == 0)) {
1354 int32_t imm4 = instr->Bits(16, 4); 1361 int32_t imm4 = instr->Bits(16, 4);
1355 if (imm4 & 1) { 1362 if (imm4 & 1) {
1356 Format(instr, "vdupb 'qd, 'dm['imm4_vdup]"); 1363 Format(instr, "vdupb 'qd, 'dm['imm4_vdup]");
1357 } else if (imm4 & 2) { 1364 } else if (imm4 & 2) {
1358 Format(instr, "vduph 'qd, 'dm['imm4_vdup]"); 1365 Format(instr, "vduph 'qd, 'dm['imm4_vdup]");
1359 } else if (imm4 & 4) { 1366 } else if (imm4 & 4) {
1360 Format(instr, "vdupw 'qd, 'dm['imm4_vdup]"); 1367 Format(instr, "vdupw 'qd, 'dm['imm4_vdup]");
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1494 human_buffer, 1501 human_buffer,
1495 sizeof(human_buffer), 1502 sizeof(human_buffer),
1496 pc); 1503 pc);
1497 pc += instruction_length; 1504 pc += instruction_length;
1498 } 1505 }
1499 } 1506 }
1500 1507
1501 } // namespace dart 1508 } // namespace dart
1502 1509
1503 #endif // defined TARGET_ARCH_ARM 1510 #endif // defined TARGET_ARCH_ARM
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