Add cmpxchg and lock instructions to x64 and ia32 {dis,}assemblers

src/x64/assembler-x64.h

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 403 matching lines @@
 
   // Adds operand displacement fields (offsets added to the memory address).
   // Needs to be called after set_sib, not before it.
   inline void set_disp8(int disp);
   inline void set_disp32(int disp);
   inline void set_disp64(int64_t disp);  // for labels.
 
   friend class Assembler;
 };
 
-
 #define ASSEMBLER_INSTRUCTION_LIST(V) \
   V(add)                              \
   V(and)                              \
   V(cmp)                              \
+  V(cmpxchg)                          \
   V(dec)                              \
   V(idiv)                             \
   V(div)                              \
   V(imul)                             \
   V(inc)                              \
   V(lea)                              \
   V(mov)                              \
   V(movzxb)                           \
   V(movzxw)                           \
   V(neg)                              \
   V(not)                              \
   V(or)                               \
   V(repmovs)                          \
   V(sbb)                              \
   V(sub)                              \
   V(test)                             \
   V(xchg)                             \
   V(xor)
 
-
 // Shift instructions on operands/registers with kPointerSize, kInt32Size and
 // kInt64Size.
 #define SHIFT_INSTRUCTION_LIST(V)       \
   V(rol, 0x0)                           \
   V(ror, 0x1)                           \
   V(rcl, 0x2)                           \
   V(rcr, 0x3)                           \
   V(shl, 0x4)                           \
   V(shr, 0x5)                           \
   V(sar, 0x7)                           \
@@ skipping 322 matching lines @@
 
   void testw(Register reg, const Operand& op) { testw(op, reg); }
 
   void andb(Register dst, Immediate src) {
     immediate_arithmetic_op_8(0x4, dst, src);
   }
 
   void decb(Register dst);
   void decb(const Operand& dst);
 
+  // Lock prefix.
+  void lock();
+
   void xchgb(Register reg, const Operand& op);
   void xchgw(Register reg, const Operand& op);
 
+  void cmpxchgb(const Operand& dst, Register src);
+  void cmpxchgw(const Operand& dst, Register src);
+
   // Sign-extends rax into rdx:rax.
   void cqo();
   // Sign-extends eax into edx:eax.
   void cdq();
 
   // Multiply eax by src, put the result in edx:eax.
   void mull(Register src);
   void mull(const Operand& src);
   // Multiply rax by src, put the result in rdx:rax.
   void mulq(Register src);
@@ skipping 1243 matching lines @@
   }
 
   void emit_cmp(Register dst, Immediate src, int size) {
     immediate_arithmetic_op(0x7, dst, src, size);
   }
 
   void emit_cmp(const Operand& dst, Immediate src, int size) {
     immediate_arithmetic_op(0x7, dst, src, size);
   }
 
+  // Compare {al,ax,eax,rax} with src.  If equal, set ZF and write dst into
+  // src. Otherwise clear ZF and write src into {al,ax,eax,rax}.  This
+  // operation is only atomic if prefixed by the lock instruction.
+  void emit_cmpxchg(const Operand& dst, Register src, int size);
+
   void emit_dec(Register dst, int size);
   void emit_dec(const Operand& dst, int size);
 
   // Divide rdx:rax by src.  Quotient in rax, remainder in rdx when size is 64.
   // Divide edx:eax by lower 32 bits of src.  Quotient in eax, remainder in edx
   // when size is 32.
   void emit_idiv(Register src, int size);
   void emit_div(Register src, int size);
 
   // Signed multiply instructions.
@@ skipping 165 matching lines @@
   Assembler* assembler_;
 #ifdef DEBUG
   int space_before_;
 #endif
 };
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_X64_ASSEMBLER_X64_H_