Increases the number of ARM floating-point registers.

runtime/vm/assembler_arm.cc

Index: runtime/vm/assembler_arm.cc
===================================================================
--- runtime/vm/assembler_arm.cc	(revision 25344)
+++ runtime/vm/assembler_arm.cc	(working copy)
@@ -920,6 +920,7 @@
                       DRegister first, DRegister last, Condition cond) {
   ASSERT((am == IA) || (am == IA_W) || (am == DB_W));
   ASSERT(last > first);
+  ASSERT(last - first <= 16);

[regis, 2013/07/23 17:38:04]

ASSERT((last - first + 1) <= 16);

[zra, 2013/07/23 18:24:14]

Done.

   EmitMultiVDMemOp(cond, am, true, base, first, last - first + 1);
 }
 
@@ -928,6 +929,7 @@
                       DRegister first, DRegister last, Condition cond) {
   ASSERT((am == IA) || (am == IA_W) || (am == DB_W));
   ASSERT(last > first);
+  ASSERT(last - first <= 16);

[regis, 2013/07/23 17:38:04]

ditto

[zra, 2013/07/23 18:24:14]

Done.

   EmitMultiVDMemOp(cond, am, false, base, first, last - first + 1);
 }
 
@@ -2281,7 +2283,15 @@
   // Preserve all volatile FPU registers.
   DRegister firstv = EvenDRegisterOf(kDartFirstVolatileFpuReg);
   DRegister lastv = OddDRegisterOf(kDartLastVolatileFpuReg);
-  vstmd(DB_W, SP, firstv, lastv);
+  if (lastv - firstv > 16) {

[regis, 2013/07/23 17:38:04]

if ((lastv - firstv + 1) > 16) {

[zra, 2013/07/23 18:24:14]

Done.

+    ASSERT(kNumberOfDRegisters <= 32);

[regis, 2013/07/23 17:38:04]

This assert seems overcautious.

I wonder if we should change the parameters of vstmd and vldmd to take a
register and a count, instead of a first and last register, which complicates
the call sites.

[zra, 2013/07/23 18:24:14]

I changed vstmd and vldrd to take a count instead of a second register, and
added an assert there.

+    DRegister mid1 = static_cast<DRegister>(firstv + 15);
+    DRegister mid2 = static_cast<DRegister>(firstv + 16);
+    vstmd(DB_W, SP, mid2, lastv);
+    vstmd(DB_W, SP, firstv, mid1);
+  } else {
+    vstmd(DB_W, SP, firstv, lastv);
+  }
 
   ReserveAlignedFrameSpace(frame_space);
 }
@@ -2299,7 +2309,15 @@
   // Restore all volatile FPU registers.
   DRegister firstv = EvenDRegisterOf(kDartFirstVolatileFpuReg);
   DRegister lastv = OddDRegisterOf(kDartLastVolatileFpuReg);
-  vldmd(IA_W, SP, firstv, lastv);
+  if (lastv - firstv > 16) {

[regis, 2013/07/23 17:38:04]

ditto

[zra, 2013/07/23 18:24:14]

Done.

+    ASSERT(kNumberOfDRegisters <= 32);
+    DRegister mid1 = static_cast<DRegister>(firstv + 15);
+    DRegister mid2 = static_cast<DRegister>(firstv + 16);
+    vldmd(IA_W, SP, firstv, mid1);
+    vldmd(IA_W, SP, mid2, lastv);
+  } else {
+    vldmd(IA_W, SP, firstv, lastv);
+  }
 
   // Restore volatile CPU registers.
   LeaveFrame(kDartVolatileCpuRegs | (1 << FP) | (1 << LR));