ARM: fix assertions for uxtb and co.

src/arm/disasm-arm.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 1043 matching lines @@
               UNREACHABLE();
               break;
             case 1:
               UNREACHABLE();
               break;
             case 2:
               if ((instr->Bit(20) == 0) && (instr->Bits(9, 6) == 1)) {
                 if (instr->Bits(19, 16) == 0xF) {
                   switch (instr->Bits(11, 10)) {
                     case 0:
-                      Format(instr, "uxtb16'cond 'rd, 'rm, ror #0");
+                      Format(instr, "uxtb16'cond 'rd, 'rm");
                       break;
                     case 1:
                       Format(instr, "uxtb16'cond 'rd, 'rm, ror #8");
                       break;
                     case 2:
                       Format(instr, "uxtb16'cond 'rd, 'rm, ror #16");
                       break;
                     case 3:
                       Format(instr, "uxtb16'cond 'rd, 'rm, ror #24");
                       break;
                   }
                 } else {
                   UNREACHABLE();
                 }
               } else {
                 UNREACHABLE();
               }
               break;
             case 3:
               if ((instr->Bit(20) == 0) && (instr->Bits(9, 6) == 1)) {
                 if (instr->Bits(19, 16) == 0xF) {
                   switch (instr->Bits(11, 10)) {
                     case 0:
-                      Format(instr, "uxtb'cond 'rd, 'rm, ror #0");
+                      Format(instr, "uxtb'cond 'rd, 'rm");
                       break;
                     case 1:
                       Format(instr, "uxtb'cond 'rd, 'rm, ror #8");
                       break;
                     case 2:
                       Format(instr, "uxtb'cond 'rd, 'rm, ror #16");
                       break;
                     case 3:
                       Format(instr, "uxtb'cond 'rd, 'rm, ror #24");
                       break;
                   }
                 } else {
                   switch (instr->Bits(11, 10)) {
                     case 0:
-                      Format(instr, "uxtab'cond 'rd, 'rn, 'rm, ror #0");
+                      Format(instr, "uxtab'cond 'rd, 'rn, 'rm");
                       break;
                     case 1:
                       Format(instr, "uxtab'cond 'rd, 'rn, 'rm, ror #8");
                       break;
                     case 2:
                       Format(instr, "uxtab'cond 'rd, 'rn, 'rm, ror #16");
                       break;
                     case 3:
                       Format(instr, "uxtab'cond 'rd, 'rn, 'rm, ror #24");
                       break;
@@ skipping 691 matching lines @@
     v8::internal::PrintF(
         f, "%p    %08x      %s\n",
         prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_ARM