opcodes/i386-dis.c - Issue 19803007: Update disassembler in NaCl binutils

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Issue 19803007: Update disassembler in NaCl binutils (Closed) Base URL: http://git.chromium.org/native_client/nacl-binutils.git@master

Patch Set: Created 7 years, 5 months ago

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1 /* Print i386 instructions for GDB, the GNU debugger.	1 /* Print i386 instructions for GDB, the GNU debugger.

2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,	2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,

3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009	3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012

4 Free Software Foundation, Inc.	4 Free Software Foundation, Inc.

5	5

6 This file is part of the GNU opcodes library.	6 This file is part of the GNU opcodes library.

7	7

8 This library is free software; you can redistribute it and/or modify	8 This library is free software; you can redistribute it and/or modify

9 it under the terms of the GNU General Public License as published by	9 it under the terms of the GNU General Public License as published by

10 the Free Software Foundation; either version 3, or (at your option)	10 the Free Software Foundation; either version 3, or (at your option)

11 any later version.	11 any later version.

12	12

13 It is distributed in the hope that it will be useful, but WITHOUT	13 It is distributed in the hope that it will be useful, but WITHOUT

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35 the Intel manual for details. */	35 the Intel manual for details. */

36	36

37 #include "sysdep.h"	37 #include "sysdep.h"

38 #include "dis-asm.h"	38 #include "dis-asm.h"

39 #include "opintl.h"	39 #include "opintl.h"

40 #include "opcode/i386.h"	40 #include "opcode/i386.h"

41 #include "libiberty.h"	41 #include "libiberty.h"

42	42

43 #include <setjmp.h>	43 #include <setjmp.h>

44	44

45 static int fetch_data (struct disassemble_info , bfd_byte );

46 static void ckprefix (void);

47 static const char *prefix_name (int, int);

48 static int print_insn (bfd_vma, disassemble_info *);	45 static int print_insn (bfd_vma, disassemble_info *);

49 static void dofloat (int);	46 static void dofloat (int);

50 static void OP_ST (int, int);	47 static void OP_ST (int, int);

51 static void OP_STi (int, int);	48 static void OP_STi (int, int);

52 static int putop (const char *, int);	49 static int putop (const char *, int);

53 static void oappend (const char *);	50 static void oappend (const char *);

54 static void append_seg (void);	51 static void append_seg (void);

55 static void OP_indirE (int, int);	52 static void OP_indirE (int, int);

56 static void print_operand_value (char *, int, bfd_vma);	53 static void print_operand_value (char *, int, bfd_vma);

57 static void OP_E_register (int, int);	54 static void OP_E_register (int, int);

58 static void OP_E_memory (int, int);	55 static void OP_E_memory (int, int);

59 static void OP_E_extended (int, int);

60 static void print_displacement (char *, bfd_vma);	56 static void print_displacement (char *, bfd_vma);

61 static void OP_E (int, int);	57 static void OP_E (int, int);

62 static void OP_G (int, int);	58 static void OP_G (int, int);

63 static bfd_vma get64 (void);	59 static bfd_vma get64 (void);

64 static bfd_signed_vma get32 (void);	60 static bfd_signed_vma get32 (void);

65 static bfd_signed_vma get32s (void);	61 static bfd_signed_vma get32s (void);

66 static int get16 (void);	62 static int get16 (void);

67 static void set_op (bfd_vma, int);	63 static void set_op (bfd_vma, int);

68 static void OP_Skip_MODRM (int, int);	64 static void OP_Skip_MODRM (int, int);

69 static void OP_REG (int, int);	65 static void OP_REG (int, int);

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86 static void OP_MMX (int, int);	82 static void OP_MMX (int, int);

87 static void OP_XMM (int, int);	83 static void OP_XMM (int, int);

88 static void OP_EM (int, int);	84 static void OP_EM (int, int);

89 static void OP_EX (int, int);	85 static void OP_EX (int, int);

90 static void OP_EMC (int,int);	86 static void OP_EMC (int,int);

91 static void OP_MXC (int,int);	87 static void OP_MXC (int,int);

92 static void OP_MS (int, int);	88 static void OP_MS (int, int);

93 static void OP_XS (int, int);	89 static void OP_XS (int, int);

94 static void OP_M (int, int);	90 static void OP_M (int, int);

95 static void OP_VEX (int, int);	91 static void OP_VEX (int, int);

96 static void OP_VEX_FMA (int, int);

97 static void OP_EX_Vex (int, int);	92 static void OP_EX_Vex (int, int);

98 static void OP_EX_VexW (int, int);	93 static void OP_EX_VexW (int, int);

	94 static void OP_EX_VexImmW (int, int);

99 static void OP_XMM_Vex (int, int);	95 static void OP_XMM_Vex (int, int);

100 static void OP_XMM_VexW (int, int);	96 static void OP_XMM_VexW (int, int);

101 static void OP_REG_VexI4 (int, int);	97 static void OP_REG_VexI4 (int, int);

102 static void PCLMUL_Fixup (int, int);	98 static void PCLMUL_Fixup (int, int);

103 static void VEXI4_Fixup (int, int);	99 static void VEXI4_Fixup (int, int);

104 static void VZERO_Fixup (int, int);	100 static void VZERO_Fixup (int, int);

105 static void VCMP_Fixup (int, int);	101 static void VCMP_Fixup (int, int);

106 static void OP_0f07 (int, int);	102 static void OP_0f07 (int, int);

107 static void OP_Monitor (int, int);	103 static void OP_Monitor (int, int);

108 static void OP_Mwait (int, int);	104 static void OP_Mwait (int, int);

109 static void NOP_Fixup1 (int, int);	105 static void NOP_Fixup1 (int, int);

110 static void NOP_Fixup2 (int, int);	106 static void NOP_Fixup2 (int, int);

111 static void OP_3DNowSuffix (int, int);	107 static void OP_3DNowSuffix (int, int);

112 static void CMP_Fixup (int, int);	108 static void CMP_Fixup (int, int);

113 static void BadOp (void);	109 static void BadOp (void);

114 static void REP_Fixup (int, int);	110 static void REP_Fixup (int, int);

	111 static void HLE_Fixup1 (int, int);

	112 static void HLE_Fixup2 (int, int);

	113 static void HLE_Fixup3 (int, int);

115 static void CMPXCHG8B_Fixup (int, int);	114 static void CMPXCHG8B_Fixup (int, int);

116 static void XMM_Fixup (int, int);	115 static void XMM_Fixup (int, int);

117 static void CRC32_Fixup (int, int);	116 static void CRC32_Fixup (int, int);

	117 static void FXSAVE_Fixup (int, int);

	118 static void OP_LWPCB_E (int, int);

	119 static void OP_LWP_E (int, int);

	120 static void OP_Vex_2src_1 (int, int);

	121 static void OP_Vex_2src_2 (int, int);

118	122

119 static void MOVBE_Fixup (int, int);	123 static void MOVBE_Fixup (int, int);

120	124

121 struct dis_private {	125 struct dis_private {

122 /* Points to first byte not fetched. */	126 /* Points to first byte not fetched. */

123 bfd_byte *max_fetched;	127 bfd_byte *max_fetched;

124 bfd_byte the_buffer[MAX_MNEM_SIZE];	128 bfd_byte the_buffer[MAX_MNEM_SIZE];

125 bfd_vma insn_start;	129 bfd_vma insn_start;

126 int orig_sizeflag;	130 int orig_sizeflag;

127 jmp_buf bailout;	131 jmp_buf bailout;

128 };	132 };

129	133

130 enum address_mode	134 enum address_mode

131 {	135 {

132 mode_16bit,	136 mode_16bit,

133 mode_32bit,	137 mode_32bit,

134 mode_64bit	138 mode_64bit

135 };	139 };

136	140

137 enum address_mode address_mode;	141 enum address_mode address_mode;

138	142

139 /* Flags for the prefixes for the current instruction. See below. */	143 /* Flags for the prefixes for the current instruction. See below. */

140 static int prefixes;	144 static int prefixes;

141	145

142 /* REX prefix the current instruction. See below. */	146 /* REX prefix the current instruction. See below. */

143 static int rex;	147 static int rex;

144 /* Bits of REX we've already used. */	148 /* Bits of REX we've already used. */

145 static int rex_used;	149 static int rex_used;

146 /* Original REX prefix. */	150 /* REX bits in original REX prefix ignored. */

147 static int rex_original;

148 /* REX bits in original REX prefix ignored. It may not be the same

149 as rex_original since some bits may not be ignored. */

150 static int rex_ignored;	151 static int rex_ignored;

151 /* Mark parts used in the REX prefix. When we are testing for	152 /* Mark parts used in the REX prefix. When we are testing for

152 empty prefix (for 8bit register REX extension), just mask it	153 empty prefix (for 8bit register REX extension), just mask it

153 out. Otherwise test for REX bit is excuse for existence of REX	154 out. Otherwise test for REX bit is excuse for existence of REX

154 only in case value is nonzero. */	155 only in case value is nonzero. */

155 #define USED_REX(value) \	156 #define USED_REX(value) \

156 { \	157 { \

157 if (value) \	158 if (value) \

158 { \	159 { \

159 if ((rex & value)) \	160 if ((rex & value)) \

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211 if (priv->max_fetched == priv->the_buffer)	212 if (priv->max_fetched == priv->the_buffer)

212 (*info->memory_error_func) (status, start, info);	213 (*info->memory_error_func) (status, start, info);

213 longjmp (priv->bailout, 1);	214 longjmp (priv->bailout, 1);

214 }	215 }

215 else	216 else

216 priv->max_fetched = addr;	217 priv->max_fetched = addr;

217 return 1;	218 return 1;

218 }	219 }

219	220

220 #define XX { NULL, 0 }	221 #define XX { NULL, 0 }

	222 #define Bad_Opcode NULL, { { NULL, 0 } }

221	223

222 #define Eb { OP_E, b_mode }	224 #define Eb { OP_E, b_mode }

223 #define EbS { OP_E, b_swap_mode }	225 #define EbS { OP_E, b_swap_mode }

224 #define Ev { OP_E, v_mode }	226 #define Ev { OP_E, v_mode }

225 #define EvS { OP_E, v_swap_mode }	227 #define EvS { OP_E, v_swap_mode }

226 #define Ed { OP_E, d_mode }	228 #define Ed { OP_E, d_mode }

227 #define Edq { OP_E, dq_mode }	229 #define Edq { OP_E, dq_mode }

228 #define Edqw { OP_E, dqw_mode }	230 #define Edqw { OP_E, dqw_mode }

229 #define Edqb { OP_E, dqb_mode }	231 #define Edqb { OP_E, dqb_mode }

230 #define Edqd { OP_E, dqd_mode }	232 #define Edqd { OP_E, dqd_mode }

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246 #define Gb { OP_G, b_mode }	248 #define Gb { OP_G, b_mode }

247 #define Gv { OP_G, v_mode }	249 #define Gv { OP_G, v_mode }

248 #define Gd { OP_G, d_mode }	250 #define Gd { OP_G, d_mode }

249 #define Gdq { OP_G, dq_mode }	251 #define Gdq { OP_G, dq_mode }

250 #define Gm { OP_G, m_mode }	252 #define Gm { OP_G, m_mode }

251 #define Gw { OP_G, w_mode }	253 #define Gw { OP_G, w_mode }

252 #define Rd { OP_R, d_mode }	254 #define Rd { OP_R, d_mode }

253 #define Rm { OP_R, m_mode }	255 #define Rm { OP_R, m_mode }

254 #define Ib { OP_I, b_mode }	256 #define Ib { OP_I, b_mode }

255 #define sIb { OP_sI, b_mode } /* sign extened byte */	257 #define sIb { OP_sI, b_mode } /* sign extened byte */

	258 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */

256 #define Iv { OP_I, v_mode }	259 #define Iv { OP_I, v_mode }

	260 #define sIv { OP_sI, v_mode }

257 #define Iq { OP_I, q_mode }	261 #define Iq { OP_I, q_mode }

258 #define Iv64 { OP_I64, v_mode }	262 #define Iv64 { OP_I64, v_mode }

259 #define Iw { OP_I, w_mode }	263 #define Iw { OP_I, w_mode }

260 #define I1 { OP_I, const_1_mode }	264 #define I1 { OP_I, const_1_mode }

261 #define Jb { OP_J, b_mode }	265 #define Jb { OP_J, b_mode }

262 #define Jv { OP_J, v_mode }	266 #define Jv { OP_J, v_mode }

263 #define Cm { OP_C, m_mode }	267 #define Cm { OP_C, m_mode }

264 #define Dm { OP_D, m_mode }	268 #define Dm { OP_D, m_mode }

265 #define Td { OP_T, d_mode }	269 #define Td { OP_T, d_mode }

266 #define Skip_MODRM { OP_Skip_MODRM, 0 }	270 #define Skip_MODRM { OP_Skip_MODRM, 0 }

267	271

268 #define RMeAX { OP_REG, eAX_reg }	272 #define RMeAX { OP_REG, eAX_reg }

269 #define RMeBX { OP_REG, eBX_reg }	273 #define RMeBX { OP_REG, eBX_reg }

270 #define RMeCX { OP_REG, eCX_reg }	274 #define RMeCX { OP_REG, eCX_reg }

271 #define RMeDX { OP_REG, eDX_reg }	275 #define RMeDX { OP_REG, eDX_reg }

272 #define RMeSP { OP_REG, eSP_reg }	276 #define RMeSP { OP_REG, eSP_reg }

273 #define RMeBP { OP_REG, eBP_reg }	277 #define RMeBP { OP_REG, eBP_reg }

274 #define RMeSI { OP_REG, eSI_reg }	278 #define RMeSI { OP_REG, eSI_reg }

275 #define RMeDI { OP_REG, eDI_reg }	279 #define RMeDI { OP_REG, eDI_reg }

276 #define RMrAX { OP_REG, rAX_reg }	280 #define RMrAX { OP_REG, rAX_reg }

277 #define RMrBX { OP_REG, rBX_reg }	281 #define RMrBX { OP_REG, rBX_reg }

278 #define RMrCX { OP_REG, rCX_reg }	282 #define RMrCX { OP_REG, rCX_reg }

279 #define RMrDX { OP_REG, rDX_reg }	283 #define RMrDX { OP_REG, rDX_reg }

280 #define RMrSP { OP_REG, rSP_reg }	284 #define RMrSP { OP_REG, rSP_reg }

281 #define RMrBP { OP_REG, rBP_reg }	285 #define RMrBP { OP_REG, rBP_reg }

282 #define RMrSI { OP_REG, rSI_reg }	286 #define RMrSI { OP_REG, rSI_reg }

283 #define RMrDI { OP_REG, rDI_reg }	287 #define RMrDI { OP_REG, rDI_reg }

284 #define RMAL { OP_REG, al_reg }	288 #define RMAL { OP_REG, al_reg }

285 #define RMAL { OP_REG, al_reg }

286 #define RMCL { OP_REG, cl_reg }	289 #define RMCL { OP_REG, cl_reg }

287 #define RMDL { OP_REG, dl_reg }	290 #define RMDL { OP_REG, dl_reg }

288 #define RMBL { OP_REG, bl_reg }	291 #define RMBL { OP_REG, bl_reg }

289 #define RMAH { OP_REG, ah_reg }	292 #define RMAH { OP_REG, ah_reg }

290 #define RMCH { OP_REG, ch_reg }	293 #define RMCH { OP_REG, ch_reg }

291 #define RMDH { OP_REG, dh_reg }	294 #define RMDH { OP_REG, dh_reg }

292 #define RMBH { OP_REG, bh_reg }	295 #define RMBH { OP_REG, bh_reg }

293 #define RMAX { OP_REG, ax_reg }	296 #define RMAX { OP_REG, ax_reg }

294 #define RMDX { OP_REG, dx_reg }	297 #define RMDX { OP_REG, dx_reg }

295	298

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328	331

329 #define es { OP_REG, es_reg }	332 #define es { OP_REG, es_reg }

330 #define ss { OP_REG, ss_reg }	333 #define ss { OP_REG, ss_reg }

331 #define cs { OP_REG, cs_reg }	334 #define cs { OP_REG, cs_reg }

332 #define ds { OP_REG, ds_reg }	335 #define ds { OP_REG, ds_reg }

333 #define fs { OP_REG, fs_reg }	336 #define fs { OP_REG, fs_reg }

334 #define gs { OP_REG, gs_reg }	337 #define gs { OP_REG, gs_reg }

335	338

336 #define MX { OP_MMX, 0 }	339 #define MX { OP_MMX, 0 }

337 #define XM { OP_XMM, 0 }	340 #define XM { OP_XMM, 0 }

	341 #define XMScalar { OP_XMM, scalar_mode }

	342 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }

338 #define XMM { OP_XMM, xmm_mode }	343 #define XMM { OP_XMM, xmm_mode }

339 #define EM { OP_EM, v_mode }	344 #define EM { OP_EM, v_mode }

340 #define EMS { OP_EM, v_swap_mode }	345 #define EMS { OP_EM, v_swap_mode }

341 #define EMd { OP_EM, d_mode }	346 #define EMd { OP_EM, d_mode }

342 #define EMx { OP_EM, x_mode }	347 #define EMx { OP_EM, x_mode }

343 #define EXw { OP_EX, w_mode }	348 #define EXw { OP_EX, w_mode }

344 #define EXd { OP_EX, d_mode }	349 #define EXd { OP_EX, d_mode }

	350 #define EXdScalar { OP_EX, d_scalar_mode }

345 #define EXdS { OP_EX, d_swap_mode }	351 #define EXdS { OP_EX, d_swap_mode }

346 #define EXq { OP_EX, q_mode }	352 #define EXq { OP_EX, q_mode }

	353 #define EXqScalar { OP_EX, q_scalar_mode }

	354 #define EXqScalarS { OP_EX, q_scalar_swap_mode }

347 #define EXqS { OP_EX, q_swap_mode }	355 #define EXqS { OP_EX, q_swap_mode }

348 #define EXx { OP_EX, x_mode }	356 #define EXx { OP_EX, x_mode }

349 #define EXxS { OP_EX, x_swap_mode }	357 #define EXxS { OP_EX, x_swap_mode }

350 #define EXxmm { OP_EX, xmm_mode }	358 #define EXxmm { OP_EX, xmm_mode }

351 #define EXxmmq { OP_EX, xmmq_mode }	359 #define EXxmmq { OP_EX, xmmq_mode }

	360 #define EXxmm_mb { OP_EX, xmm_mb_mode }

	361 #define EXxmm_mw { OP_EX, xmm_mw_mode }

	362 #define EXxmm_md { OP_EX, xmm_md_mode }

	363 #define EXxmm_mq { OP_EX, xmm_mq_mode }

	364 #define EXxmmdw { OP_EX, xmmdw_mode }

	365 #define EXxmmqd { OP_EX, xmmqd_mode }

352 #define EXymmq { OP_EX, ymmq_mode }	366 #define EXymmq { OP_EX, ymmq_mode }

353 #define EXVexWdq { OP_EX, vex_w_dq_mode }	367 #define EXVexWdq { OP_EX, vex_w_dq_mode }

	368 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }

354 #define MS { OP_MS, v_mode }	369 #define MS { OP_MS, v_mode }

355 #define XS { OP_XS, v_mode }	370 #define XS { OP_XS, v_mode }

356 #define EMCq { OP_EMC, q_mode }	371 #define EMCq { OP_EMC, q_mode }

357 #define MXC { OP_MXC, 0 }	372 #define MXC { OP_MXC, 0 }

358 #define OPSUF { OP_3DNowSuffix, 0 }	373 #define OPSUF { OP_3DNowSuffix, 0 }

359 #define CMP { CMP_Fixup, 0 }	374 #define CMP { CMP_Fixup, 0 }

360 #define XMM0 { XMM_Fixup, 0 }	375 #define XMM0 { XMM_Fixup, 0 }

	376 #define FXSAVE { FXSAVE_Fixup, 0 }

	377 #define Vex_2src_1 { OP_Vex_2src_1, 0 }

	378 #define Vex_2src_2 { OP_Vex_2src_2, 0 }

361	379

362 #define Vex { OP_VEX, vex_mode }	380 #define Vex { OP_VEX, vex_mode }

	381 #define VexScalar { OP_VEX, vex_scalar_mode }

	382 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }

363 #define Vex128 { OP_VEX, vex128_mode }	383 #define Vex128 { OP_VEX, vex128_mode }

364 #define Vex256 { OP_VEX, vex256_mode }	384 #define Vex256 { OP_VEX, vex256_mode }

	385 #define VexGdq { OP_VEX, dq_mode }

365 #define VexI4 { VEXI4_Fixup, 0}	386 #define VexI4 { VEXI4_Fixup, 0}

366 #define VexFMA { OP_VEX_FMA, vex_mode }

367 #define Vex128FMA { OP_VEX_FMA, vex128_mode }

368 #define EXdVex { OP_EX_Vex, d_mode }	387 #define EXdVex { OP_EX_Vex, d_mode }

369 #define EXdVexS { OP_EX_Vex, d_swap_mode }	388 #define EXdVexS { OP_EX_Vex, d_swap_mode }

	389 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }

370 #define EXqVex { OP_EX_Vex, q_mode }	390 #define EXqVex { OP_EX_Vex, q_mode }

371 #define EXqVexS { OP_EX_Vex, q_swap_mode }	391 #define EXqVexS { OP_EX_Vex, q_swap_mode }

	392 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }

372 #define EXVexW { OP_EX_VexW, x_mode }	393 #define EXVexW { OP_EX_VexW, x_mode }

373 #define EXdVexW { OP_EX_VexW, d_mode }	394 #define EXdVexW { OP_EX_VexW, d_mode }

374 #define EXqVexW { OP_EX_VexW, q_mode }	395 #define EXqVexW { OP_EX_VexW, q_mode }

	396 #define EXVexImmW { OP_EX_VexImmW, x_mode }

375 #define XMVex { OP_XMM_Vex, 0 }	397 #define XMVex { OP_XMM_Vex, 0 }

	398 #define XMVexScalar { OP_XMM_Vex, scalar_mode }

376 #define XMVexW { OP_XMM_VexW, 0 }	399 #define XMVexW { OP_XMM_VexW, 0 }

377 #define XMVexI4 { OP_REG_VexI4, x_mode }	400 #define XMVexI4 { OP_REG_VexI4, x_mode }

378 #define PCLMUL { PCLMUL_Fixup, 0 }	401 #define PCLMUL { PCLMUL_Fixup, 0 }

379 #define VZERO { VZERO_Fixup, 0 }	402 #define VZERO { VZERO_Fixup, 0 }

380 #define VCMP { VCMP_Fixup, 0 }	403 #define VCMP { VCMP_Fixup, 0 }

381	404

	405 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }

	406 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }

	407

382 /* Used handle "rep" prefix for string instructions. */	408 /* Used handle "rep" prefix for string instructions. */

383 #define Xbr { REP_Fixup, eSI_reg }	409 #define Xbr { REP_Fixup, eSI_reg }

384 #define Xvr { REP_Fixup, eSI_reg }	410 #define Xvr { REP_Fixup, eSI_reg }

385 #define Ybr { REP_Fixup, eDI_reg }	411 #define Ybr { REP_Fixup, eDI_reg }

386 #define Yvr { REP_Fixup, eDI_reg }	412 #define Yvr { REP_Fixup, eDI_reg }

387 #define Yzr { REP_Fixup, eDI_reg }	413 #define Yzr { REP_Fixup, eDI_reg }

388 #define indirDXr { REP_Fixup, indir_dx_reg }	414 #define indirDXr { REP_Fixup, indir_dx_reg }

389 #define ALr { REP_Fixup, al_reg }	415 #define ALr { REP_Fixup, al_reg }

390 #define eAXr { REP_Fixup, eAX_reg }	416 #define eAXr { REP_Fixup, eAX_reg }

391	417

	418 /* Used handle HLE prefix for lockable instructions. */

	419 #define Ebh1 { HLE_Fixup1, b_mode }

	420 #define Evh1 { HLE_Fixup1, v_mode }

	421 #define Ebh2 { HLE_Fixup2, b_mode }

	422 #define Evh2 { HLE_Fixup2, v_mode }

	423 #define Ebh3 { HLE_Fixup3, b_mode }

	424 #define Evh3 { HLE_Fixup3, v_mode }

	425

392 #define cond_jump_flag { NULL, cond_jump_mode }	426 #define cond_jump_flag { NULL, cond_jump_mode }

393 #define loop_jcxz_flag { NULL, loop_jcxz_mode }	427 #define loop_jcxz_flag { NULL, loop_jcxz_mode }

394	428

395 /* bits in sizeflag */	429 /* bits in sizeflag */

396 #define SUFFIX_ALWAYS 4	430 #define SUFFIX_ALWAYS 4

397 #define AFLAG 2	431 #define AFLAG 2

398 #define DFLAG 1	432 #define DFLAG 1

399	433

400 /* byte operand */	434 enum

401 #define b_mode» » » 1	435 {

402 /* byte operand with operand swapped */	436 /* byte operand */

403 #define b_swap_mode» » (b_mode + 1)	437 b_mode = 1,

404 /* operand size depends on prefixes */	438 /* byte operand with operand swapped */

405 #define v_mode» » » (b_swap_mode + 1)	439 b_swap_mode,

406 /* operand size depends on prefixes with operand swapped */	440 /* byte operand, sign extend like 'T' suffix */

407 #define v_swap_mode» » (v_mode + 1)	441 b_T_mode,

408 /* word operand */	442 /* operand size depends on prefixes */

409 #define w_mode» » » (v_swap_mode + 1)	443 v_mode,

410 /* double word operand */	444 /* operand size depends on prefixes with operand swapped */

411 #define d_mode» » » (w_mode + 1)	445 v_swap_mode,

412 /* double word operand with operand swapped */	446 /* word operand */

413 #define d_swap_mode» » (d_mode + 1)	447 w_mode,

414 /* quad word operand */	448 /* double word operand */

415 #define q_mode» » » (d_swap_mode + 1)	449 d_mode,

416 /* quad word operand with operand swapped */	450 /* double word operand with operand swapped */

417 #define q_swap_mode» » (q_mode + 1)	451 d_swap_mode,

418 /* ten-byte operand */	452 /* quad word operand */

419 #define t_mode» » » (q_swap_mode + 1)	453 q_mode,

420 /* 16-byte XMM or 32-byte YMM operand */	454 /* quad word operand with operand swapped */

421 #define x_mode» » » (t_mode + 1)	455 q_swap_mode,

422 /* 16-byte XMM or 32-byte YMM operand with operand swapped */	456 /* ten-byte operand */

423 #define x_swap_mode» » (x_mode + 1)	457 t_mode,

424 /* 16-byte XMM operand */	458 /* 16-byte XMM or 32-byte YMM operand */

425 #define xmm_mode» » (x_swap_mode + 1)	459 x_mode,

426 /* 16-byte XMM or quad word operand */	460 /* 16-byte XMM or 32-byte YMM operand with operand swapped */

427 #define xmmq_mode» » (xmm_mode + 1)	461 x_swap_mode,

428 /* 32-byte YMM or quad word operand */	462 /* 16-byte XMM operand */

429 #define ymmq_mode» » (xmmq_mode + 1)	463 xmm_mode,

430 /* d_mode in 32bit, q_mode in 64bit mode. */	464 /* 16-byte XMM or quad word operand */

431 #define m_mode» » » (ymmq_mode + 1)	465 xmmq_mode,

432 /* pair of v_mode operands */	466 /* XMM register or byte memory operand */

433 #define a_mode» » » (m_mode + 1)	467 xmm_mb_mode,

434 #define cond_jump_mode» » (a_mode + 1)	468 /* XMM register or word memory operand */

435 #define loop_jcxz_mode» » (cond_jump_mode + 1)	469 xmm_mw_mode,

436 /* operand size depends on REX prefixes. */	470 /* XMM register or double word memory operand */

437 #define dq_mode»» » (loop_jcxz_mode + 1)	471 xmm_md_mode,

438 /* registers like dq_mode, memory like w_mode. */	472 /* XMM register or quad word memory operand */

439 #define dqw_mode» » (dq_mode + 1)	473 xmm_mq_mode,

440 /* 4- or 6-byte pointer operand */	474 /* 16-byte XMM, word or double word operand */

441 #define f_mode» » » (dqw_mode + 1)	475 xmmdw_mode,

442 #define const_1_mode» » (f_mode + 1)	476 /* 16-byte XMM, double word or quad word operand */

443 /* v_mode for stack-related opcodes. */	477 xmmqd_mode,

444 #define stack_v_mode» » (const_1_mode + 1)	478 /* 32-byte YMM or quad word operand */

445 /* non-quad operand size depends on prefixes */	479 ymmq_mode,

446 #define z_mode» » » (stack_v_mode + 1)	480 /* 32-byte YMM or 16-byte word operand */

447 /* 16-byte operand */	481 ymmxmm_mode,

448 #define o_mode» » » (z_mode + 1)	482 /* d_mode in 32bit, q_mode in 64bit mode. */

449 /* registers like dq_mode, memory like b_mode. */	483 m_mode,

450 #define dqb_mode» » (o_mode + 1)	484 /* pair of v_mode operands */

451 /* registers like dq_mode, memory like d_mode. */	485 a_mode,

452 #define dqd_mode» » (dqb_mode + 1)	486 cond_jump_mode,

453 /* normal vex mode */	487 loop_jcxz_mode,

454 #define vex_mode» » (dqd_mode + 1)	488 /* operand size depends on REX prefixes. */

455 /* 128bit vex mode */	489 dq_mode,

456 #define vex128_mode» » (vex_mode + 1)	490 /* registers like dq_mode, memory like w_mode. */

457 /* 256bit vex mode */	491 dqw_mode,

458 #define vex256_mode» » (vex128_mode + 1)	492 /* 4- or 6-byte pointer operand */

459 /* operand size depends on the VEX.W bit. */	493 f_mode,

460 #define vex_w_dq_mode» » (vex256_mode + 1)	494 const_1_mode,

	495 /* v_mode for stack-related opcodes. */

	496 stack_v_mode,

	497 /* non-quad operand size depends on prefixes */

	498 z_mode,

	499 /* 16-byte operand */

	500 o_mode,

	501 /* registers like dq_mode, memory like b_mode. */

	502 dqb_mode,

	503 /* registers like dq_mode, memory like d_mode. */

	504 dqd_mode,

	505 /* normal vex mode */

	506 vex_mode,

	507 /* 128bit vex mode */

	508 vex128_mode,

	509 /* 256bit vex mode */

	510 vex256_mode,

	511 /* operand size depends on the VEX.W bit. */

	512 vex_w_dq_mode,

461	513

462 #define es_reg» » » (vex_w_dq_mode + 1)	514 /* Similar to vex_w_dq_mode, with VSIB dword indices. */

463 #define cs_reg» » » (es_reg + 1)	515 vex_vsib_d_w_dq_mode,

464 #define ss_reg» » » (cs_reg + 1)	516 /* Similar to vex_w_dq_mode, with VSIB qword indices. */

465 #define ds_reg» » » (ss_reg + 1)	517 vex_vsib_q_w_dq_mode,

466 #define fs_reg» » » (ds_reg + 1)

467 #define gs_reg» » » (fs_reg + 1)

468	518

469 #define eAX_reg»» » (gs_reg + 1)	519 /* scalar, ignore vector length. */

470 #define eCX_reg»» » (eAX_reg + 1)	520 scalar_mode,

471 #define eDX_reg»» » (eCX_reg + 1)	521 /* like d_mode, ignore vector length. */

472 #define eBX_reg»» » (eDX_reg + 1)	522 d_scalar_mode,

473 #define eSP_reg»» » (eBX_reg + 1)	523 /* like d_swap_mode, ignore vector length. */

474 #define eBP_reg»» » (eSP_reg + 1)	524 d_scalar_swap_mode,

475 #define eSI_reg»» » (eBP_reg + 1)	525 /* like q_mode, ignore vector length. */

476 #define eDI_reg»» » (eSI_reg + 1)	526 q_scalar_mode,

	527 /* like q_swap_mode, ignore vector length. */

	528 q_scalar_swap_mode,

	529 /* like vex_mode, ignore vector length. */

	530 vex_scalar_mode,

	531 /* like vex_w_dq_mode, ignore vector length. */

	532 vex_scalar_w_dq_mode,

477	533

478 #define al_reg» » » (eDI_reg + 1)	534 es_reg,

479 #define cl_reg» » » (al_reg + 1)	535 cs_reg,

480 #define dl_reg» » » (cl_reg + 1)	536 ss_reg,

481 #define bl_reg» » » (dl_reg + 1)	537 ds_reg,

482 #define ah_reg» » » (bl_reg + 1)	538 fs_reg,

483 #define ch_reg» » » (ah_reg + 1)	539 gs_reg,

484 #define dh_reg» » » (ch_reg + 1)

485 #define bh_reg» » » (dh_reg + 1)

486	540

487 #define ax_reg» » » (bh_reg + 1)	541 eAX_reg,

488 #define cx_reg» » » (ax_reg + 1)	542 eCX_reg,

489 #define dx_reg» » » (cx_reg + 1)	543 eDX_reg,

490 #define bx_reg» » » (dx_reg + 1)	544 eBX_reg,

491 #define sp_reg» » » (bx_reg + 1)	545 eSP_reg,

492 #define bp_reg» » » (sp_reg + 1)	546 eBP_reg,

493 #define si_reg» » » (bp_reg + 1)	547 eSI_reg,

494 #define di_reg» » » (si_reg + 1)	548 eDI_reg,

495	549

496 #define rAX_reg»» » (di_reg + 1)	550 al_reg,

497 #define rCX_reg»» » (rAX_reg + 1)	551 cl_reg,

498 #define rDX_reg»» » (rCX_reg + 1)	552 dl_reg,

499 #define rBX_reg»» » (rDX_reg + 1)	553 bl_reg,

500 #define rSP_reg»» » (rBX_reg + 1)	554 ah_reg,

501 #define rBP_reg»» » (rSP_reg + 1)	555 ch_reg,

502 #define rSI_reg»» » (rBP_reg + 1)	556 dh_reg,

503 #define rDI_reg»» » (rSI_reg + 1)	557 bh_reg,

504	558

505 #define z_mode_ax_reg» » (rDI_reg + 1)	559 ax_reg,

506 #define indir_dx_reg» » (z_mode_ax_reg + 1)	560 cx_reg,

	561 dx_reg,

	562 bx_reg,

	563 sp_reg,

	564 bp_reg,

	565 si_reg,

	566 di_reg,

507	567

508 #define MAX_BYTEMODE» indir_dx_reg	568 rAX_reg,

	569 rCX_reg,

	570 rDX_reg,

	571 rBX_reg,

	572 rSP_reg,

	573 rBP_reg,

	574 rSI_reg,

	575 rDI_reg,

509	576

	577 z_mode_ax_reg,

	578 indir_dx_reg

	579 };

510	580

511 #define FLOATCODE» » 1	581 enum

512 #define USE_REG_TABLE» » (FLOATCODE + 1)	582 {

513 #define USE_MOD_TABLE» » (USE_REG_TABLE + 1)	583 FLOATCODE = 1,

514 #define USE_RM_TABLE» » (USE_MOD_TABLE + 1)	584 USE_REG_TABLE,

515 #define USE_PREFIX_TABLE» (USE_RM_TABLE + 1)	585 USE_MOD_TABLE,

516 #define USE_X86_64_TABLE» (USE_PREFIX_TABLE + 1)	586 USE_RM_TABLE,

517 #define USE_3BYTE_TABLE»» (USE_X86_64_TABLE + 1)	587 USE_PREFIX_TABLE,

518 #define USE_VEX_C4_TABLE» (USE_3BYTE_TABLE + 1)	588 USE_X86_64_TABLE,

519 #define USE_VEX_C5_TABLE» (USE_VEX_C4_TABLE + 1)	589 USE_3BYTE_TABLE,

520 #define USE_VEX_LEN_TABLE» (USE_VEX_C5_TABLE + 1)	590 USE_XOP_8F_TABLE,

	591 USE_VEX_C4_TABLE,

	592 USE_VEX_C5_TABLE,

	593 USE_VEX_LEN_TABLE,

	594 USE_VEX_W_TABLE

	595 };

521	596

522 #define FLOAT NULL, { { NULL, FLOATCODE } }	597 #define FLOAT NULL, { { NULL, FLOATCODE } }

523	598

524 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }	599 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }

525 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))	600 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))

526 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))	601 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))

527 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))	602 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))

528 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))	603 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))

529 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))	604 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))

530 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))	605 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))

	606 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))

531 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))	607 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))

532 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))	608 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))

533 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))	609 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))

	610 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))

534	611

535 enum	612 enum

536 {	613 {

537 REG_80 = 0,	614 REG_80 = 0,

538 REG_81,	615 REG_81,

539 REG_82,	616 REG_82,

540 REG_8F,	617 REG_8F,

541 REG_C0,	618 REG_C0,

542 REG_C1,	619 REG_C1,

543 REG_C6,	620 REG_C6,

(...skipping 11 matching lines...) Expand all Loading...
555 REG_0F0D,	632 REG_0F0D,

556 REG_0F18,	633 REG_0F18,

557 REG_0F71,	634 REG_0F71,

558 REG_0F72,	635 REG_0F72,

559 REG_0F73,	636 REG_0F73,

560 REG_0FA6,	637 REG_0FA6,

561 REG_0FA7,	638 REG_0FA7,

562 REG_0FAE,	639 REG_0FAE,

563 REG_0FBA,	640 REG_0FBA,

564 REG_0FC7,	641 REG_0FC7,

565 REG_VEX_71,	642 REG_VEX_0F71,

566 REG_VEX_72,	643 REG_VEX_0F72,

567 REG_VEX_73,	644 REG_VEX_0F73,

568 REG_VEX_AE	645 REG_VEX_0FAE,

	646 REG_VEX_0F38F3,

	647 REG_XOP_LWPCB,

	648 REG_XOP_LWP,

	649 REG_XOP_TBM_01,

	650 REG_XOP_TBM_02

569 };	651 };

570	652

571 enum	653 enum

572 {	654 {

573 MOD_8D = 0,	655 MOD_8D = 0,

	656 MOD_C6_REG_7,

	657 MOD_C7_REG_7,

574 MOD_0F01_REG_0,	658 MOD_0F01_REG_0,

575 MOD_0F01_REG_1,	659 MOD_0F01_REG_1,

576 MOD_0F01_REG_2,	660 MOD_0F01_REG_2,

577 MOD_0F01_REG_3,	661 MOD_0F01_REG_3,

578 MOD_0F01_REG_7,	662 MOD_0F01_REG_7,

579 MOD_0F12_PREFIX_0,	663 MOD_0F12_PREFIX_0,

580 MOD_0F13,	664 MOD_0F13,

581 MOD_0F16_PREFIX_0,	665 MOD_0F16_PREFIX_0,

582 MOD_0F17,	666 MOD_0F17,

583 MOD_0F18_REG_0,	667 MOD_0F18_REG_0,

584 MOD_0F18_REG_1,	668 MOD_0F18_REG_1,

585 MOD_0F18_REG_2,	669 MOD_0F18_REG_2,

586 MOD_0F18_REG_3,	670 MOD_0F18_REG_3,

	671 MOD_0F18_REG_4,

	672 MOD_0F18_REG_5,

	673 MOD_0F18_REG_6,

	674 MOD_0F18_REG_7,

587 MOD_0F20,	675 MOD_0F20,

588 MOD_0F21,	676 MOD_0F21,

589 MOD_0F22,	677 MOD_0F22,

590 MOD_0F23,	678 MOD_0F23,

591 MOD_0F24,	679 MOD_0F24,

592 MOD_0F26,	680 MOD_0F26,

593 MOD_0F2B_PREFIX_0,	681 MOD_0F2B_PREFIX_0,

594 MOD_0F2B_PREFIX_1,	682 MOD_0F2B_PREFIX_1,

595 MOD_0F2B_PREFIX_2,	683 MOD_0F2B_PREFIX_2,

596 MOD_0F2B_PREFIX_3,	684 MOD_0F2B_PREFIX_3,

(...skipping 21 matching lines...) Expand all Loading...
618 MOD_0FB5,	706 MOD_0FB5,

619 MOD_0FC7_REG_6,	707 MOD_0FC7_REG_6,

620 MOD_0FC7_REG_7,	708 MOD_0FC7_REG_7,

621 MOD_0FD7,	709 MOD_0FD7,

622 MOD_0FE7_PREFIX_2,	710 MOD_0FE7_PREFIX_2,

623 MOD_0FF0_PREFIX_3,	711 MOD_0FF0_PREFIX_3,

624 MOD_0F382A_PREFIX_2,	712 MOD_0F382A_PREFIX_2,

625 MOD_62_32BIT,	713 MOD_62_32BIT,

626 MOD_C4_32BIT,	714 MOD_C4_32BIT,

627 MOD_C5_32BIT,	715 MOD_C5_32BIT,

628 MOD_VEX_12_PREFIX_0,	716 MOD_VEX_0F12_PREFIX_0,

629 MOD_VEX_13,	717 MOD_VEX_0F13,

630 MOD_VEX_16_PREFIX_0,	718 MOD_VEX_0F16_PREFIX_0,

631 MOD_VEX_17,	719 MOD_VEX_0F17,

632 MOD_VEX_2B,	720 MOD_VEX_0F2B,

633 MOD_VEX_51,	721 MOD_VEX_0F50,

634 MOD_VEX_71_REG_2,	722 MOD_VEX_0F71_REG_2,

635 MOD_VEX_71_REG_4,	723 MOD_VEX_0F71_REG_4,

636 MOD_VEX_71_REG_6,	724 MOD_VEX_0F71_REG_6,

637 MOD_VEX_72_REG_2,	725 MOD_VEX_0F72_REG_2,

638 MOD_VEX_72_REG_4,	726 MOD_VEX_0F72_REG_4,

639 MOD_VEX_72_REG_6,	727 MOD_VEX_0F72_REG_6,

640 MOD_VEX_73_REG_2,	728 MOD_VEX_0F73_REG_2,

641 MOD_VEX_73_REG_3,	729 MOD_VEX_0F73_REG_3,

642 MOD_VEX_73_REG_6,	730 MOD_VEX_0F73_REG_6,

643 MOD_VEX_73_REG_7,	731 MOD_VEX_0F73_REG_7,

644 MOD_VEX_AE_REG_2,	732 MOD_VEX_0FAE_REG_2,

645 MOD_VEX_AE_REG_3,	733 MOD_VEX_0FAE_REG_3,

646 MOD_VEX_D7_PREFIX_2,	734 MOD_VEX_0FD7_PREFIX_2,

647 MOD_VEX_E7_PREFIX_2,	735 MOD_VEX_0FE7_PREFIX_2,

648 MOD_VEX_F0_PREFIX_3,	736 MOD_VEX_0FF0_PREFIX_3,

649 MOD_VEX_3818_PREFIX_2,	737 MOD_VEX_0F381A_PREFIX_2,

650 MOD_VEX_3819_PREFIX_2,	738 MOD_VEX_0F382A_PREFIX_2,

651 MOD_VEX_381A_PREFIX_2,	739 MOD_VEX_0F382C_PREFIX_2,

652 MOD_VEX_382A_PREFIX_2,	740 MOD_VEX_0F382D_PREFIX_2,

653 MOD_VEX_382C_PREFIX_2,	741 MOD_VEX_0F382E_PREFIX_2,

654 MOD_VEX_382D_PREFIX_2,	742 MOD_VEX_0F382F_PREFIX_2,

655 MOD_VEX_382E_PREFIX_2,	743 MOD_VEX_0F385A_PREFIX_2,

656 MOD_VEX_382F_PREFIX_2	744 MOD_VEX_0F388C_PREFIX_2,

	745 MOD_VEX_0F388E_PREFIX_2,

657 };	746 };

658	747

659 enum	748 enum

660 {	749 {

661 RM_0F01_REG_0 = 0,	750 RM_C6_REG_7 = 0,

	751 RM_C7_REG_7,

	752 RM_0F01_REG_0,

662 RM_0F01_REG_1,	753 RM_0F01_REG_1,

663 RM_0F01_REG_2,	754 RM_0F01_REG_2,

664 RM_0F01_REG_3,	755 RM_0F01_REG_3,

665 RM_0F01_REG_7,	756 RM_0F01_REG_7,

666 RM_0FAE_REG_5,	757 RM_0FAE_REG_5,

667 RM_0FAE_REG_6,	758 RM_0FAE_REG_6,

668 RM_0FAE_REG_7	759 RM_0FAE_REG_7

669 };	760 };

670	761

671 enum	762 enum

(...skipping 28 matching lines...) Expand all Loading...
700 PREFIX_0F6F,	791 PREFIX_0F6F,

701 PREFIX_0F70,	792 PREFIX_0F70,

702 PREFIX_0F73_REG_3,	793 PREFIX_0F73_REG_3,

703 PREFIX_0F73_REG_7,	794 PREFIX_0F73_REG_7,

704 PREFIX_0F78,	795 PREFIX_0F78,

705 PREFIX_0F79,	796 PREFIX_0F79,

706 PREFIX_0F7C,	797 PREFIX_0F7C,

707 PREFIX_0F7D,	798 PREFIX_0F7D,

708 PREFIX_0F7E,	799 PREFIX_0F7E,

709 PREFIX_0F7F,	800 PREFIX_0F7F,

	801 PREFIX_0FAE_REG_0,

	802 PREFIX_0FAE_REG_1,

	803 PREFIX_0FAE_REG_2,

	804 PREFIX_0FAE_REG_3,

710 PREFIX_0FB8,	805 PREFIX_0FB8,

	806 PREFIX_0FBC,

711 PREFIX_0FBD,	807 PREFIX_0FBD,

712 PREFIX_0FC2,	808 PREFIX_0FC2,

713 PREFIX_0FC3,	809 PREFIX_0FC3,

714 PREFIX_0FC7_REG_6,	810 PREFIX_0FC7_REG_6,

715 PREFIX_0FD0,	811 PREFIX_0FD0,

716 PREFIX_0FD6,	812 PREFIX_0FD6,

717 PREFIX_0FE6,	813 PREFIX_0FE6,

718 PREFIX_0FE7,	814 PREFIX_0FE7,

719 PREFIX_0FF0,	815 PREFIX_0FF0,

720 PREFIX_0FF7,	816 PREFIX_0FF7,

(...skipping 23 matching lines...) Expand all Loading...
744 PREFIX_0F383A,	840 PREFIX_0F383A,

745 PREFIX_0F383B,	841 PREFIX_0F383B,

746 PREFIX_0F383C,	842 PREFIX_0F383C,

747 PREFIX_0F383D,	843 PREFIX_0F383D,

748 PREFIX_0F383E,	844 PREFIX_0F383E,

749 PREFIX_0F383F,	845 PREFIX_0F383F,

750 PREFIX_0F3840,	846 PREFIX_0F3840,

751 PREFIX_0F3841,	847 PREFIX_0F3841,

752 PREFIX_0F3880,	848 PREFIX_0F3880,

753 PREFIX_0F3881,	849 PREFIX_0F3881,

	850 PREFIX_0F3882,

754 PREFIX_0F38DB,	851 PREFIX_0F38DB,

755 PREFIX_0F38DC,	852 PREFIX_0F38DC,

756 PREFIX_0F38DD,	853 PREFIX_0F38DD,

757 PREFIX_0F38DE,	854 PREFIX_0F38DE,

758 PREFIX_0F38DF,	855 PREFIX_0F38DF,

759 PREFIX_0F38F0,	856 PREFIX_0F38F0,

760 PREFIX_0F38F1,	857 PREFIX_0F38F1,

	858 PREFIX_0F38F6,

761 PREFIX_0F3A08,	859 PREFIX_0F3A08,

762 PREFIX_0F3A09,	860 PREFIX_0F3A09,

763 PREFIX_0F3A0A,	861 PREFIX_0F3A0A,

764 PREFIX_0F3A0B,	862 PREFIX_0F3A0B,

765 PREFIX_0F3A0C,	863 PREFIX_0F3A0C,

766 PREFIX_0F3A0D,	864 PREFIX_0F3A0D,

767 PREFIX_0F3A0E,	865 PREFIX_0F3A0E,

768 PREFIX_0F3A14,	866 PREFIX_0F3A14,

769 PREFIX_0F3A15,	867 PREFIX_0F3A15,

770 PREFIX_0F3A16,	868 PREFIX_0F3A16,

771 PREFIX_0F3A17,	869 PREFIX_0F3A17,

772 PREFIX_0F3A20,	870 PREFIX_0F3A20,

773 PREFIX_0F3A21,	871 PREFIX_0F3A21,

774 PREFIX_0F3A22,	872 PREFIX_0F3A22,

775 PREFIX_0F3A40,	873 PREFIX_0F3A40,

776 PREFIX_0F3A41,	874 PREFIX_0F3A41,

777 PREFIX_0F3A42,	875 PREFIX_0F3A42,

778 PREFIX_0F3A44,	876 PREFIX_0F3A44,

779 PREFIX_0F3A60,	877 PREFIX_0F3A60,

780 PREFIX_0F3A61,	878 PREFIX_0F3A61,

781 PREFIX_0F3A62,	879 PREFIX_0F3A62,

782 PREFIX_0F3A63,	880 PREFIX_0F3A63,

783 PREFIX_0F3ADF,	881 PREFIX_0F3ADF,

784 PREFIX_VEX_10,	882 PREFIX_VEX_0F10,

785 PREFIX_VEX_11,	883 PREFIX_VEX_0F11,

786 PREFIX_VEX_12,	884 PREFIX_VEX_0F12,

787 PREFIX_VEX_16,	885 PREFIX_VEX_0F16,

788 PREFIX_VEX_2A,	886 PREFIX_VEX_0F2A,

789 PREFIX_VEX_2C,	887 PREFIX_VEX_0F2C,

790 PREFIX_VEX_2D,	888 PREFIX_VEX_0F2D,

791 PREFIX_VEX_2E,	889 PREFIX_VEX_0F2E,

792 PREFIX_VEX_2F,	890 PREFIX_VEX_0F2F,

793 PREFIX_VEX_51,	891 PREFIX_VEX_0F51,

794 PREFIX_VEX_52,	892 PREFIX_VEX_0F52,

795 PREFIX_VEX_53,	893 PREFIX_VEX_0F53,

796 PREFIX_VEX_58,	894 PREFIX_VEX_0F58,

797 PREFIX_VEX_59,	895 PREFIX_VEX_0F59,

798 PREFIX_VEX_5A,	896 PREFIX_VEX_0F5A,

799 PREFIX_VEX_5B,	897 PREFIX_VEX_0F5B,

800 PREFIX_VEX_5C,	898 PREFIX_VEX_0F5C,

801 PREFIX_VEX_5D,	899 PREFIX_VEX_0F5D,

802 PREFIX_VEX_5E,	900 PREFIX_VEX_0F5E,

803 PREFIX_VEX_5F,	901 PREFIX_VEX_0F5F,

804 PREFIX_VEX_60,	902 PREFIX_VEX_0F60,

805 PREFIX_VEX_61,	903 PREFIX_VEX_0F61,

806 PREFIX_VEX_62,	904 PREFIX_VEX_0F62,

807 PREFIX_VEX_63,	905 PREFIX_VEX_0F63,

808 PREFIX_VEX_64,	906 PREFIX_VEX_0F64,

809 PREFIX_VEX_65,	907 PREFIX_VEX_0F65,

810 PREFIX_VEX_66,	908 PREFIX_VEX_0F66,

811 PREFIX_VEX_67,	909 PREFIX_VEX_0F67,

812 PREFIX_VEX_68,	910 PREFIX_VEX_0F68,

813 PREFIX_VEX_69,	911 PREFIX_VEX_0F69,

814 PREFIX_VEX_6A,	912 PREFIX_VEX_0F6A,

815 PREFIX_VEX_6B,	913 PREFIX_VEX_0F6B,

816 PREFIX_VEX_6C,	914 PREFIX_VEX_0F6C,

817 PREFIX_VEX_6D,	915 PREFIX_VEX_0F6D,

818 PREFIX_VEX_6E,	916 PREFIX_VEX_0F6E,

819 PREFIX_VEX_6F,	917 PREFIX_VEX_0F6F,

820 PREFIX_VEX_70,	918 PREFIX_VEX_0F70,

821 PREFIX_VEX_71_REG_2,	919 PREFIX_VEX_0F71_REG_2,

822 PREFIX_VEX_71_REG_4,	920 PREFIX_VEX_0F71_REG_4,

823 PREFIX_VEX_71_REG_6,	921 PREFIX_VEX_0F71_REG_6,

824 PREFIX_VEX_72_REG_2,	922 PREFIX_VEX_0F72_REG_2,

825 PREFIX_VEX_72_REG_4,	923 PREFIX_VEX_0F72_REG_4,

826 PREFIX_VEX_72_REG_6,	924 PREFIX_VEX_0F72_REG_6,

827 PREFIX_VEX_73_REG_2,	925 PREFIX_VEX_0F73_REG_2,

828 PREFIX_VEX_73_REG_3,	926 PREFIX_VEX_0F73_REG_3,

829 PREFIX_VEX_73_REG_6,	927 PREFIX_VEX_0F73_REG_6,

830 PREFIX_VEX_73_REG_7,	928 PREFIX_VEX_0F73_REG_7,

831 PREFIX_VEX_74,	929 PREFIX_VEX_0F74,

832 PREFIX_VEX_75,	930 PREFIX_VEX_0F75,

833 PREFIX_VEX_76,	931 PREFIX_VEX_0F76,

834 PREFIX_VEX_77,	932 PREFIX_VEX_0F77,

835 PREFIX_VEX_7C,	933 PREFIX_VEX_0F7C,

836 PREFIX_VEX_7D,	934 PREFIX_VEX_0F7D,

837 PREFIX_VEX_7E,	935 PREFIX_VEX_0F7E,

838 PREFIX_VEX_7F,	936 PREFIX_VEX_0F7F,

839 PREFIX_VEX_C2,	937 PREFIX_VEX_0FC2,

840 PREFIX_VEX_C4,	938 PREFIX_VEX_0FC4,

841 PREFIX_VEX_C5,	939 PREFIX_VEX_0FC5,

842 PREFIX_VEX_D0,	940 PREFIX_VEX_0FD0,

843 PREFIX_VEX_D1,	941 PREFIX_VEX_0FD1,

844 PREFIX_VEX_D2,	942 PREFIX_VEX_0FD2,

845 PREFIX_VEX_D3,	943 PREFIX_VEX_0FD3,

846 PREFIX_VEX_D4,	944 PREFIX_VEX_0FD4,

847 PREFIX_VEX_D5,	945 PREFIX_VEX_0FD5,

848 PREFIX_VEX_D6,	946 PREFIX_VEX_0FD6,

849 PREFIX_VEX_D7,	947 PREFIX_VEX_0FD7,

850 PREFIX_VEX_D8,	948 PREFIX_VEX_0FD8,

851 PREFIX_VEX_D9,	949 PREFIX_VEX_0FD9,

852 PREFIX_VEX_DA,	950 PREFIX_VEX_0FDA,

853 PREFIX_VEX_DB,	951 PREFIX_VEX_0FDB,

854 PREFIX_VEX_DC,	952 PREFIX_VEX_0FDC,

855 PREFIX_VEX_DD,	953 PREFIX_VEX_0FDD,

856 PREFIX_VEX_DE,	954 PREFIX_VEX_0FDE,

857 PREFIX_VEX_DF,	955 PREFIX_VEX_0FDF,

858 PREFIX_VEX_E0,	956 PREFIX_VEX_0FE0,

859 PREFIX_VEX_E1,	957 PREFIX_VEX_0FE1,

860 PREFIX_VEX_E2,	958 PREFIX_VEX_0FE2,

861 PREFIX_VEX_E3,	959 PREFIX_VEX_0FE3,

862 PREFIX_VEX_E4,	960 PREFIX_VEX_0FE4,

863 PREFIX_VEX_E5,	961 PREFIX_VEX_0FE5,

864 PREFIX_VEX_E6,	962 PREFIX_VEX_0FE6,

865 PREFIX_VEX_E7,	963 PREFIX_VEX_0FE7,

866 PREFIX_VEX_E8,	964 PREFIX_VEX_0FE8,

867 PREFIX_VEX_E9,	965 PREFIX_VEX_0FE9,

868 PREFIX_VEX_EA,	966 PREFIX_VEX_0FEA,

869 PREFIX_VEX_EB,	967 PREFIX_VEX_0FEB,

870 PREFIX_VEX_EC,	968 PREFIX_VEX_0FEC,

871 PREFIX_VEX_ED,	969 PREFIX_VEX_0FED,

872 PREFIX_VEX_EE,	970 PREFIX_VEX_0FEE,

873 PREFIX_VEX_EF,	971 PREFIX_VEX_0FEF,

874 PREFIX_VEX_F0,	972 PREFIX_VEX_0FF0,

875 PREFIX_VEX_F1,	973 PREFIX_VEX_0FF1,

876 PREFIX_VEX_F2,	974 PREFIX_VEX_0FF2,

877 PREFIX_VEX_F3,	975 PREFIX_VEX_0FF3,

878 PREFIX_VEX_F4,	976 PREFIX_VEX_0FF4,

879 PREFIX_VEX_F5,	977 PREFIX_VEX_0FF5,

880 PREFIX_VEX_F6,	978 PREFIX_VEX_0FF6,

881 PREFIX_VEX_F7,	979 PREFIX_VEX_0FF7,

882 PREFIX_VEX_F8,	980 PREFIX_VEX_0FF8,

883 PREFIX_VEX_F9,	981 PREFIX_VEX_0FF9,

884 PREFIX_VEX_FA,	982 PREFIX_VEX_0FFA,

885 PREFIX_VEX_FB,	983 PREFIX_VEX_0FFB,

886 PREFIX_VEX_FC,	984 PREFIX_VEX_0FFC,

887 PREFIX_VEX_FD,	985 PREFIX_VEX_0FFD,

888 PREFIX_VEX_FE,	986 PREFIX_VEX_0FFE,

889 PREFIX_VEX_3800,	987 PREFIX_VEX_0F3800,

890 PREFIX_VEX_3801,	988 PREFIX_VEX_0F3801,

891 PREFIX_VEX_3802,	989 PREFIX_VEX_0F3802,

892 PREFIX_VEX_3803,	990 PREFIX_VEX_0F3803,

893 PREFIX_VEX_3804,	991 PREFIX_VEX_0F3804,

894 PREFIX_VEX_3805,	992 PREFIX_VEX_0F3805,

895 PREFIX_VEX_3806,	993 PREFIX_VEX_0F3806,

896 PREFIX_VEX_3807,	994 PREFIX_VEX_0F3807,

897 PREFIX_VEX_3808,	995 PREFIX_VEX_0F3808,

898 PREFIX_VEX_3809,	996 PREFIX_VEX_0F3809,

899 PREFIX_VEX_380A,	997 PREFIX_VEX_0F380A,

900 PREFIX_VEX_380B,	998 PREFIX_VEX_0F380B,

901 PREFIX_VEX_380C,	999 PREFIX_VEX_0F380C,

902 PREFIX_VEX_380D,	1000 PREFIX_VEX_0F380D,

903 PREFIX_VEX_380E,	1001 PREFIX_VEX_0F380E,

904 PREFIX_VEX_380F,	1002 PREFIX_VEX_0F380F,

905 PREFIX_VEX_3817,	1003 PREFIX_VEX_0F3813,

906 PREFIX_VEX_3818,	1004 PREFIX_VEX_0F3816,

907 PREFIX_VEX_3819,	1005 PREFIX_VEX_0F3817,

908 PREFIX_VEX_381A,	1006 PREFIX_VEX_0F3818,

909 PREFIX_VEX_381C,	1007 PREFIX_VEX_0F3819,

910 PREFIX_VEX_381D,	1008 PREFIX_VEX_0F381A,

911 PREFIX_VEX_381E,	1009 PREFIX_VEX_0F381C,

912 PREFIX_VEX_3820,	1010 PREFIX_VEX_0F381D,

913 PREFIX_VEX_3821,	1011 PREFIX_VEX_0F381E,

914 PREFIX_VEX_3822,	1012 PREFIX_VEX_0F3820,

915 PREFIX_VEX_3823,	1013 PREFIX_VEX_0F3821,

916 PREFIX_VEX_3824,	1014 PREFIX_VEX_0F3822,

917 PREFIX_VEX_3825,	1015 PREFIX_VEX_0F3823,

918 PREFIX_VEX_3828,	1016 PREFIX_VEX_0F3824,

919 PREFIX_VEX_3829,	1017 PREFIX_VEX_0F3825,

920 PREFIX_VEX_382A,	1018 PREFIX_VEX_0F3828,

921 PREFIX_VEX_382B,	1019 PREFIX_VEX_0F3829,

922 PREFIX_VEX_382C,	1020 PREFIX_VEX_0F382A,

923 PREFIX_VEX_382D,	1021 PREFIX_VEX_0F382B,

924 PREFIX_VEX_382E,	1022 PREFIX_VEX_0F382C,

925 PREFIX_VEX_382F,	1023 PREFIX_VEX_0F382D,

926 PREFIX_VEX_3830,	1024 PREFIX_VEX_0F382E,

927 PREFIX_VEX_3831,	1025 PREFIX_VEX_0F382F,

928 PREFIX_VEX_3832,	1026 PREFIX_VEX_0F3830,

929 PREFIX_VEX_3833,	1027 PREFIX_VEX_0F3831,

930 PREFIX_VEX_3834,	1028 PREFIX_VEX_0F3832,

931 PREFIX_VEX_3835,	1029 PREFIX_VEX_0F3833,

932 PREFIX_VEX_3837,	1030 PREFIX_VEX_0F3834,

933 PREFIX_VEX_3838,	1031 PREFIX_VEX_0F3835,

934 PREFIX_VEX_3839,	1032 PREFIX_VEX_0F3836,

935 PREFIX_VEX_383A,	1033 PREFIX_VEX_0F3837,

936 PREFIX_VEX_383B,	1034 PREFIX_VEX_0F3838,

937 PREFIX_VEX_383C,	1035 PREFIX_VEX_0F3839,

938 PREFIX_VEX_383D,	1036 PREFIX_VEX_0F383A,

939 PREFIX_VEX_383E,	1037 PREFIX_VEX_0F383B,

940 PREFIX_VEX_383F,	1038 PREFIX_VEX_0F383C,

941 PREFIX_VEX_3840,	1039 PREFIX_VEX_0F383D,

942 PREFIX_VEX_3841,	1040 PREFIX_VEX_0F383E,

943 PREFIX_VEX_3896,	1041 PREFIX_VEX_0F383F,

944 PREFIX_VEX_3897,	1042 PREFIX_VEX_0F3840,

945 PREFIX_VEX_3898,	1043 PREFIX_VEX_0F3841,

946 PREFIX_VEX_3899,	1044 PREFIX_VEX_0F3845,

947 PREFIX_VEX_389A,	1045 PREFIX_VEX_0F3846,

948 PREFIX_VEX_389B,	1046 PREFIX_VEX_0F3847,

949 PREFIX_VEX_389C,	1047 PREFIX_VEX_0F3858,

950 PREFIX_VEX_389D,	1048 PREFIX_VEX_0F3859,

951 PREFIX_VEX_389E,	1049 PREFIX_VEX_0F385A,

952 PREFIX_VEX_389F,	1050 PREFIX_VEX_0F3878,

953 PREFIX_VEX_38A6,	1051 PREFIX_VEX_0F3879,

954 PREFIX_VEX_38A7,	1052 PREFIX_VEX_0F388C,

955 PREFIX_VEX_38A8,	1053 PREFIX_VEX_0F388E,

956 PREFIX_VEX_38A9,	1054 PREFIX_VEX_0F3890,

957 PREFIX_VEX_38AA,	1055 PREFIX_VEX_0F3891,

958 PREFIX_VEX_38AB,	1056 PREFIX_VEX_0F3892,

959 PREFIX_VEX_38AC,	1057 PREFIX_VEX_0F3893,

960 PREFIX_VEX_38AD,	1058 PREFIX_VEX_0F3896,

961 PREFIX_VEX_38AE,	1059 PREFIX_VEX_0F3897,

962 PREFIX_VEX_38AF,	1060 PREFIX_VEX_0F3898,

963 PREFIX_VEX_38B6,	1061 PREFIX_VEX_0F3899,

964 PREFIX_VEX_38B7,	1062 PREFIX_VEX_0F389A,

965 PREFIX_VEX_38B8,	1063 PREFIX_VEX_0F389B,

966 PREFIX_VEX_38B9,	1064 PREFIX_VEX_0F389C,

967 PREFIX_VEX_38BA,	1065 PREFIX_VEX_0F389D,

968 PREFIX_VEX_38BB,	1066 PREFIX_VEX_0F389E,

969 PREFIX_VEX_38BC,	1067 PREFIX_VEX_0F389F,

970 PREFIX_VEX_38BD,	1068 PREFIX_VEX_0F38A6,

971 PREFIX_VEX_38BE,	1069 PREFIX_VEX_0F38A7,

972 PREFIX_VEX_38BF,	1070 PREFIX_VEX_0F38A8,

973 PREFIX_VEX_38DB,	1071 PREFIX_VEX_0F38A9,

974 PREFIX_VEX_38DC,	1072 PREFIX_VEX_0F38AA,

975 PREFIX_VEX_38DD,	1073 PREFIX_VEX_0F38AB,

976 PREFIX_VEX_38DE,	1074 PREFIX_VEX_0F38AC,

977 PREFIX_VEX_38DF,	1075 PREFIX_VEX_0F38AD,

978 PREFIX_VEX_3A04,	1076 PREFIX_VEX_0F38AE,

979 PREFIX_VEX_3A05,	1077 PREFIX_VEX_0F38AF,

980 PREFIX_VEX_3A06,	1078 PREFIX_VEX_0F38B6,

981 PREFIX_VEX_3A08,	1079 PREFIX_VEX_0F38B7,

982 PREFIX_VEX_3A09,	1080 PREFIX_VEX_0F38B8,

983 PREFIX_VEX_3A0A,	1081 PREFIX_VEX_0F38B9,

984 PREFIX_VEX_3A0B,	1082 PREFIX_VEX_0F38BA,

985 PREFIX_VEX_3A0C,	1083 PREFIX_VEX_0F38BB,

986 PREFIX_VEX_3A0D,	1084 PREFIX_VEX_0F38BC,

987 PREFIX_VEX_3A0E,	1085 PREFIX_VEX_0F38BD,

988 PREFIX_VEX_3A0F,	1086 PREFIX_VEX_0F38BE,

989 PREFIX_VEX_3A14,	1087 PREFIX_VEX_0F38BF,

990 PREFIX_VEX_3A15,	1088 PREFIX_VEX_0F38DB,

991 PREFIX_VEX_3A16,	1089 PREFIX_VEX_0F38DC,

992 PREFIX_VEX_3A17,	1090 PREFIX_VEX_0F38DD,

993 PREFIX_VEX_3A18,	1091 PREFIX_VEX_0F38DE,

994 PREFIX_VEX_3A19,	1092 PREFIX_VEX_0F38DF,

995 PREFIX_VEX_3A20,	1093 PREFIX_VEX_0F38F2,

996 PREFIX_VEX_3A21,	1094 PREFIX_VEX_0F38F3_REG_1,

997 PREFIX_VEX_3A22,	1095 PREFIX_VEX_0F38F3_REG_2,

998 PREFIX_VEX_3A40,	1096 PREFIX_VEX_0F38F3_REG_3,

999 PREFIX_VEX_3A41,	1097 PREFIX_VEX_0F38F5,

1000 PREFIX_VEX_3A42,	1098 PREFIX_VEX_0F38F6,

1001 PREFIX_VEX_3A44,	1099 PREFIX_VEX_0F38F7,

1002 PREFIX_VEX_3A4A,	1100 PREFIX_VEX_0F3A00,

1003 PREFIX_VEX_3A4B,	1101 PREFIX_VEX_0F3A01,

1004 PREFIX_VEX_3A4C,	1102 PREFIX_VEX_0F3A02,

1005 PREFIX_VEX_3A5C,	1103 PREFIX_VEX_0F3A04,

1006 PREFIX_VEX_3A5D,	1104 PREFIX_VEX_0F3A05,

1007 PREFIX_VEX_3A5E,	1105 PREFIX_VEX_0F3A06,

1008 PREFIX_VEX_3A5F,	1106 PREFIX_VEX_0F3A08,

1009 PREFIX_VEX_3A60,	1107 PREFIX_VEX_0F3A09,

1010 PREFIX_VEX_3A61,	1108 PREFIX_VEX_0F3A0A,

1011 PREFIX_VEX_3A62,	1109 PREFIX_VEX_0F3A0B,

1012 PREFIX_VEX_3A63,	1110 PREFIX_VEX_0F3A0C,

1013 PREFIX_VEX_3A68,	1111 PREFIX_VEX_0F3A0D,

1014 PREFIX_VEX_3A69,	1112 PREFIX_VEX_0F3A0E,

1015 PREFIX_VEX_3A6A,	1113 PREFIX_VEX_0F3A0F,

1016 PREFIX_VEX_3A6B,	1114 PREFIX_VEX_0F3A14,

1017 PREFIX_VEX_3A6C,	1115 PREFIX_VEX_0F3A15,

1018 PREFIX_VEX_3A6D,	1116 PREFIX_VEX_0F3A16,

1019 PREFIX_VEX_3A6E,	1117 PREFIX_VEX_0F3A17,

1020 PREFIX_VEX_3A6F,	1118 PREFIX_VEX_0F3A18,

1021 PREFIX_VEX_3A78,	1119 PREFIX_VEX_0F3A19,

1022 PREFIX_VEX_3A79,	1120 PREFIX_VEX_0F3A1D,

1023 PREFIX_VEX_3A7A,	1121 PREFIX_VEX_0F3A20,

1024 PREFIX_VEX_3A7B,	1122 PREFIX_VEX_0F3A21,

1025 PREFIX_VEX_3A7C,	1123 PREFIX_VEX_0F3A22,

1026 PREFIX_VEX_3A7D,	1124 PREFIX_VEX_0F3A38,

1027 PREFIX_VEX_3A7E,	1125 PREFIX_VEX_0F3A39,

1028 PREFIX_VEX_3A7F,	1126 PREFIX_VEX_0F3A40,

1029 PREFIX_VEX_3ADF	1127 PREFIX_VEX_0F3A41,

	1128 PREFIX_VEX_0F3A42,

	1129 PREFIX_VEX_0F3A44,

	1130 PREFIX_VEX_0F3A46,

	1131 PREFIX_VEX_0F3A48,

	1132 PREFIX_VEX_0F3A49,

	1133 PREFIX_VEX_0F3A4A,

	1134 PREFIX_VEX_0F3A4B,

	1135 PREFIX_VEX_0F3A4C,

	1136 PREFIX_VEX_0F3A5C,

	1137 PREFIX_VEX_0F3A5D,

	1138 PREFIX_VEX_0F3A5E,

	1139 PREFIX_VEX_0F3A5F,

	1140 PREFIX_VEX_0F3A60,

	1141 PREFIX_VEX_0F3A61,

	1142 PREFIX_VEX_0F3A62,

	1143 PREFIX_VEX_0F3A63,

	1144 PREFIX_VEX_0F3A68,

	1145 PREFIX_VEX_0F3A69,

	1146 PREFIX_VEX_0F3A6A,

	1147 PREFIX_VEX_0F3A6B,

	1148 PREFIX_VEX_0F3A6C,

	1149 PREFIX_VEX_0F3A6D,

	1150 PREFIX_VEX_0F3A6E,

	1151 PREFIX_VEX_0F3A6F,

	1152 PREFIX_VEX_0F3A78,

	1153 PREFIX_VEX_0F3A79,

	1154 PREFIX_VEX_0F3A7A,

	1155 PREFIX_VEX_0F3A7B,

	1156 PREFIX_VEX_0F3A7C,

	1157 PREFIX_VEX_0F3A7D,

	1158 PREFIX_VEX_0F3A7E,

	1159 PREFIX_VEX_0F3A7F,

	1160 PREFIX_VEX_0F3ADF,

	1161 PREFIX_VEX_0F3AF0

1030 };	1162 };

1031	1163

1032 enum	1164 enum

1033 {	1165 {

1034 X86_64_06 = 0,	1166 X86_64_06 = 0,

1035 X86_64_07,	1167 X86_64_07,

1036 X86_64_0D,	1168 X86_64_0D,

1037 X86_64_16,	1169 X86_64_16,

1038 X86_64_17,	1170 X86_64_17,

1039 X86_64_1E,	1171 X86_64_1E,

(...skipping 23 matching lines...) Expand all Loading...
1063	1195

1064 enum	1196 enum

1065 {	1197 {

1066 THREE_BYTE_0F38 = 0,	1198 THREE_BYTE_0F38 = 0,

1067 THREE_BYTE_0F3A,	1199 THREE_BYTE_0F3A,

1068 THREE_BYTE_0F7A	1200 THREE_BYTE_0F7A

1069 };	1201 };

1070	1202

1071 enum	1203 enum

1072 {	1204 {

	1205 XOP_08 = 0,

	1206 XOP_09,

	1207 XOP_0A

	1208 };

	1209

	1210 enum

	1211 {

1073 VEX_0F = 0,	1212 VEX_0F = 0,

1074 VEX_0F38,	1213 VEX_0F38,

1075 VEX_0F3A	1214 VEX_0F3A

1076 };	1215 };

1077	1216

1078 enum	1217 enum

1079 {	1218 {

1080 VEX_LEN_10_P_1 = 0,	1219 VEX_LEN_0F10_P_1 = 0,

1081 VEX_LEN_10_P_3,	1220 VEX_LEN_0F10_P_3,

1082 VEX_LEN_11_P_1,	1221 VEX_LEN_0F11_P_1,

1083 VEX_LEN_11_P_3,	1222 VEX_LEN_0F11_P_3,

1084 VEX_LEN_12_P_0_M_0,	1223 VEX_LEN_0F12_P_0_M_0,

1085 VEX_LEN_12_P_0_M_1,	1224 VEX_LEN_0F12_P_0_M_1,

1086 VEX_LEN_12_P_2,	1225 VEX_LEN_0F12_P_2,

1087 VEX_LEN_13_M_0,	1226 VEX_LEN_0F13_M_0,

1088 VEX_LEN_16_P_0_M_0,	1227 VEX_LEN_0F16_P_0_M_0,

1089 VEX_LEN_16_P_0_M_1,	1228 VEX_LEN_0F16_P_0_M_1,

1090 VEX_LEN_16_P_2,	1229 VEX_LEN_0F16_P_2,

1091 VEX_LEN_17_M_0,	1230 VEX_LEN_0F17_M_0,

1092 VEX_LEN_2A_P_1,	1231 VEX_LEN_0F2A_P_1,

1093 VEX_LEN_2A_P_3,	1232 VEX_LEN_0F2A_P_3,

1094 VEX_LEN_2C_P_1,	1233 VEX_LEN_0F2C_P_1,

1095 VEX_LEN_2C_P_3,	1234 VEX_LEN_0F2C_P_3,

1096 VEX_LEN_2D_P_1,	1235 VEX_LEN_0F2D_P_1,

1097 VEX_LEN_2D_P_3,	1236 VEX_LEN_0F2D_P_3,

1098 VEX_LEN_2E_P_0,	1237 VEX_LEN_0F2E_P_0,

1099 VEX_LEN_2E_P_2,	1238 VEX_LEN_0F2E_P_2,

1100 VEX_LEN_2F_P_0,	1239 VEX_LEN_0F2F_P_0,

1101 VEX_LEN_2F_P_2,	1240 VEX_LEN_0F2F_P_2,

1102 VEX_LEN_51_P_1,	1241 VEX_LEN_0F51_P_1,

1103 VEX_LEN_51_P_3,	1242 VEX_LEN_0F51_P_3,

1104 VEX_LEN_52_P_1,	1243 VEX_LEN_0F52_P_1,

1105 VEX_LEN_53_P_1,	1244 VEX_LEN_0F53_P_1,

1106 VEX_LEN_58_P_1,	1245 VEX_LEN_0F58_P_1,

1107 VEX_LEN_58_P_3,	1246 VEX_LEN_0F58_P_3,

1108 VEX_LEN_59_P_1,	1247 VEX_LEN_0F59_P_1,

1109 VEX_LEN_59_P_3,	1248 VEX_LEN_0F59_P_3,

1110 VEX_LEN_5A_P_1,	1249 VEX_LEN_0F5A_P_1,

1111 VEX_LEN_5A_P_3,	1250 VEX_LEN_0F5A_P_3,

1112 VEX_LEN_5C_P_1,	1251 VEX_LEN_0F5C_P_1,

1113 VEX_LEN_5C_P_3,	1252 VEX_LEN_0F5C_P_3,

1114 VEX_LEN_5D_P_1,	1253 VEX_LEN_0F5D_P_1,

1115 VEX_LEN_5D_P_3,	1254 VEX_LEN_0F5D_P_3,

1116 VEX_LEN_5E_P_1,	1255 VEX_LEN_0F5E_P_1,

1117 VEX_LEN_5E_P_3,	1256 VEX_LEN_0F5E_P_3,

1118 VEX_LEN_5F_P_1,	1257 VEX_LEN_0F5F_P_1,

1119 VEX_LEN_5F_P_3,	1258 VEX_LEN_0F5F_P_3,

1120 VEX_LEN_60_P_2,	1259 VEX_LEN_0F6E_P_2,

1121 VEX_LEN_61_P_2,	1260 VEX_LEN_0F7E_P_1,

1122 VEX_LEN_62_P_2,	1261 VEX_LEN_0F7E_P_2,

1123 VEX_LEN_63_P_2,	1262 VEX_LEN_0FAE_R_2_M_0,

1124 VEX_LEN_64_P_2,	1263 VEX_LEN_0FAE_R_3_M_0,

1125 VEX_LEN_65_P_2,	1264 VEX_LEN_0FC2_P_1,

1126 VEX_LEN_66_P_2,	1265 VEX_LEN_0FC2_P_3,

1127 VEX_LEN_67_P_2,	1266 VEX_LEN_0FC4_P_2,

1128 VEX_LEN_68_P_2,	1267 VEX_LEN_0FC5_P_2,

1129 VEX_LEN_69_P_2,	1268 VEX_LEN_0FD6_P_2,

1130 VEX_LEN_6A_P_2,	1269 VEX_LEN_0FF7_P_2,

1131 VEX_LEN_6B_P_2,	1270 VEX_LEN_0F3816_P_2,

1132 VEX_LEN_6C_P_2,	1271 VEX_LEN_0F3819_P_2,

1133 VEX_LEN_6D_P_2,	1272 VEX_LEN_0F381A_P_2_M_0,

1134 VEX_LEN_6E_P_2,	1273 VEX_LEN_0F3836_P_2,

1135 VEX_LEN_70_P_1,	1274 VEX_LEN_0F3841_P_2,

1136 VEX_LEN_70_P_2,	1275 VEX_LEN_0F385A_P_2_M_0,

1137 VEX_LEN_70_P_3,	1276 VEX_LEN_0F38DB_P_2,

1138 VEX_LEN_71_R_2_P_2,	1277 VEX_LEN_0F38DC_P_2,

1139 VEX_LEN_71_R_4_P_2,	1278 VEX_LEN_0F38DD_P_2,

1140 VEX_LEN_71_R_6_P_2,	1279 VEX_LEN_0F38DE_P_2,

1141 VEX_LEN_72_R_2_P_2,	1280 VEX_LEN_0F38DF_P_2,

1142 VEX_LEN_72_R_4_P_2,	1281 VEX_LEN_0F38F2_P_0,

1143 VEX_LEN_72_R_6_P_2,	1282 VEX_LEN_0F38F3_R_1_P_0,

1144 VEX_LEN_73_R_2_P_2,	1283 VEX_LEN_0F38F3_R_2_P_0,

1145 VEX_LEN_73_R_3_P_2,	1284 VEX_LEN_0F38F3_R_3_P_0,

1146 VEX_LEN_73_R_6_P_2,	1285 VEX_LEN_0F38F5_P_0,

1147 VEX_LEN_73_R_7_P_2,	1286 VEX_LEN_0F38F5_P_1,

1148 VEX_LEN_74_P_2,	1287 VEX_LEN_0F38F5_P_3,

1149 VEX_LEN_75_P_2,	1288 VEX_LEN_0F38F6_P_3,

1150 VEX_LEN_76_P_2,	1289 VEX_LEN_0F38F7_P_0,

1151 VEX_LEN_7E_P_1,	1290 VEX_LEN_0F38F7_P_1,

1152 VEX_LEN_7E_P_2,	1291 VEX_LEN_0F38F7_P_2,

1153 VEX_LEN_AE_R_2_M_0,	1292 VEX_LEN_0F38F7_P_3,

1154 VEX_LEN_AE_R_3_M_0,	1293 VEX_LEN_0F3A00_P_2,

1155 VEX_LEN_C2_P_1,	1294 VEX_LEN_0F3A01_P_2,

1156 VEX_LEN_C2_P_3,	1295 VEX_LEN_0F3A06_P_2,

1157 VEX_LEN_C4_P_2,	1296 VEX_LEN_0F3A0A_P_2,

1158 VEX_LEN_C5_P_2,	1297 VEX_LEN_0F3A0B_P_2,

1159 VEX_LEN_D1_P_2,	1298 VEX_LEN_0F3A14_P_2,

1160 VEX_LEN_D2_P_2,	1299 VEX_LEN_0F3A15_P_2,

1161 VEX_LEN_D3_P_2,	1300 VEX_LEN_0F3A16_P_2,

1162 VEX_LEN_D4_P_2,	1301 VEX_LEN_0F3A17_P_2,

1163 VEX_LEN_D5_P_2,	1302 VEX_LEN_0F3A18_P_2,

1164 VEX_LEN_D6_P_2,	1303 VEX_LEN_0F3A19_P_2,

1165 VEX_LEN_D7_P_2_M_1,	1304 VEX_LEN_0F3A20_P_2,

1166 VEX_LEN_D8_P_2,	1305 VEX_LEN_0F3A21_P_2,

1167 VEX_LEN_D9_P_2,	1306 VEX_LEN_0F3A22_P_2,

1168 VEX_LEN_DA_P_2,	1307 VEX_LEN_0F3A38_P_2,

1169 VEX_LEN_DB_P_2,	1308 VEX_LEN_0F3A39_P_2,

1170 VEX_LEN_DC_P_2,	1309 VEX_LEN_0F3A41_P_2,

1171 VEX_LEN_DD_P_2,	1310 VEX_LEN_0F3A44_P_2,

1172 VEX_LEN_DE_P_2,	1311 VEX_LEN_0F3A46_P_2,

1173 VEX_LEN_DF_P_2,	1312 VEX_LEN_0F3A60_P_2,

1174 VEX_LEN_E0_P_2,	1313 VEX_LEN_0F3A61_P_2,

1175 VEX_LEN_E1_P_2,	1314 VEX_LEN_0F3A62_P_2,

1176 VEX_LEN_E2_P_2,	1315 VEX_LEN_0F3A63_P_2,

1177 VEX_LEN_E3_P_2,	1316 VEX_LEN_0F3A6A_P_2,

1178 VEX_LEN_E4_P_2,	1317 VEX_LEN_0F3A6B_P_2,

1179 VEX_LEN_E5_P_2,	1318 VEX_LEN_0F3A6E_P_2,

1180 VEX_LEN_E8_P_2,	1319 VEX_LEN_0F3A6F_P_2,

1181 VEX_LEN_E9_P_2,	1320 VEX_LEN_0F3A7A_P_2,

1182 VEX_LEN_EA_P_2,	1321 VEX_LEN_0F3A7B_P_2,

1183 VEX_LEN_EB_P_2,	1322 VEX_LEN_0F3A7E_P_2,

1184 VEX_LEN_EC_P_2,	1323 VEX_LEN_0F3A7F_P_2,

1185 VEX_LEN_ED_P_2,	1324 VEX_LEN_0F3ADF_P_2,

1186 VEX_LEN_EE_P_2,	1325 VEX_LEN_0F3AF0_P_3,

1187 VEX_LEN_EF_P_2,	1326 VEX_LEN_0FXOP_08_CC,

1188 VEX_LEN_F1_P_2,	1327 VEX_LEN_0FXOP_08_CD,

1189 VEX_LEN_F2_P_2,	1328 VEX_LEN_0FXOP_08_CE,

1190 VEX_LEN_F3_P_2,	1329 VEX_LEN_0FXOP_08_CF,

1191 VEX_LEN_F4_P_2,	1330 VEX_LEN_0FXOP_08_EC,

1192 VEX_LEN_F5_P_2,	1331 VEX_LEN_0FXOP_08_ED,

1193 VEX_LEN_F6_P_2,	1332 VEX_LEN_0FXOP_08_EE,

1194 VEX_LEN_F7_P_2,	1333 VEX_LEN_0FXOP_08_EF,

1195 VEX_LEN_F8_P_2,	1334 VEX_LEN_0FXOP_09_80,

1196 VEX_LEN_F9_P_2,	1335 VEX_LEN_0FXOP_09_81

1197 VEX_LEN_FA_P_2,	1336 };

1198 VEX_LEN_FB_P_2,	1337

1199 VEX_LEN_FC_P_2,	1338 enum

1200 VEX_LEN_FD_P_2,	1339 {

1201 VEX_LEN_FE_P_2,	1340 VEX_W_0F10_P_0 = 0,

1202 VEX_LEN_3800_P_2,	1341 VEX_W_0F10_P_1,

1203 VEX_LEN_3801_P_2,	1342 VEX_W_0F10_P_2,

1204 VEX_LEN_3802_P_2,	1343 VEX_W_0F10_P_3,

1205 VEX_LEN_3803_P_2,	1344 VEX_W_0F11_P_0,

1206 VEX_LEN_3804_P_2,	1345 VEX_W_0F11_P_1,

1207 VEX_LEN_3805_P_2,	1346 VEX_W_0F11_P_2,

1208 VEX_LEN_3806_P_2,	1347 VEX_W_0F11_P_3,

1209 VEX_LEN_3807_P_2,	1348 VEX_W_0F12_P_0_M_0,

1210 VEX_LEN_3808_P_2,	1349 VEX_W_0F12_P_0_M_1,

1211 VEX_LEN_3809_P_2,	1350 VEX_W_0F12_P_1,

1212 VEX_LEN_380A_P_2,	1351 VEX_W_0F12_P_2,

1213 VEX_LEN_380B_P_2,	1352 VEX_W_0F12_P_3,

1214 VEX_LEN_3819_P_2_M_0,	1353 VEX_W_0F13_M_0,

1215 VEX_LEN_381A_P_2_M_0,	1354 VEX_W_0F14,

1216 VEX_LEN_381C_P_2,	1355 VEX_W_0F15,

1217 VEX_LEN_381D_P_2,	1356 VEX_W_0F16_P_0_M_0,

1218 VEX_LEN_381E_P_2,	1357 VEX_W_0F16_P_0_M_1,

1219 VEX_LEN_3820_P_2,	1358 VEX_W_0F16_P_1,

1220 VEX_LEN_3821_P_2,	1359 VEX_W_0F16_P_2,

1221 VEX_LEN_3822_P_2,	1360 VEX_W_0F17_M_0,

1222 VEX_LEN_3823_P_2,	1361 VEX_W_0F28,

1223 VEX_LEN_3824_P_2,	1362 VEX_W_0F29,

1224 VEX_LEN_3825_P_2,	1363 VEX_W_0F2B_M_0,

1225 VEX_LEN_3828_P_2,	1364 VEX_W_0F2E_P_0,

1226 VEX_LEN_3829_P_2,	1365 VEX_W_0F2E_P_2,

1227 VEX_LEN_382A_P_2_M_0,	1366 VEX_W_0F2F_P_0,

1228 VEX_LEN_382B_P_2,	1367 VEX_W_0F2F_P_2,

1229 VEX_LEN_3830_P_2,	1368 VEX_W_0F50_M_0,

1230 VEX_LEN_3831_P_2,	1369 VEX_W_0F51_P_0,

1231 VEX_LEN_3832_P_2,	1370 VEX_W_0F51_P_1,

1232 VEX_LEN_3833_P_2,	1371 VEX_W_0F51_P_2,

1233 VEX_LEN_3834_P_2,	1372 VEX_W_0F51_P_3,

1234 VEX_LEN_3835_P_2,	1373 VEX_W_0F52_P_0,

1235 VEX_LEN_3837_P_2,	1374 VEX_W_0F52_P_1,

1236 VEX_LEN_3838_P_2,	1375 VEX_W_0F53_P_0,

1237 VEX_LEN_3839_P_2,	1376 VEX_W_0F53_P_1,

1238 VEX_LEN_383A_P_2,	1377 VEX_W_0F58_P_0,

1239 VEX_LEN_383B_P_2,	1378 VEX_W_0F58_P_1,

1240 VEX_LEN_383C_P_2,	1379 VEX_W_0F58_P_2,

1241 VEX_LEN_383D_P_2,	1380 VEX_W_0F58_P_3,

1242 VEX_LEN_383E_P_2,	1381 VEX_W_0F59_P_0,

1243 VEX_LEN_383F_P_2,	1382 VEX_W_0F59_P_1,

1244 VEX_LEN_3840_P_2,	1383 VEX_W_0F59_P_2,

1245 VEX_LEN_3841_P_2,	1384 VEX_W_0F59_P_3,

1246 VEX_LEN_38DB_P_2,	1385 VEX_W_0F5A_P_0,

1247 VEX_LEN_38DC_P_2,	1386 VEX_W_0F5A_P_1,

1248 VEX_LEN_38DD_P_2,	1387 VEX_W_0F5A_P_3,

1249 VEX_LEN_38DE_P_2,	1388 VEX_W_0F5B_P_0,

1250 VEX_LEN_38DF_P_2,	1389 VEX_W_0F5B_P_1,

1251 VEX_LEN_3A06_P_2,	1390 VEX_W_0F5B_P_2,

1252 VEX_LEN_3A0A_P_2,	1391 VEX_W_0F5C_P_0,

1253 VEX_LEN_3A0B_P_2,	1392 VEX_W_0F5C_P_1,

1254 VEX_LEN_3A0E_P_2,	1393 VEX_W_0F5C_P_2,

1255 VEX_LEN_3A0F_P_2,	1394 VEX_W_0F5C_P_3,

1256 VEX_LEN_3A14_P_2,	1395 VEX_W_0F5D_P_0,

1257 VEX_LEN_3A15_P_2,	1396 VEX_W_0F5D_P_1,

1258 VEX_LEN_3A16_P_2,	1397 VEX_W_0F5D_P_2,

1259 VEX_LEN_3A17_P_2,	1398 VEX_W_0F5D_P_3,

1260 VEX_LEN_3A18_P_2,	1399 VEX_W_0F5E_P_0,

1261 VEX_LEN_3A19_P_2,	1400 VEX_W_0F5E_P_1,

1262 VEX_LEN_3A20_P_2,	1401 VEX_W_0F5E_P_2,

1263 VEX_LEN_3A21_P_2,	1402 VEX_W_0F5E_P_3,

1264 VEX_LEN_3A22_P_2,	1403 VEX_W_0F5F_P_0,

1265 VEX_LEN_3A41_P_2,	1404 VEX_W_0F5F_P_1,

1266 VEX_LEN_3A42_P_2,	1405 VEX_W_0F5F_P_2,

1267 VEX_LEN_3A44_P_2,	1406 VEX_W_0F5F_P_3,

1268 VEX_LEN_3A4C_P_2,	1407 VEX_W_0F60_P_2,

1269 VEX_LEN_3A60_P_2,	1408 VEX_W_0F61_P_2,

1270 VEX_LEN_3A61_P_2,	1409 VEX_W_0F62_P_2,

1271 VEX_LEN_3A62_P_2,	1410 VEX_W_0F63_P_2,

1272 VEX_LEN_3A63_P_2,	1411 VEX_W_0F64_P_2,

1273 VEX_LEN_3A6A_P_2,	1412 VEX_W_0F65_P_2,

1274 VEX_LEN_3A6B_P_2,	1413 VEX_W_0F66_P_2,

1275 VEX_LEN_3A6E_P_2,	1414 VEX_W_0F67_P_2,

1276 VEX_LEN_3A6F_P_2,	1415 VEX_W_0F68_P_2,

1277 VEX_LEN_3A7A_P_2,	1416 VEX_W_0F69_P_2,

1278 VEX_LEN_3A7B_P_2,	1417 VEX_W_0F6A_P_2,

1279 VEX_LEN_3A7E_P_2,	1418 VEX_W_0F6B_P_2,

1280 VEX_LEN_3A7F_P_2,	1419 VEX_W_0F6C_P_2,

1281 VEX_LEN_3ADF_P_2	1420 VEX_W_0F6D_P_2,

	1421 VEX_W_0F6F_P_1,

	1422 VEX_W_0F6F_P_2,

	1423 VEX_W_0F70_P_1,

	1424 VEX_W_0F70_P_2,

	1425 VEX_W_0F70_P_3,

	1426 VEX_W_0F71_R_2_P_2,

	1427 VEX_W_0F71_R_4_P_2,

	1428 VEX_W_0F71_R_6_P_2,

	1429 VEX_W_0F72_R_2_P_2,

	1430 VEX_W_0F72_R_4_P_2,

	1431 VEX_W_0F72_R_6_P_2,

	1432 VEX_W_0F73_R_2_P_2,

	1433 VEX_W_0F73_R_3_P_2,

	1434 VEX_W_0F73_R_6_P_2,

	1435 VEX_W_0F73_R_7_P_2,

	1436 VEX_W_0F74_P_2,

	1437 VEX_W_0F75_P_2,

	1438 VEX_W_0F76_P_2,

	1439 VEX_W_0F77_P_0,

	1440 VEX_W_0F7C_P_2,

	1441 VEX_W_0F7C_P_3,

	1442 VEX_W_0F7D_P_2,

	1443 VEX_W_0F7D_P_3,

	1444 VEX_W_0F7E_P_1,

	1445 VEX_W_0F7F_P_1,

	1446 VEX_W_0F7F_P_2,

	1447 VEX_W_0FAE_R_2_M_0,

	1448 VEX_W_0FAE_R_3_M_0,

	1449 VEX_W_0FC2_P_0,

	1450 VEX_W_0FC2_P_1,

	1451 VEX_W_0FC2_P_2,

	1452 VEX_W_0FC2_P_3,

	1453 VEX_W_0FC4_P_2,

	1454 VEX_W_0FC5_P_2,

	1455 VEX_W_0FD0_P_2,

	1456 VEX_W_0FD0_P_3,

	1457 VEX_W_0FD1_P_2,

	1458 VEX_W_0FD2_P_2,

	1459 VEX_W_0FD3_P_2,

	1460 VEX_W_0FD4_P_2,

	1461 VEX_W_0FD5_P_2,

	1462 VEX_W_0FD6_P_2,

	1463 VEX_W_0FD7_P_2_M_1,

	1464 VEX_W_0FD8_P_2,

	1465 VEX_W_0FD9_P_2,

	1466 VEX_W_0FDA_P_2,

	1467 VEX_W_0FDB_P_2,

	1468 VEX_W_0FDC_P_2,

	1469 VEX_W_0FDD_P_2,

	1470 VEX_W_0FDE_P_2,

	1471 VEX_W_0FDF_P_2,

	1472 VEX_W_0FE0_P_2,

	1473 VEX_W_0FE1_P_2,

	1474 VEX_W_0FE2_P_2,

	1475 VEX_W_0FE3_P_2,

	1476 VEX_W_0FE4_P_2,

	1477 VEX_W_0FE5_P_2,

	1478 VEX_W_0FE6_P_1,

	1479 VEX_W_0FE6_P_2,

	1480 VEX_W_0FE6_P_3,

	1481 VEX_W_0FE7_P_2_M_0,

	1482 VEX_W_0FE8_P_2,

	1483 VEX_W_0FE9_P_2,

	1484 VEX_W_0FEA_P_2,

	1485 VEX_W_0FEB_P_2,

	1486 VEX_W_0FEC_P_2,

	1487 VEX_W_0FED_P_2,

	1488 VEX_W_0FEE_P_2,

	1489 VEX_W_0FEF_P_2,

	1490 VEX_W_0FF0_P_3_M_0,

	1491 VEX_W_0FF1_P_2,

	1492 VEX_W_0FF2_P_2,

	1493 VEX_W_0FF3_P_2,

	1494 VEX_W_0FF4_P_2,

	1495 VEX_W_0FF5_P_2,

	1496 VEX_W_0FF6_P_2,

	1497 VEX_W_0FF7_P_2,

	1498 VEX_W_0FF8_P_2,

	1499 VEX_W_0FF9_P_2,

	1500 VEX_W_0FFA_P_2,

	1501 VEX_W_0FFB_P_2,

	1502 VEX_W_0FFC_P_2,

	1503 VEX_W_0FFD_P_2,

	1504 VEX_W_0FFE_P_2,

	1505 VEX_W_0F3800_P_2,

	1506 VEX_W_0F3801_P_2,

	1507 VEX_W_0F3802_P_2,

	1508 VEX_W_0F3803_P_2,

	1509 VEX_W_0F3804_P_2,

	1510 VEX_W_0F3805_P_2,

	1511 VEX_W_0F3806_P_2,

	1512 VEX_W_0F3807_P_2,

	1513 VEX_W_0F3808_P_2,

	1514 VEX_W_0F3809_P_2,

	1515 VEX_W_0F380A_P_2,

	1516 VEX_W_0F380B_P_2,

	1517 VEX_W_0F380C_P_2,

	1518 VEX_W_0F380D_P_2,

	1519 VEX_W_0F380E_P_2,

	1520 VEX_W_0F380F_P_2,

	1521 VEX_W_0F3816_P_2,

	1522 VEX_W_0F3817_P_2,

	1523 VEX_W_0F3818_P_2,

	1524 VEX_W_0F3819_P_2,

	1525 VEX_W_0F381A_P_2_M_0,

	1526 VEX_W_0F381C_P_2,

	1527 VEX_W_0F381D_P_2,

	1528 VEX_W_0F381E_P_2,

	1529 VEX_W_0F3820_P_2,

	1530 VEX_W_0F3821_P_2,

	1531 VEX_W_0F3822_P_2,

	1532 VEX_W_0F3823_P_2,

	1533 VEX_W_0F3824_P_2,

	1534 VEX_W_0F3825_P_2,

	1535 VEX_W_0F3828_P_2,

	1536 VEX_W_0F3829_P_2,

	1537 VEX_W_0F382A_P_2_M_0,

	1538 VEX_W_0F382B_P_2,

	1539 VEX_W_0F382C_P_2_M_0,

	1540 VEX_W_0F382D_P_2_M_0,

	1541 VEX_W_0F382E_P_2_M_0,

	1542 VEX_W_0F382F_P_2_M_0,

	1543 VEX_W_0F3830_P_2,

	1544 VEX_W_0F3831_P_2,

	1545 VEX_W_0F3832_P_2,

	1546 VEX_W_0F3833_P_2,

	1547 VEX_W_0F3834_P_2,

	1548 VEX_W_0F3835_P_2,

	1549 VEX_W_0F3836_P_2,

	1550 VEX_W_0F3837_P_2,

	1551 VEX_W_0F3838_P_2,

	1552 VEX_W_0F3839_P_2,

	1553 VEX_W_0F383A_P_2,

	1554 VEX_W_0F383B_P_2,

	1555 VEX_W_0F383C_P_2,

	1556 VEX_W_0F383D_P_2,

	1557 VEX_W_0F383E_P_2,

	1558 VEX_W_0F383F_P_2,

	1559 VEX_W_0F3840_P_2,

	1560 VEX_W_0F3841_P_2,

	1561 VEX_W_0F3846_P_2,

	1562 VEX_W_0F3858_P_2,

	1563 VEX_W_0F3859_P_2,

	1564 VEX_W_0F385A_P_2_M_0,

	1565 VEX_W_0F3878_P_2,

	1566 VEX_W_0F3879_P_2,

	1567 VEX_W_0F38DB_P_2,

	1568 VEX_W_0F38DC_P_2,

	1569 VEX_W_0F38DD_P_2,

	1570 VEX_W_0F38DE_P_2,

	1571 VEX_W_0F38DF_P_2,

	1572 VEX_W_0F3A00_P_2,

	1573 VEX_W_0F3A01_P_2,

	1574 VEX_W_0F3A02_P_2,

	1575 VEX_W_0F3A04_P_2,

	1576 VEX_W_0F3A05_P_2,

	1577 VEX_W_0F3A06_P_2,

	1578 VEX_W_0F3A08_P_2,

	1579 VEX_W_0F3A09_P_2,

	1580 VEX_W_0F3A0A_P_2,

	1581 VEX_W_0F3A0B_P_2,

	1582 VEX_W_0F3A0C_P_2,

	1583 VEX_W_0F3A0D_P_2,

	1584 VEX_W_0F3A0E_P_2,

	1585 VEX_W_0F3A0F_P_2,

	1586 VEX_W_0F3A14_P_2,

	1587 VEX_W_0F3A15_P_2,

	1588 VEX_W_0F3A18_P_2,

	1589 VEX_W_0F3A19_P_2,

	1590 VEX_W_0F3A20_P_2,

	1591 VEX_W_0F3A21_P_2,

	1592 VEX_W_0F3A38_P_2,

	1593 VEX_W_0F3A39_P_2,

	1594 VEX_W_0F3A40_P_2,

	1595 VEX_W_0F3A41_P_2,

	1596 VEX_W_0F3A42_P_2,

	1597 VEX_W_0F3A44_P_2,

	1598 VEX_W_0F3A46_P_2,

	1599 VEX_W_0F3A48_P_2,

	1600 VEX_W_0F3A49_P_2,

	1601 VEX_W_0F3A4A_P_2,

	1602 VEX_W_0F3A4B_P_2,

	1603 VEX_W_0F3A4C_P_2,

	1604 VEX_W_0F3A60_P_2,

	1605 VEX_W_0F3A61_P_2,

	1606 VEX_W_0F3A62_P_2,

	1607 VEX_W_0F3A63_P_2,

	1608 VEX_W_0F3ADF_P_2

1282 };	1609 };

1283	1610

1284 typedef void (*op_rtn) (int bytemode, int sizeflag);	1611 typedef void (*op_rtn) (int bytemode, int sizeflag);

1285	1612

1286 struct dis386 {	1613 struct dis386 {

1287 const char *name;	1614 const char *name;

1288 struct	1615 struct

1289 {	1616 {

1290 op_rtn rtn;	1617 op_rtn rtn;

1291 int bytemode;	1618 int bytemode;

(...skipping 32 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
1324 'X' => print 's', 'd' depending on data16 prefix (for XMM)	1651 'X' => print 's', 'd' depending on data16 prefix (for XMM)

1325 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and	1652 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and

1326 suffix_always is true.	1653 suffix_always is true.

1327 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise	1654 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise

1328 '!' => change condition from true to false or from false to true.	1655 '!' => change condition from true to false or from false to true.

1329 '%' => add 1 upper case letter to the macro.	1656 '%' => add 1 upper case letter to the macro.

1330	1657

1331 2 upper case letter macros:	1658 2 upper case letter macros:

1332 "XY" => print 'x' or 'y' if no register operands or suffix_always	1659 "XY" => print 'x' or 'y' if no register operands or suffix_always

1333 is true.	1660 is true.

1334 'XW' => print 's', 'd' depending on the VEX.W bit (for FMA)	1661 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)

1335 'LQ' => print 'l' ('d' in Intel mode) or 'q' for memory operand	1662 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand

1336 or suffix_always is true	1663 or suffix_always is true

	1664 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise

	1665 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise

	1666 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise

	1667 "LW" => print 'd', 'q' depending on the VEX.W bit

1337	1668

1338 Many of the above letters print nothing in Intel mode. See "putop"	1669 Many of the above letters print nothing in Intel mode. See "putop"

1339 for the details.	1670 for the details.

1340	1671

1341 Braces '{' and '}', and vertical bars '\|', indicate alternative	1672 Braces '{' and '}', and vertical bars '\|', indicate alternative

1342 mnemonic strings for AT&T and Intel. */	1673 mnemonic strings for AT&T and Intel. */

1343	1674

1344 static const struct dis386 dis386[] = {	1675 static const struct dis386 dis386[] = {

1345 /* 00 */	1676 /* 00 */

1346 { "addB",» » { Eb, Gb } },	1677 { "addB",» » { Ebh1, Gb } },

1347 { "addS",» » { Ev, Gv } },	1678 { "addS",» » { Evh1, Gv } },

1348 { "addB", { Gb, EbS } },	1679 { "addB", { Gb, EbS } },

1349 { "addS", { Gv, EvS } },	1680 { "addS", { Gv, EvS } },

1350 { "addB", { AL, Ib } },	1681 { "addB", { AL, Ib } },

1351 { "addS", { eAX, Iv } },	1682 { "addS", { eAX, Iv } },

1352 { X86_64_TABLE (X86_64_06) },	1683 { X86_64_TABLE (X86_64_06) },

1353 { X86_64_TABLE (X86_64_07) },	1684 { X86_64_TABLE (X86_64_07) },

1354 /* 08 */	1685 /* 08 */

1355 { "orB",» » { Eb, Gb } },	1686 { "orB",» » { Ebh1, Gb } },

1356 { "orS",» » { Ev, Gv } },	1687 { "orS",» » { Evh1, Gv } },

1357 { "orB", { Gb, EbS } },	1688 { "orB", { Gb, EbS } },

1358 { "orS", { Gv, EvS } },	1689 { "orS", { Gv, EvS } },

1359 { "orB", { AL, Ib } },	1690 { "orB", { AL, Ib } },

1360 { "orS", { eAX, Iv } },	1691 { "orS", { eAX, Iv } },

1361 { X86_64_TABLE (X86_64_0D) },	1692 { X86_64_TABLE (X86_64_0D) },

1362 { "(bad)",» » { XX } },» /* 0x0f extended opcode escape */	1693 { Bad_Opcode },» /* 0x0f extended opcode escape */

1363 /* 10 */	1694 /* 10 */

1364 { "adcB",» » { Eb, Gb } },	1695 { "adcB",» » { Ebh1, Gb } },

1365 { "adcS",» » { Ev, Gv } },	1696 { "adcS",» » { Evh1, Gv } },

1366 { "adcB", { Gb, EbS } },	1697 { "adcB", { Gb, EbS } },

1367 { "adcS", { Gv, EvS } },	1698 { "adcS", { Gv, EvS } },

1368 { "adcB", { AL, Ib } },	1699 { "adcB", { AL, Ib } },

1369 { "adcS", { eAX, Iv } },	1700 { "adcS", { eAX, Iv } },

1370 { X86_64_TABLE (X86_64_16) },	1701 { X86_64_TABLE (X86_64_16) },

1371 { X86_64_TABLE (X86_64_17) },	1702 { X86_64_TABLE (X86_64_17) },

1372 /* 18 */	1703 /* 18 */

1373 { "sbbB",» » { Eb, Gb } },	1704 { "sbbB",» » { Ebh1, Gb } },

1374 { "sbbS",» » { Ev, Gv } },	1705 { "sbbS",» » { Evh1, Gv } },

1375 { "sbbB", { Gb, EbS } },	1706 { "sbbB", { Gb, EbS } },

1376 { "sbbS", { Gv, EvS } },	1707 { "sbbS", { Gv, EvS } },

1377 { "sbbB", { AL, Ib } },	1708 { "sbbB", { AL, Ib } },

1378 { "sbbS", { eAX, Iv } },	1709 { "sbbS", { eAX, Iv } },

1379 { X86_64_TABLE (X86_64_1E) },	1710 { X86_64_TABLE (X86_64_1E) },

1380 { X86_64_TABLE (X86_64_1F) },	1711 { X86_64_TABLE (X86_64_1F) },

1381 /* 20 */	1712 /* 20 */

1382 { "andB",» » { Eb, Gb } },	1713 { "andB",» » { Ebh1, Gb } },

1383 { "andS",» » { Ev, Gv } },	1714 { "andS",» » { Evh1, Gv } },

1384 { "andB", { Gb, EbS } },	1715 { "andB", { Gb, EbS } },

1385 { "andS", { Gv, EvS } },	1716 { "andS", { Gv, EvS } },

1386 { "andB", { AL, Ib } },	1717 { "andB", { AL, Ib } },

1387 { "andS", { eAX, Iv } },	1718 { "andS", { eAX, Iv } },

1388 { "(bad)",» » { XX } },» /* SEG ES prefix */	1719 { Bad_Opcode },» /* SEG ES prefix */

1389 { X86_64_TABLE (X86_64_27) },	1720 { X86_64_TABLE (X86_64_27) },

1390 /* 28 */	1721 /* 28 */

1391 { "subB",» » { Eb, Gb } },	1722 { "subB",» » { Ebh1, Gb } },

1392 { "subS",» » { Ev, Gv } },	1723 { "subS",» » { Evh1, Gv } },

1393 { "subB", { Gb, EbS } },	1724 { "subB", { Gb, EbS } },

1394 { "subS", { Gv, EvS } },	1725 { "subS", { Gv, EvS } },

1395 { "subB", { AL, Ib } },	1726 { "subB", { AL, Ib } },

1396 { "subS", { eAX, Iv } },	1727 { "subS", { eAX, Iv } },

1397 { "(bad)",» » { XX } },» /* SEG CS prefix */	1728 { Bad_Opcode },» /* SEG CS prefix */

1398 { X86_64_TABLE (X86_64_2F) },	1729 { X86_64_TABLE (X86_64_2F) },

1399 /* 30 */	1730 /* 30 */

1400 { "xorB",» » { Eb, Gb } },	1731 { "xorB",» » { Ebh1, Gb } },

1401 { "xorS",» » { Ev, Gv } },	1732 { "xorS",» » { Evh1, Gv } },

1402 { "xorB", { Gb, EbS } },	1733 { "xorB", { Gb, EbS } },

1403 { "xorS", { Gv, EvS } },	1734 { "xorS", { Gv, EvS } },

1404 { "xorB", { AL, Ib } },	1735 { "xorB", { AL, Ib } },

1405 { "xorS", { eAX, Iv } },	1736 { "xorS", { eAX, Iv } },

1406 { "(bad)",» » { XX } },» /* SEG SS prefix */	1737 { Bad_Opcode },» /* SEG SS prefix */

1407 { X86_64_TABLE (X86_64_37) },	1738 { X86_64_TABLE (X86_64_37) },

1408 /* 38 */	1739 /* 38 */

1409 { "cmpB", { Eb, Gb } },	1740 { "cmpB", { Eb, Gb } },

1410 { "cmpS", { Ev, Gv } },	1741 { "cmpS", { Ev, Gv } },

1411 { "cmpB", { Gb, EbS } },	1742 { "cmpB", { Gb, EbS } },

1412 { "cmpS", { Gv, EvS } },	1743 { "cmpS", { Gv, EvS } },

1413 { "cmpB", { AL, Ib } },	1744 { "cmpB", { AL, Ib } },

1414 { "cmpS", { eAX, Iv } },	1745 { "cmpS", { eAX, Iv } },

1415 { "(bad)",» » { XX } },» /* SEG DS prefix */	1746 { Bad_Opcode },» /* SEG DS prefix */

1416 { X86_64_TABLE (X86_64_3F) },	1747 { X86_64_TABLE (X86_64_3F) },

1417 /* 40 */	1748 /* 40 */

1418 { "inc{S\|}", { RMeAX } },	1749 { "inc{S\|}", { RMeAX } },

1419 { "inc{S\|}", { RMeCX } },	1750 { "inc{S\|}", { RMeCX } },

1420 { "inc{S\|}", { RMeDX } },	1751 { "inc{S\|}", { RMeDX } },

1421 { "inc{S\|}", { RMeBX } },	1752 { "inc{S\|}", { RMeBX } },

1422 { "inc{S\|}", { RMeSP } },	1753 { "inc{S\|}", { RMeSP } },

1423 { "inc{S\|}", { RMeBP } },	1754 { "inc{S\|}", { RMeBP } },

1424 { "inc{S\|}", { RMeSI } },	1755 { "inc{S\|}", { RMeSI } },

1425 { "inc{S\|}", { RMeDI } },	1756 { "inc{S\|}", { RMeDI } },

(...skipping 22 matching lines...) Expand all Loading...
1448 { "popV", { RMrBX } },	1779 { "popV", { RMrBX } },

1449 { "popV", { RMrSP } },	1780 { "popV", { RMrSP } },

1450 { "popV", { RMrBP } },	1781 { "popV", { RMrBP } },

1451 { "popV", { RMrSI } },	1782 { "popV", { RMrSI } },

1452 { "popV", { RMrDI } },	1783 { "popV", { RMrDI } },

1453 /* 60 */	1784 /* 60 */

1454 { X86_64_TABLE (X86_64_60) },	1785 { X86_64_TABLE (X86_64_60) },

1455 { X86_64_TABLE (X86_64_61) },	1786 { X86_64_TABLE (X86_64_61) },

1456 { X86_64_TABLE (X86_64_62) },	1787 { X86_64_TABLE (X86_64_62) },

1457 { X86_64_TABLE (X86_64_63) },	1788 { X86_64_TABLE (X86_64_63) },

1458 { "(bad)",» » { XX } },» /* seg fs */	1789 { Bad_Opcode },» /* seg fs */

1459 { "(bad)",» » { XX } },» /* seg gs */	1790 { Bad_Opcode },» /* seg gs */

1460 { "(bad)",» » { XX } },» /* op size prefix */	1791 { Bad_Opcode },» /* op size prefix */

1461 { "(bad)",» » { XX } },» /* adr size prefix */	1792 { Bad_Opcode },» /* adr size prefix */

1462 /* 68 */	1793 /* 68 */

1463 { "pushT",» » { Iq } },	1794 { "pushT",» » { sIv } },

1464 { "imulS", { Gv, Ev, Iv } },	1795 { "imulS", { Gv, Ev, Iv } },

1465 { "pushT",» » { sIb } },	1796 { "pushT",» » { sIbT } },

1466 { "imulS", { Gv, Ev, sIb } },	1797 { "imulS", { Gv, Ev, sIb } },

1467 { "ins{b\|}", { Ybr, indirDX } },	1798 { "ins{b\|}", { Ybr, indirDX } },

1468 { X86_64_TABLE (X86_64_6D) },	1799 { X86_64_TABLE (X86_64_6D) },

1469 { "outs{b\|}", { indirDXr, Xb } },	1800 { "outs{b\|}", { indirDXr, Xb } },

1470 { X86_64_TABLE (X86_64_6F) },	1801 { X86_64_TABLE (X86_64_6F) },

1471 /* 70 */	1802 /* 70 */

1472 { "joH", { Jb, XX, cond_jump_flag } },	1803 { "joH", { Jb, XX, cond_jump_flag } },

1473 { "jnoH", { Jb, XX, cond_jump_flag } },	1804 { "jnoH", { Jb, XX, cond_jump_flag } },

1474 { "jbH", { Jb, XX, cond_jump_flag } },	1805 { "jbH", { Jb, XX, cond_jump_flag } },

1475 { "jaeH", { Jb, XX, cond_jump_flag } },	1806 { "jaeH", { Jb, XX, cond_jump_flag } },

1476 { "jeH", { Jb, XX, cond_jump_flag } },	1807 { "jeH", { Jb, XX, cond_jump_flag } },

1477 { "jneH", { Jb, XX, cond_jump_flag } },	1808 { "jneH", { Jb, XX, cond_jump_flag } },

1478 { "jbeH", { Jb, XX, cond_jump_flag } },	1809 { "jbeH", { Jb, XX, cond_jump_flag } },

1479 { "jaH", { Jb, XX, cond_jump_flag } },	1810 { "jaH", { Jb, XX, cond_jump_flag } },

1480 /* 78 */	1811 /* 78 */

1481 { "jsH", { Jb, XX, cond_jump_flag } },	1812 { "jsH", { Jb, XX, cond_jump_flag } },

1482 { "jnsH", { Jb, XX, cond_jump_flag } },	1813 { "jnsH", { Jb, XX, cond_jump_flag } },

1483 { "jpH", { Jb, XX, cond_jump_flag } },	1814 { "jpH", { Jb, XX, cond_jump_flag } },

1484 { "jnpH", { Jb, XX, cond_jump_flag } },	1815 { "jnpH", { Jb, XX, cond_jump_flag } },

1485 { "jlH", { Jb, XX, cond_jump_flag } },	1816 { "jlH", { Jb, XX, cond_jump_flag } },

1486 { "jgeH", { Jb, XX, cond_jump_flag } },	1817 { "jgeH", { Jb, XX, cond_jump_flag } },

1487 { "jleH", { Jb, XX, cond_jump_flag } },	1818 { "jleH", { Jb, XX, cond_jump_flag } },

1488 { "jgH", { Jb, XX, cond_jump_flag } },	1819 { "jgH", { Jb, XX, cond_jump_flag } },

1489 /* 80 */	1820 /* 80 */

1490 { REG_TABLE (REG_80) },	1821 { REG_TABLE (REG_80) },

1491 { REG_TABLE (REG_81) },	1822 { REG_TABLE (REG_81) },

1492 { "(bad)",» » { XX } },	1823 { Bad_Opcode },

1493 { REG_TABLE (REG_82) },	1824 { REG_TABLE (REG_82) },

1494 { "testB", { Eb, Gb } },	1825 { "testB", { Eb, Gb } },

1495 { "testS", { Ev, Gv } },	1826 { "testS", { Ev, Gv } },

1496 { "xchgB",» » { Eb, Gb } },	1827 { "xchgB",» » { Ebh2, Gb } },

1497 { "xchgS",» » { Ev, Gv } },	1828 { "xchgS",» » { Evh2, Gv } },

1498 /* 88 */	1829 /* 88 */

1499 { "movB",» » { Eb, Gb } },	1830 { "movB",» » { Ebh3, Gb } },

1500 { "movS",» » { Ev, Gv } },	1831 { "movS",» » { Evh3, Gv } },

1501 { "movB", { Gb, EbS } },	1832 { "movB", { Gb, EbS } },

1502 { "movS", { Gv, EvS } },	1833 { "movS", { Gv, EvS } },

1503 { "movD", { Sv, Sw } },	1834 { "movD", { Sv, Sw } },

1504 { MOD_TABLE (MOD_8D) },	1835 { MOD_TABLE (MOD_8D) },

1505 { "movD", { Sw, Sv } },	1836 { "movD", { Sw, Sv } },

1506 { REG_TABLE (REG_8F) },	1837 { REG_TABLE (REG_8F) },

1507 /* 90 */	1838 /* 90 */

1508 { PREFIX_TABLE (PREFIX_90) },	1839 { PREFIX_TABLE (PREFIX_90) },

1509 { "xchgS", { RMeCX, eAX } },	1840 { "xchgS", { RMeCX, eAX } },

1510 { "xchgS", { RMeDX, eAX } },	1841 { "xchgS", { RMeDX, eAX } },

1511 { "xchgS", { RMeBX, eAX } },	1842 { "xchgS", { RMeBX, eAX } },

1512 { "xchgS", { RMeSP, eAX } },	1843 { "xchgS", { RMeSP, eAX } },

1513 { "xchgS", { RMeBP, eAX } },	1844 { "xchgS", { RMeBP, eAX } },

1514 { "xchgS", { RMeSI, eAX } },	1845 { "xchgS", { RMeSI, eAX } },

1515 { "xchgS", { RMeDI, eAX } },	1846 { "xchgS", { RMeDI, eAX } },

1516 /* 98 */	1847 /* 98 */

1517 { "cW{t\|}R", { XX } },	1848 { "cW{t\|}R", { XX } },

1518 { "cR{t\|}O", { XX } },	1849 { "cR{t\|}O", { XX } },

1519 { X86_64_TABLE (X86_64_9A) },	1850 { X86_64_TABLE (X86_64_9A) },

1520 { "(bad)",» » { XX } },» /* fwait */	1851 { Bad_Opcode },» /* fwait */

1521 { "pushfT", { XX } },	1852 { "pushfT", { XX } },

1522 { "popfT", { XX } },	1853 { "popfT", { XX } },

1523 { "sahf", { XX } },	1854 { "sahf", { XX } },

1524 { "lahf", { XX } },	1855 { "lahf", { XX } },

1525 /* a0 */	1856 /* a0 */

1526 { "movB",» » { AL, Ob } },	1857 { "mov%LB",» » { AL, Ob } },

1527 { "movS",» » { eAX, Ov } },	1858 { "mov%LS",» » { eAX, Ov } },

1528 { "movB",» » { Ob, AL } },	1859 { "mov%LB",» » { Ob, AL } },

1529 { "movS",» » { Ov, eAX } },	1860 { "mov%LS",» » { Ov, eAX } },

1530 { "movs{b\|}", { Ybr, Xb } },	1861 { "movs{b\|}", { Ybr, Xb } },

1531 { "movs{R\|}", { Yvr, Xv } },	1862 { "movs{R\|}", { Yvr, Xv } },

1532 { "cmps{b\|}", { Xb, Yb } },	1863 { "cmps{b\|}", { Xb, Yb } },

1533 { "cmps{R\|}", { Xv, Yv } },	1864 { "cmps{R\|}", { Xv, Yv } },

1534 /* a8 */	1865 /* a8 */

1535 { "testB", { AL, Ib } },	1866 { "testB", { AL, Ib } },

1536 { "testS", { eAX, Iv } },	1867 { "testS", { eAX, Iv } },

1537 { "stosB", { Ybr, AL } },	1868 { "stosB", { Ybr, AL } },

1538 { "stosS", { Yvr, eAX } },	1869 { "stosS", { Yvr, eAX } },

1539 { "lodsB", { ALr, Xb } },	1870 { "lodsB", { ALr, Xb } },

1540 { "lodsS", { eAXr, Xv } },	1871 { "lodsS", { eAXr, Xv } },

1541 { "scasB", { AL, Yb } },	1872 { "scasB", { AL, Yb } },

1542 { "scasS", { eAX, Yv } },	1873 { "scasS", { eAX, Yv } },

1543 /* b0 */	1874 /* b0 */

1544 { "movB", { RMAL, Ib } },	1875 { "movB", { RMAL, Ib } },

1545 { "movB", { RMCL, Ib } },	1876 { "movB", { RMCL, Ib } },

1546 { "movB", { RMDL, Ib } },	1877 { "movB", { RMDL, Ib } },

1547 { "movB", { RMBL, Ib } },	1878 { "movB", { RMBL, Ib } },

1548 { "movB", { RMAH, Ib } },	1879 { "movB", { RMAH, Ib } },

1549 { "movB", { RMCH, Ib } },	1880 { "movB", { RMCH, Ib } },

1550 { "movB", { RMDH, Ib } },	1881 { "movB", { RMDH, Ib } },

1551 { "movB", { RMBH, Ib } },	1882 { "movB", { RMBH, Ib } },

1552 /* b8 */	1883 /* b8 */

1553 { "movS",» » { RMeAX, Iv64 } },	1884 { "mov%LV",» » { RMeAX, Iv64 } },

1554 { "movS",» » { RMeCX, Iv64 } },	1885 { "mov%LV",» » { RMeCX, Iv64 } },

1555 { "movS",» » { RMeDX, Iv64 } },	1886 { "mov%LV",» » { RMeDX, Iv64 } },

1556 { "movS",» » { RMeBX, Iv64 } },	1887 { "mov%LV",» » { RMeBX, Iv64 } },

1557 { "movS",» » { RMeSP, Iv64 } },	1888 { "mov%LV",» » { RMeSP, Iv64 } },

1558 { "movS",» » { RMeBP, Iv64 } },	1889 { "mov%LV",» » { RMeBP, Iv64 } },

1559 { "movS",» » { RMeSI, Iv64 } },	1890 { "mov%LV",» » { RMeSI, Iv64 } },

1560 { "movS",» » { RMeDI, Iv64 } },	1891 { "mov%LV",» » { RMeDI, Iv64 } },

1561 /* c0 */	1892 /* c0 */

1562 { REG_TABLE (REG_C0) },	1893 { REG_TABLE (REG_C0) },

1563 { REG_TABLE (REG_C1) },	1894 { REG_TABLE (REG_C1) },

1564 { "retT", { Iw } },	1895 { "retT", { Iw } },

1565 { "retT", { XX } },	1896 { "retT", { XX } },

1566 { X86_64_TABLE (X86_64_C4) },	1897 { X86_64_TABLE (X86_64_C4) },

1567 { X86_64_TABLE (X86_64_C5) },	1898 { X86_64_TABLE (X86_64_C5) },

1568 { REG_TABLE (REG_C6) },	1899 { REG_TABLE (REG_C6) },

1569 { REG_TABLE (REG_C7) },	1900 { REG_TABLE (REG_C7) },

1570 /* c8 */	1901 /* c8 */

1571 { "enterT", { Iw, Ib } },	1902 { "enterT", { Iw, Ib } },

1572 { "leaveT", { XX } },	1903 { "leaveT", { XX } },

1573 { "Jret{\|f}P", { Iw } },	1904 { "Jret{\|f}P", { Iw } },

1574 { "Jret{\|f}P", { XX } },	1905 { "Jret{\|f}P", { XX } },

1575 { "int3", { XX } },	1906 { "int3", { XX } },

1576 { "int", { Ib } },	1907 { "int", { Ib } },

1577 { X86_64_TABLE (X86_64_CE) },	1908 { X86_64_TABLE (X86_64_CE) },

1578 { "iretP", { XX } },	1909 { "iretP", { XX } },

1579 /* d0 */	1910 /* d0 */

1580 { REG_TABLE (REG_D0) },	1911 { REG_TABLE (REG_D0) },

1581 { REG_TABLE (REG_D1) },	1912 { REG_TABLE (REG_D1) },

1582 { REG_TABLE (REG_D2) },	1913 { REG_TABLE (REG_D2) },

1583 { REG_TABLE (REG_D3) },	1914 { REG_TABLE (REG_D3) },

1584 { X86_64_TABLE (X86_64_D4) },	1915 { X86_64_TABLE (X86_64_D4) },

1585 { X86_64_TABLE (X86_64_D5) },	1916 { X86_64_TABLE (X86_64_D5) },

1586 { "(bad)",» » { XX } },	1917 { Bad_Opcode },

1587 { "xlat", { DSBX } },	1918 { "xlat", { DSBX } },

1588 /* d8 */	1919 /* d8 */

1589 { FLOAT },	1920 { FLOAT },

1590 { FLOAT },	1921 { FLOAT },

1591 { FLOAT },	1922 { FLOAT },

1592 { FLOAT },	1923 { FLOAT },

1593 { FLOAT },	1924 { FLOAT },

1594 { FLOAT },	1925 { FLOAT },

1595 { FLOAT },	1926 { FLOAT },

1596 { FLOAT },	1927 { FLOAT },

1597 /* e0 */	1928 /* e0 */

1598 { "loopneFH", { Jb, XX, loop_jcxz_flag } },	1929 { "loopneFH", { Jb, XX, loop_jcxz_flag } },

1599 { "loopeFH", { Jb, XX, loop_jcxz_flag } },	1930 { "loopeFH", { Jb, XX, loop_jcxz_flag } },

1600 { "loopFH", { Jb, XX, loop_jcxz_flag } },	1931 { "loopFH", { Jb, XX, loop_jcxz_flag } },

1601 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },	1932 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },

1602 { "inB", { AL, Ib } },	1933 { "inB", { AL, Ib } },

1603 { "inG", { zAX, Ib } },	1934 { "inG", { zAX, Ib } },

1604 { "outB", { Ib, AL } },	1935 { "outB", { Ib, AL } },

1605 { "outG", { Ib, zAX } },	1936 { "outG", { Ib, zAX } },

1606 /* e8 */	1937 /* e8 */

1607 { "callT", { Jv } },	1938 { "callT", { Jv } },

1608 { "jmpT", { Jv } },	1939 { "jmpT", { Jv } },

1609 { X86_64_TABLE (X86_64_EA) },	1940 { X86_64_TABLE (X86_64_EA) },

1610 { "jmp", { Jb } },	1941 { "jmp", { Jb } },

1611 { "inB", { AL, indirDX } },	1942 { "inB", { AL, indirDX } },

1612 { "inG", { zAX, indirDX } },	1943 { "inG", { zAX, indirDX } },

1613 { "outB", { indirDX, AL } },	1944 { "outB", { indirDX, AL } },

1614 { "outG", { indirDX, zAX } },	1945 { "outG", { indirDX, zAX } },

1615 /* f0 */	1946 /* f0 */

1616 { "(bad)",» » { XX } },» /* lock prefix */	1947 { Bad_Opcode },» /* lock prefix */

1617 { "icebp", { XX } },	1948 { "icebp", { XX } },

1618 { "(bad)",» » { XX } },» /* repne */	1949 { Bad_Opcode },» /* repne */

1619 { "(bad)",» » { XX } },» /* repz */	1950 { Bad_Opcode },» /* repz */

1620 { "hlt", { XX } },	1951 { "hlt", { XX } },

1621 { "cmc", { XX } },	1952 { "cmc", { XX } },

1622 { REG_TABLE (REG_F6) },	1953 { REG_TABLE (REG_F6) },

1623 { REG_TABLE (REG_F7) },	1954 { REG_TABLE (REG_F7) },

1624 /* f8 */	1955 /* f8 */

1625 { "clc", { XX } },	1956 { "clc", { XX } },

1626 { "stc", { XX } },	1957 { "stc", { XX } },

1627 { "cli", { XX } },	1958 { "cli", { XX } },

1628 { "sti", { XX } },	1959 { "sti", { XX } },

1629 { "cld", { XX } },	1960 { "cld", { XX } },

1630 { "std", { XX } },	1961 { "std", { XX } },

1631 { REG_TABLE (REG_FE) },	1962 { REG_TABLE (REG_FE) },

1632 { REG_TABLE (REG_FF) },	1963 { REG_TABLE (REG_FF) },

1633 };	1964 };

1634	1965

1635 static const struct dis386 dis386_twobyte[] = {	1966 static const struct dis386 dis386_twobyte[] = {

1636 /* 00 */	1967 /* 00 */

1637 { REG_TABLE (REG_0F00 ) },	1968 { REG_TABLE (REG_0F00 ) },

1638 { REG_TABLE (REG_0F01 ) },	1969 { REG_TABLE (REG_0F01 ) },

1639 { "larS", { Gv, Ew } },	1970 { "larS", { Gv, Ew } },

1640 { "lslS", { Gv, Ew } },	1971 { "lslS", { Gv, Ew } },

1641 { "(bad)",» » { XX } },	1972 { Bad_Opcode },

1642 { "syscall", { XX } },	1973 { "syscall", { XX } },

1643 { "clts", { XX } },	1974 { "clts", { XX } },

1644 { "sysretP", { XX } },	1975 { "sysretP", { XX } },

1645 /* 08 */	1976 /* 08 */

1646 { "invd", { XX } },	1977 { "invd", { XX } },

1647 { "wbinvd", { XX } },	1978 { "wbinvd", { XX } },

1648 { "(bad)",» » { XX } },	1979 { Bad_Opcode },

1649 { "ud2a",» » { XX } },	1980 { "ud2",» » { XX } },

1650 { "(bad)",» » { XX } },	1981 { Bad_Opcode },

1651 { REG_TABLE (REG_0F0D) },	1982 { REG_TABLE (REG_0F0D) },

1652 { "femms", { XX } },	1983 { "femms", { XX } },

1653 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */	1984 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */

1654 /* 10 */	1985 /* 10 */

1655 { PREFIX_TABLE (PREFIX_0F10) },	1986 { PREFIX_TABLE (PREFIX_0F10) },

1656 { PREFIX_TABLE (PREFIX_0F11) },	1987 { PREFIX_TABLE (PREFIX_0F11) },

1657 { PREFIX_TABLE (PREFIX_0F12) },	1988 { PREFIX_TABLE (PREFIX_0F12) },

1658 { MOD_TABLE (MOD_0F13) },	1989 { MOD_TABLE (MOD_0F13) },

1659 { "unpcklpX", { XM, EXx } },	1990 { "unpcklpX", { XM, EXx } },

1660 { "unpckhpX", { XM, EXx } },	1991 { "unpckhpX", { XM, EXx } },

1661 { PREFIX_TABLE (PREFIX_0F16) },	1992 { PREFIX_TABLE (PREFIX_0F16) },

1662 { MOD_TABLE (MOD_0F17) },	1993 { MOD_TABLE (MOD_0F17) },

1663 /* 18 */	1994 /* 18 */

1664 { REG_TABLE (REG_0F18) },	1995 { REG_TABLE (REG_0F18) },

1665 { "nopQ", { Ev } },	1996 { "nopQ", { Ev } },

1666 { "nopQ", { Ev } },	1997 { "nopQ", { Ev } },

1667 { "nopQ", { Ev } },	1998 { "nopQ", { Ev } },

1668 { "nopQ", { Ev } },	1999 { "nopQ", { Ev } },

1669 { "nopQ", { Ev } },	2000 { "nopQ", { Ev } },

1670 { "nopQ", { Ev } },	2001 { "nopQ", { Ev } },

1671 { "nopQ", { Ev } },	2002 { "nopQ", { Ev } },

1672 /* 20 */	2003 /* 20 */

1673 { MOD_TABLE (MOD_0F20) },	2004 { MOD_TABLE (MOD_0F20) },

1674 { MOD_TABLE (MOD_0F21) },	2005 { MOD_TABLE (MOD_0F21) },

1675 { MOD_TABLE (MOD_0F22) },	2006 { MOD_TABLE (MOD_0F22) },

1676 { MOD_TABLE (MOD_0F23) },	2007 { MOD_TABLE (MOD_0F23) },

1677 { MOD_TABLE (MOD_0F24) },	2008 { MOD_TABLE (MOD_0F24) },

1678 { "(bad)",» » { XX } },	2009 { Bad_Opcode },

1679 { MOD_TABLE (MOD_0F26) },	2010 { MOD_TABLE (MOD_0F26) },

1680 { "(bad)",» » { XX } },	2011 { Bad_Opcode },

1681 /* 28 */	2012 /* 28 */

1682 { "movapX", { XM, EXx } },	2013 { "movapX", { XM, EXx } },

1683 { "movapX", { EXxS, XM } },	2014 { "movapX", { EXxS, XM } },

1684 { PREFIX_TABLE (PREFIX_0F2A) },	2015 { PREFIX_TABLE (PREFIX_0F2A) },

1685 { PREFIX_TABLE (PREFIX_0F2B) },	2016 { PREFIX_TABLE (PREFIX_0F2B) },

1686 { PREFIX_TABLE (PREFIX_0F2C) },	2017 { PREFIX_TABLE (PREFIX_0F2C) },

1687 { PREFIX_TABLE (PREFIX_0F2D) },	2018 { PREFIX_TABLE (PREFIX_0F2D) },

1688 { PREFIX_TABLE (PREFIX_0F2E) },	2019 { PREFIX_TABLE (PREFIX_0F2E) },

1689 { PREFIX_TABLE (PREFIX_0F2F) },	2020 { PREFIX_TABLE (PREFIX_0F2F) },

1690 /* 30 */	2021 /* 30 */

1691 { "wrmsr", { XX } },	2022 { "wrmsr", { XX } },

1692 { "rdtsc", { XX } },	2023 { "rdtsc", { XX } },

1693 { "rdmsr", { XX } },	2024 { "rdmsr", { XX } },

1694 { "rdpmc", { XX } },	2025 { "rdpmc", { XX } },

1695 { "sysenter", { XX } },	2026 { "sysenter", { XX } },

1696 { "sysexit", { XX } },	2027 { "sysexit", { XX } },

1697 { "(bad)",» » { XX } },	2028 { Bad_Opcode },

1698 { "getsec", { XX } },	2029 { "getsec", { XX } },

1699 /* 38 */	2030 /* 38 */

1700 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },	2031 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },

1701 { "(bad)",» » { XX } },	2032 { Bad_Opcode },

1702 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },	2033 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },

1703 { "(bad)",» » { XX } },	2034 { Bad_Opcode },

1704 { "(bad)",» » { XX } },	2035 { Bad_Opcode },

1705 { "(bad)",» » { XX } },	2036 { Bad_Opcode },

1706 { "(bad)",» » { XX } },	2037 { Bad_Opcode },

1707 { "(bad)",» » { XX } },	2038 { Bad_Opcode },

1708 /* 40 */	2039 /* 40 */

1709 { "cmovoS", { Gv, Ev } },	2040 { "cmovoS", { Gv, Ev } },

1710 { "cmovnoS", { Gv, Ev } },	2041 { "cmovnoS", { Gv, Ev } },

1711 { "cmovbS", { Gv, Ev } },	2042 { "cmovbS", { Gv, Ev } },

1712 { "cmovaeS", { Gv, Ev } },	2043 { "cmovaeS", { Gv, Ev } },

1713 { "cmoveS", { Gv, Ev } },	2044 { "cmoveS", { Gv, Ev } },

1714 { "cmovneS", { Gv, Ev } },	2045 { "cmovneS", { Gv, Ev } },

1715 { "cmovbeS", { Gv, Ev } },	2046 { "cmovbeS", { Gv, Ev } },

1716 { "cmovaS", { Gv, Ev } },	2047 { "cmovaS", { Gv, Ev } },

1717 /* 48 */	2048 /* 48 */

(...skipping 47 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
1765 { REG_TABLE (REG_0F72) },	2096 { REG_TABLE (REG_0F72) },

1766 { REG_TABLE (REG_0F73) },	2097 { REG_TABLE (REG_0F73) },

1767 { "pcmpeqb", { MX, EM } },	2098 { "pcmpeqb", { MX, EM } },

1768 { "pcmpeqw", { MX, EM } },	2099 { "pcmpeqw", { MX, EM } },

1769 { "pcmpeqd", { MX, EM } },	2100 { "pcmpeqd", { MX, EM } },

1770 { "emms", { XX } },	2101 { "emms", { XX } },

1771 /* 78 */	2102 /* 78 */

1772 { PREFIX_TABLE (PREFIX_0F78) },	2103 { PREFIX_TABLE (PREFIX_0F78) },

1773 { PREFIX_TABLE (PREFIX_0F79) },	2104 { PREFIX_TABLE (PREFIX_0F79) },

1774 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },	2105 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },

1775 { "(bad)",» » { XX } },	2106 { Bad_Opcode },

1776 { PREFIX_TABLE (PREFIX_0F7C) },	2107 { PREFIX_TABLE (PREFIX_0F7C) },

1777 { PREFIX_TABLE (PREFIX_0F7D) },	2108 { PREFIX_TABLE (PREFIX_0F7D) },

1778 { PREFIX_TABLE (PREFIX_0F7E) },	2109 { PREFIX_TABLE (PREFIX_0F7E) },

1779 { PREFIX_TABLE (PREFIX_0F7F) },	2110 { PREFIX_TABLE (PREFIX_0F7F) },

1780 /* 80 */	2111 /* 80 */

1781 { "joH", { Jv, XX, cond_jump_flag } },	2112 { "joH", { Jv, XX, cond_jump_flag } },

1782 { "jnoH", { Jv, XX, cond_jump_flag } },	2113 { "jnoH", { Jv, XX, cond_jump_flag } },

1783 { "jbH", { Jv, XX, cond_jump_flag } },	2114 { "jbH", { Jv, XX, cond_jump_flag } },

1784 { "jaeH", { Jv, XX, cond_jump_flag } },	2115 { "jaeH", { Jv, XX, cond_jump_flag } },

1785 { "jeH", { Jv, XX, cond_jump_flag } },	2116 { "jeH", { Jv, XX, cond_jump_flag } },

(...skipping 33 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
1819 { "cpuid", { XX } },	2150 { "cpuid", { XX } },

1820 { "btS", { Ev, Gv } },	2151 { "btS", { Ev, Gv } },

1821 { "shldS", { Ev, Gv, Ib } },	2152 { "shldS", { Ev, Gv, Ib } },

1822 { "shldS", { Ev, Gv, CL } },	2153 { "shldS", { Ev, Gv, CL } },

1823 { REG_TABLE (REG_0FA6) },	2154 { REG_TABLE (REG_0FA6) },

1824 { REG_TABLE (REG_0FA7) },	2155 { REG_TABLE (REG_0FA7) },

1825 /* a8 */	2156 /* a8 */

1826 { "pushT", { gs } },	2157 { "pushT", { gs } },

1827 { "popT", { gs } },	2158 { "popT", { gs } },

1828 { "rsm", { XX } },	2159 { "rsm", { XX } },

1829 { "btsS",» » { Ev, Gv } },	2160 { "btsS",» » { Evh1, Gv } },

1830 { "shrdS", { Ev, Gv, Ib } },	2161 { "shrdS", { Ev, Gv, Ib } },

1831 { "shrdS", { Ev, Gv, CL } },	2162 { "shrdS", { Ev, Gv, CL } },

1832 { REG_TABLE (REG_0FAE) },	2163 { REG_TABLE (REG_0FAE) },

1833 { "imulS", { Gv, Ev } },	2164 { "imulS", { Gv, Ev } },

1834 /* b0 */	2165 /* b0 */

1835 { "cmpxchgB",»» { Eb, Gb } },	2166 { "cmpxchgB",»» { Ebh1, Gb } },

1836 { "cmpxchgS",»» { Ev, Gv } },	2167 { "cmpxchgS",»» { Evh1, Gv } },

1837 { MOD_TABLE (MOD_0FB2) },	2168 { MOD_TABLE (MOD_0FB2) },

1838 { "btrS",» » { Ev, Gv } },	2169 { "btrS",» » { Evh1, Gv } },

1839 { MOD_TABLE (MOD_0FB4) },	2170 { MOD_TABLE (MOD_0FB4) },

1840 { MOD_TABLE (MOD_0FB5) },	2171 { MOD_TABLE (MOD_0FB5) },

1841 { "movz{bR\|x}", { Gv, Eb } },	2172 { "movz{bR\|x}", { Gv, Eb } },

1842 { "movz{wR\|x}", { Gv, Ew } }, /* yes, there really is movzww ! */	2173 { "movz{wR\|x}", { Gv, Ew } }, /* yes, there really is movzww ! */

1843 /* b8 */	2174 /* b8 */

1844 { PREFIX_TABLE (PREFIX_0FB8) },	2175 { PREFIX_TABLE (PREFIX_0FB8) },

1845 { "ud2b",» » { XX } },	2176 { "ud1",» » { XX } },

1846 { REG_TABLE (REG_0FBA) },	2177 { REG_TABLE (REG_0FBA) },

1847 { "btcS",» » { Ev, Gv } },	2178 { "btcS",» » { Evh1, Gv } },

1848 { "bsfS",» » { Gv, Ev } },	2179 { PREFIX_TABLE (PREFIX_0FBC) },

1849 { PREFIX_TABLE (PREFIX_0FBD) },	2180 { PREFIX_TABLE (PREFIX_0FBD) },

1850 { "movs{bR\|x}", { Gv, Eb } },	2181 { "movs{bR\|x}", { Gv, Eb } },

1851 { "movs{wR\|x}", { Gv, Ew } }, /* yes, there really is movsww ! */	2182 { "movs{wR\|x}", { Gv, Ew } }, /* yes, there really is movsww ! */

1852 /* c0 */	2183 /* c0 */

1853 { "xaddB",» » { Eb, Gb } },	2184 { "xaddB",» » { Ebh1, Gb } },

1854 { "xaddS",» » { Ev, Gv } },	2185 { "xaddS",» » { Evh1, Gv } },

1855 { PREFIX_TABLE (PREFIX_0FC2) },	2186 { PREFIX_TABLE (PREFIX_0FC2) },

1856 { PREFIX_TABLE (PREFIX_0FC3) },	2187 { PREFIX_TABLE (PREFIX_0FC3) },

1857 { "pinsrw", { MX, Edqw, Ib } },	2188 { "pinsrw", { MX, Edqw, Ib } },

1858 { "pextrw", { Gdq, MS, Ib } },	2189 { "pextrw", { Gdq, MS, Ib } },

1859 { "shufpX", { XM, EXx, Ib } },	2190 { "shufpX", { XM, EXx, Ib } },

1860 { REG_TABLE (REG_0FC7) },	2191 { REG_TABLE (REG_0FC7) },

1861 /* c8 */	2192 /* c8 */

1862 { "bswap", { RMeAX } },	2193 { "bswap", { RMeAX } },

1863 { "bswap", { RMeCX } },	2194 { "bswap", { RMeCX } },

1864 { "bswap", { RMeDX } },	2195 { "bswap", { RMeDX } },

(...skipping 48 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
1913 { "psadbw", { MX, EM } },	2244 { "psadbw", { MX, EM } },

1914 { PREFIX_TABLE (PREFIX_0FF7) },	2245 { PREFIX_TABLE (PREFIX_0FF7) },

1915 /* f8 */	2246 /* f8 */

1916 { "psubb", { MX, EM } },	2247 { "psubb", { MX, EM } },

1917 { "psubw", { MX, EM } },	2248 { "psubw", { MX, EM } },

1918 { "psubd", { MX, EM } },	2249 { "psubd", { MX, EM } },

1919 { "psubq", { MX, EM } },	2250 { "psubq", { MX, EM } },

1920 { "paddb", { MX, EM } },	2251 { "paddb", { MX, EM } },

1921 { "paddw", { MX, EM } },	2252 { "paddw", { MX, EM } },

1922 { "paddd", { MX, EM } },	2253 { "paddd", { MX, EM } },

1923 { "(bad)",» » { XX } },	2254 { Bad_Opcode },

1924 };	2255 };

1925	2256

1926 static const unsigned char onebyte_has_modrm[256] = {	2257 static const unsigned char onebyte_has_modrm[256] = {

1927 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */	2258 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */

1928 /* ------------------------------- */	2259 /* ------------------------------- */

1929 /* 00 / 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, / 00 */	2260 /* 00 / 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, / 00 */

1930 /* 10 / 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, / 10 */	2261 /* 10 / 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, / 10 */

1931 /* 20 / 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, / 20 */	2262 /* 20 / 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, / 20 */

1932 /* 30 / 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, / 30 */	2263 /* 30 / 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, / 30 */

1933 /* 40 / 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, / 40 */	2264 /* 40 / 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, / 40 */

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1969 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */	2300 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */

1970 };	2301 };

1971	2302

1972 static char obuf[100];	2303 static char obuf[100];

1973 static char *obufp;	2304 static char *obufp;

1974 static char *mnemonicendp;	2305 static char *mnemonicendp;

1975 static char scratchbuf[100];	2306 static char scratchbuf[100];

1976 static unsigned char *start_codep;	2307 static unsigned char *start_codep;

1977 static unsigned char *insn_codep;	2308 static unsigned char *insn_codep;

1978 static unsigned char *codep;	2309 static unsigned char *codep;

1979 static const char *lock_prefix;	2310 static int last_lock_prefix;

1980 static const char *data_prefix;	2311 static int last_repz_prefix;

1981 static const char *addr_prefix;	2312 static int last_repnz_prefix;

1982 static const char *repz_prefix;	2313 static int last_data_prefix;

1983 static const char *repnz_prefix;	2314 static int last_addr_prefix;

	2315 static int last_rex_prefix;

	2316 static int last_seg_prefix;

	2317 #define MAX_CODE_LENGTH 15

	2318 /* We can up to 14 prefixes since the maximum instruction length is

	2319 15bytes. */

	2320 static int all_prefixes[MAX_CODE_LENGTH - 1];

1984 static disassemble_info *the_info;	2321 static disassemble_info *the_info;

1985 static struct	2322 static struct

1986 {	2323 {

1987 int mod;	2324 int mod;

1988 int reg;	2325 int reg;

1989 int rm;	2326 int rm;

1990 }	2327 }

1991 modrm;	2328 modrm;

1992 static unsigned char need_modrm;	2329 static unsigned char need_modrm;

1993 static struct	2330 static struct

1994 {	2331 {

	2332 int scale;

	2333 int index;

	2334 int base;

	2335 }

	2336 sib;

	2337 static struct

	2338 {

1995 int register_specifier;	2339 int register_specifier;

1996 int length;	2340 int length;

1997 int prefix;	2341 int prefix;

1998 int w;	2342 int w;

1999 }	2343 }

2000 vex;	2344 vex;

2001 static unsigned char need_vex;	2345 static unsigned char need_vex;

2002 static unsigned char need_vex_reg;	2346 static unsigned char need_vex_reg;

2003 static unsigned char vex_w_done;	2347 static unsigned char vex_w_done;

2004	2348

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2072 };	2416 };

2073 static const char *att_names_seg[] = {	2417 static const char *att_names_seg[] = {

2074 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",	2418 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",

2075 };	2419 };

2076 static const char *att_index64 = "%riz";	2420 static const char *att_index64 = "%riz";

2077 static const char *att_index32 = "%eiz";	2421 static const char *att_index32 = "%eiz";

2078 static const char *att_index16[] = {	2422 static const char *att_index16[] = {

2079 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"	2423 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"

2080 };	2424 };

2081	2425

	2426 static const char **names_mm;

	2427 static const char *intel_names_mm[] = {

	2428 "mm0", "mm1", "mm2", "mm3",

	2429 "mm4", "mm5", "mm6", "mm7"

	2430 };

	2431 static const char *att_names_mm[] = {

	2432 "%mm0", "%mm1", "%mm2", "%mm3",

	2433 "%mm4", "%mm5", "%mm6", "%mm7"

	2434 };

	2435

	2436 static const char **names_xmm;

	2437 static const char *intel_names_xmm[] = {

	2438 "xmm0", "xmm1", "xmm2", "xmm3",

	2439 "xmm4", "xmm5", "xmm6", "xmm7",

	2440 "xmm8", "xmm9", "xmm10", "xmm11",

	2441 "xmm12", "xmm13", "xmm14", "xmm15"

	2442 };

	2443 static const char *att_names_xmm[] = {

	2444 "%xmm0", "%xmm1", "%xmm2", "%xmm3",

	2445 "%xmm4", "%xmm5", "%xmm6", "%xmm7",

	2446 "%xmm8", "%xmm9", "%xmm10", "%xmm11",

	2447 "%xmm12", "%xmm13", "%xmm14", "%xmm15"

	2448 };

	2449

	2450 static const char **names_ymm;

	2451 static const char *intel_names_ymm[] = {

	2452 "ymm0", "ymm1", "ymm2", "ymm3",

	2453 "ymm4", "ymm5", "ymm6", "ymm7",

	2454 "ymm8", "ymm9", "ymm10", "ymm11",

	2455 "ymm12", "ymm13", "ymm14", "ymm15"

	2456 };

	2457 static const char *att_names_ymm[] = {

	2458 "%ymm0", "%ymm1", "%ymm2", "%ymm3",

	2459 "%ymm4", "%ymm5", "%ymm6", "%ymm7",

	2460 "%ymm8", "%ymm9", "%ymm10", "%ymm11",

	2461 "%ymm12", "%ymm13", "%ymm14", "%ymm15"

	2462 };

	2463

2082 static const struct dis386 reg_table[][8] = {	2464 static const struct dis386 reg_table[][8] = {

2083 /* REG_80 */	2465 /* REG_80 */

2084 {	2466 {

2085 { "addA",» { Eb, Ib } },	2467 { "addA",» { Ebh1, Ib } },

2086 { "orA",» { Eb, Ib } },	2468 { "orA",» { Ebh1, Ib } },

2087 { "adcA",» { Eb, Ib } },	2469 { "adcA",» { Ebh1, Ib } },

2088 { "sbbA",» { Eb, Ib } },	2470 { "sbbA",» { Ebh1, Ib } },

2089 { "andA",» { Eb, Ib } },	2471 { "andA",» { Ebh1, Ib } },

2090 { "subA",» { Eb, Ib } },	2472 { "subA",» { Ebh1, Ib } },

2091 { "xorA",» { Eb, Ib } },	2473 { "xorA",» { Ebh1, Ib } },

2092 { "cmpA", { Eb, Ib } },	2474 { "cmpA", { Eb, Ib } },

2093 },	2475 },

2094 /* REG_81 */	2476 /* REG_81 */

2095 {	2477 {

2096 { "addQ",» { Ev, Iv } },	2478 { "addQ",» { Evh1, Iv } },

2097 { "orQ",» { Ev, Iv } },	2479 { "orQ",» { Evh1, Iv } },

2098 { "adcQ",» { Ev, Iv } },	2480 { "adcQ",» { Evh1, Iv } },

2099 { "sbbQ",» { Ev, Iv } },	2481 { "sbbQ",» { Evh1, Iv } },

2100 { "andQ",» { Ev, Iv } },	2482 { "andQ",» { Evh1, Iv } },

2101 { "subQ",» { Ev, Iv } },	2483 { "subQ",» { Evh1, Iv } },

2102 { "xorQ",» { Ev, Iv } },	2484 { "xorQ",» { Evh1, Iv } },

2103 { "cmpQ", { Ev, Iv } },	2485 { "cmpQ", { Ev, Iv } },

2104 },	2486 },

2105 /* REG_82 */	2487 /* REG_82 */

2106 {	2488 {

2107 { "addQ",» { Ev, sIb } },	2489 { "addQ",» { Evh1, sIb } },

2108 { "orQ",» { Ev, sIb } },	2490 { "orQ",» { Evh1, sIb } },

2109 { "adcQ",» { Ev, sIb } },	2491 { "adcQ",» { Evh1, sIb } },

2110 { "sbbQ",» { Ev, sIb } },	2492 { "sbbQ",» { Evh1, sIb } },

2111 { "andQ",» { Ev, sIb } },	2493 { "andQ",» { Evh1, sIb } },

2112 { "subQ",» { Ev, sIb } },	2494 { "subQ",» { Evh1, sIb } },

2113 { "xorQ",» { Ev, sIb } },	2495 { "xorQ",» { Evh1, sIb } },

2114 { "cmpQ", { Ev, sIb } },	2496 { "cmpQ", { Ev, sIb } },

2115 },	2497 },

2116 /* REG_8F */	2498 /* REG_8F */

2117 {	2499 {

2118 { "popU", { stackEv } },	2500 { "popU", { stackEv } },

2119 { "(bad)",» { XX } },	2501 { XOP_8F_TABLE (XOP_09) },

2120 { "(bad)",» { XX } },	2502 { Bad_Opcode },

2121 { "(bad)",» { XX } },	2503 { Bad_Opcode },

2122 { "(bad)",» { XX } },	2504 { Bad_Opcode },

2123 { "(bad)",» { XX } },	2505 { XOP_8F_TABLE (XOP_09) },

2124 { "(bad)",» { XX } },

2125 { "(bad)",» { XX } },

2126 },	2506 },

2127 /* REG_C0 */	2507 /* REG_C0 */

2128 {	2508 {

2129 { "rolA", { Eb, Ib } },	2509 { "rolA", { Eb, Ib } },

2130 { "rorA", { Eb, Ib } },	2510 { "rorA", { Eb, Ib } },

2131 { "rclA", { Eb, Ib } },	2511 { "rclA", { Eb, Ib } },

2132 { "rcrA", { Eb, Ib } },	2512 { "rcrA", { Eb, Ib } },

2133 { "shlA", { Eb, Ib } },	2513 { "shlA", { Eb, Ib } },

2134 { "shrA", { Eb, Ib } },	2514 { "shrA", { Eb, Ib } },

2135 { "(bad)",» { XX } },	2515 { Bad_Opcode },

2136 { "sarA", { Eb, Ib } },	2516 { "sarA", { Eb, Ib } },

2137 },	2517 },

2138 /* REG_C1 */	2518 /* REG_C1 */

2139 {	2519 {

2140 { "rolQ", { Ev, Ib } },	2520 { "rolQ", { Ev, Ib } },

2141 { "rorQ", { Ev, Ib } },	2521 { "rorQ", { Ev, Ib } },

2142 { "rclQ", { Ev, Ib } },	2522 { "rclQ", { Ev, Ib } },

2143 { "rcrQ", { Ev, Ib } },	2523 { "rcrQ", { Ev, Ib } },

2144 { "shlQ", { Ev, Ib } },	2524 { "shlQ", { Ev, Ib } },

2145 { "shrQ", { Ev, Ib } },	2525 { "shrQ", { Ev, Ib } },

2146 { "(bad)",» { XX } },	2526 { Bad_Opcode },

2147 { "sarQ", { Ev, Ib } },	2527 { "sarQ", { Ev, Ib } },

2148 },	2528 },

2149 /* REG_C6 */	2529 /* REG_C6 */

2150 {	2530 {

2151 { "movA",» { Eb, Ib } },	2531 { "movA",» { Ebh3, Ib } },

2152 { "(bad)",» { XX } },	2532 { Bad_Opcode },

2153 { "(bad)",» { XX } },	2533 { Bad_Opcode },

2154 { "(bad)",» { XX } },	2534 { Bad_Opcode },

2155 { "(bad)",» { XX } },	2535 { Bad_Opcode },

2156 { "(bad)",» { XX } },	2536 { Bad_Opcode },

2157 { "(bad)",» { XX } },	2537 { Bad_Opcode },

2158 { "(bad)",» { XX } },	2538 { MOD_TABLE (MOD_C6_REG_7) },

2159 },	2539 },

2160 /* REG_C7 */	2540 /* REG_C7 */

2161 {	2541 {

2162 { "movQ",» { Ev, Iv } },	2542 { "movQ",» { Evh3, Iv } },

2163 { "(bad)",» { XX } },	2543 { Bad_Opcode },

2164 { "(bad)",» { XX } },	2544 { Bad_Opcode },

2165 { "(bad)",» { XX } },	2545 { Bad_Opcode },

2166 { "(bad)",» { XX } },	2546 { Bad_Opcode },

2167 { "(bad)",» { XX } },	2547 { Bad_Opcode },

2168 { "(bad)",» { XX } },	2548 { Bad_Opcode },

2169 { "(bad)", { XX } },	2549 { MOD_TABLE (MOD_C7_REG_7) },

2170 },	2550 },

2171 /* REG_D0 */	2551 /* REG_D0 */

2172 {	2552 {

2173 { "rolA", { Eb, I1 } },	2553 { "rolA", { Eb, I1 } },

2174 { "rorA", { Eb, I1 } },	2554 { "rorA", { Eb, I1 } },

2175 { "rclA", { Eb, I1 } },	2555 { "rclA", { Eb, I1 } },

2176 { "rcrA", { Eb, I1 } },	2556 { "rcrA", { Eb, I1 } },

2177 { "shlA", { Eb, I1 } },	2557 { "shlA", { Eb, I1 } },

2178 { "shrA", { Eb, I1 } },	2558 { "shrA", { Eb, I1 } },

2179 { "(bad)",» { XX } },	2559 { Bad_Opcode },

2180 { "sarA", { Eb, I1 } },	2560 { "sarA", { Eb, I1 } },

2181 },	2561 },

2182 /* REG_D1 */	2562 /* REG_D1 */

2183 {	2563 {

2184 { "rolQ", { Ev, I1 } },	2564 { "rolQ", { Ev, I1 } },

2185 { "rorQ", { Ev, I1 } },	2565 { "rorQ", { Ev, I1 } },

2186 { "rclQ", { Ev, I1 } },	2566 { "rclQ", { Ev, I1 } },

2187 { "rcrQ", { Ev, I1 } },	2567 { "rcrQ", { Ev, I1 } },

2188 { "shlQ", { Ev, I1 } },	2568 { "shlQ", { Ev, I1 } },

2189 { "shrQ", { Ev, I1 } },	2569 { "shrQ", { Ev, I1 } },

2190 { "(bad)",» { XX } },	2570 { Bad_Opcode },

2191 { "sarQ", { Ev, I1 } },	2571 { "sarQ", { Ev, I1 } },

2192 },	2572 },

2193 /* REG_D2 */	2573 /* REG_D2 */

2194 {	2574 {

2195 { "rolA", { Eb, CL } },	2575 { "rolA", { Eb, CL } },

2196 { "rorA", { Eb, CL } },	2576 { "rorA", { Eb, CL } },

2197 { "rclA", { Eb, CL } },	2577 { "rclA", { Eb, CL } },

2198 { "rcrA", { Eb, CL } },	2578 { "rcrA", { Eb, CL } },

2199 { "shlA", { Eb, CL } },	2579 { "shlA", { Eb, CL } },

2200 { "shrA", { Eb, CL } },	2580 { "shrA", { Eb, CL } },

2201 { "(bad)",» { XX } },	2581 { Bad_Opcode },

2202 { "sarA", { Eb, CL } },	2582 { "sarA", { Eb, CL } },

2203 },	2583 },

2204 /* REG_D3 */	2584 /* REG_D3 */

2205 {	2585 {

2206 { "rolQ", { Ev, CL } },	2586 { "rolQ", { Ev, CL } },

2207 { "rorQ", { Ev, CL } },	2587 { "rorQ", { Ev, CL } },

2208 { "rclQ", { Ev, CL } },	2588 { "rclQ", { Ev, CL } },

2209 { "rcrQ", { Ev, CL } },	2589 { "rcrQ", { Ev, CL } },

2210 { "shlQ", { Ev, CL } },	2590 { "shlQ", { Ev, CL } },

2211 { "shrQ", { Ev, CL } },	2591 { "shrQ", { Ev, CL } },

2212 { "(bad)",» { XX } },	2592 { Bad_Opcode },

2213 { "sarQ", { Ev, CL } },	2593 { "sarQ", { Ev, CL } },

2214 },	2594 },

2215 /* REG_F6 */	2595 /* REG_F6 */

2216 {	2596 {

2217 { "testA", { Eb, Ib } },	2597 { "testA", { Eb, Ib } },

2218 { "(bad)",» { XX } },	2598 { Bad_Opcode },

2219 { "notA",» { Eb } },	2599 { "notA",» { Ebh1 } },

2220 { "negA",» { Eb } },	2600 { "negA",» { Ebh1 } },

2221 { "mulA", { Eb } }, /* Don't print the implicit %al register, */	2601 { "mulA", { Eb } }, /* Don't print the implicit %al register, */

2222 { "imulA", { Eb } }, /* to distinguish these opcodes from other */	2602 { "imulA", { Eb } }, /* to distinguish these opcodes from other */

2223 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */	2603 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */

2224 { "idivA", { Eb } }, /* and idiv for consistency. */	2604 { "idivA", { Eb } }, /* and idiv for consistency. */

2225 },	2605 },

2226 /* REG_F7 */	2606 /* REG_F7 */

2227 {	2607 {

2228 { "testQ", { Ev, Iv } },	2608 { "testQ", { Ev, Iv } },

2229 { "(bad)",» { XX } },	2609 { Bad_Opcode },

2230 { "notQ",» { Ev } },	2610 { "notQ",» { Evh1 } },

2231 { "negQ",» { Ev } },	2611 { "negQ",» { Evh1 } },

2232 { "mulQ", { Ev } }, /* Don't print the implicit register. */	2612 { "mulQ", { Ev } }, /* Don't print the implicit register. */

2233 { "imulQ", { Ev } },	2613 { "imulQ", { Ev } },

2234 { "divQ", { Ev } },	2614 { "divQ", { Ev } },

2235 { "idivQ", { Ev } },	2615 { "idivQ", { Ev } },

2236 },	2616 },

2237 /* REG_FE */	2617 /* REG_FE */

2238 {	2618 {

2239 { "incA",» { Eb } },	2619 { "incA",» { Ebh1 } },

2240 { "decA",» { Eb } },	2620 { "decA",» { Ebh1 } },

2241 { "(bad)",» { XX } },

2242 { "(bad)",» { XX } },

2243 { "(bad)",» { XX } },

2244 { "(bad)",» { XX } },

2245 { "(bad)",» { XX } },

2246 { "(bad)",» { XX } },

2247 },	2621 },

2248 /* REG_FF */	2622 /* REG_FF */

2249 {	2623 {

2250 { "incQ",» { Ev } },	2624 { "incQ",» { Evh1 } },

2251 { "decQ",» { Ev } },	2625 { "decQ",» { Evh1 } },

2252 { "callT",» { indirEv } },	2626 { "call{T\|}", { indirEv } },

2253 { "JcallT",»{ indirEp } },	2627 { "Jcall{T\|}", { indirEp } },

2254 { "jmpT",» { indirEv } },	2628 { "jmp{T\|}", { indirEv } },

2255 { "JjmpT",» { indirEp } },	2629 { "Jjmp{T\|}", { indirEp } },

2256 { "pushU", { stackEv } },	2630 { "pushU", { stackEv } },

2257 { "(bad)",» { XX } },	2631 { Bad_Opcode },

2258 },	2632 },

2259 /* REG_0F00 */	2633 /* REG_0F00 */

2260 {	2634 {

2261 { "sldtD", { Sv } },	2635 { "sldtD", { Sv } },

2262 { "strD", { Sv } },	2636 { "strD", { Sv } },

2263 { "lldt", { Ew } },	2637 { "lldt", { Ew } },

2264 { "ltr", { Ew } },	2638 { "ltr", { Ew } },

2265 { "verr", { Ew } },	2639 { "verr", { Ew } },

2266 { "verw", { Ew } },	2640 { "verw", { Ew } },

2267 { "(bad)",» { XX } },	2641 { Bad_Opcode },

2268 { "(bad)",» { XX } },	2642 { Bad_Opcode },

2269 },	2643 },

2270 /* REG_0F01 */	2644 /* REG_0F01 */

2271 {	2645 {

2272 { MOD_TABLE (MOD_0F01_REG_0) },	2646 { MOD_TABLE (MOD_0F01_REG_0) },

2273 { MOD_TABLE (MOD_0F01_REG_1) },	2647 { MOD_TABLE (MOD_0F01_REG_1) },

2274 { MOD_TABLE (MOD_0F01_REG_2) },	2648 { MOD_TABLE (MOD_0F01_REG_2) },

2275 { MOD_TABLE (MOD_0F01_REG_3) },	2649 { MOD_TABLE (MOD_0F01_REG_3) },

2276 { "smswD", { Sv } },	2650 { "smswD", { Sv } },

2277 { "(bad)",» { XX } },	2651 { Bad_Opcode },

2278 { "lmsw", { Ew } },	2652 { "lmsw", { Ew } },

2279 { MOD_TABLE (MOD_0F01_REG_7) },	2653 { MOD_TABLE (MOD_0F01_REG_7) },

2280 },	2654 },

2281 /* REG_0F0D */	2655 /* REG_0F0D */

2282 {	2656 {

2283 { "prefetch",» { Eb } },	2657 { "prefetch",» { Mb } },

2284 { "prefetchw",» { Eb } },	2658 { "prefetchw",» { Mb } },

2285 { "(bad)",» » { XX } },	2659 { "prefetch",» { Mb } },

2286 { "(bad)",» » { XX } },	2660 { "prefetch",» { Mb } },

2287 { "(bad)",» » { XX } },	2661 { "prefetch",» { Mb } },

2288 { "(bad)",» » { XX } },	2662 { "prefetch",» { Mb } },

2289 { "(bad)",» » { XX } },	2663 { "prefetch",» { Mb } },

2290 { "(bad)",» » { XX } },	2664 { "prefetch",» { Mb } },

2291 },	2665 },

2292 /* REG_0F18 */	2666 /* REG_0F18 */

2293 {	2667 {

2294 { MOD_TABLE (MOD_0F18_REG_0) },	2668 { MOD_TABLE (MOD_0F18_REG_0) },

2295 { MOD_TABLE (MOD_0F18_REG_1) },	2669 { MOD_TABLE (MOD_0F18_REG_1) },

2296 { MOD_TABLE (MOD_0F18_REG_2) },	2670 { MOD_TABLE (MOD_0F18_REG_2) },

2297 { MOD_TABLE (MOD_0F18_REG_3) },	2671 { MOD_TABLE (MOD_0F18_REG_3) },

2298 { "(bad)",» { XX } },	2672 { MOD_TABLE (MOD_0F18_REG_4) },

2299 { "(bad)",» { XX } },	2673 { MOD_TABLE (MOD_0F18_REG_5) },

2300 { "(bad)",» { XX } },	2674 { MOD_TABLE (MOD_0F18_REG_6) },

2301 { "(bad)",» { XX } },	2675 { MOD_TABLE (MOD_0F18_REG_7) },

2302 },	2676 },

2303 /* REG_0F71 */	2677 /* REG_0F71 */

2304 {	2678 {

2305 { "(bad)",» { XX } },	2679 { Bad_Opcode },

2306 { "(bad)",» { XX } },	2680 { Bad_Opcode },

2307 { MOD_TABLE (MOD_0F71_REG_2) },	2681 { MOD_TABLE (MOD_0F71_REG_2) },

2308 { "(bad)",» { XX } },	2682 { Bad_Opcode },

2309 { MOD_TABLE (MOD_0F71_REG_4) },	2683 { MOD_TABLE (MOD_0F71_REG_4) },

2310 { "(bad)",» { XX } },	2684 { Bad_Opcode },

2311 { MOD_TABLE (MOD_0F71_REG_6) },	2685 { MOD_TABLE (MOD_0F71_REG_6) },

2312 { "(bad)", { XX } },

2313 },	2686 },

2314 /* REG_0F72 */	2687 /* REG_0F72 */

2315 {	2688 {

2316 { "(bad)",» { XX } },	2689 { Bad_Opcode },

2317 { "(bad)",» { XX } },	2690 { Bad_Opcode },

2318 { MOD_TABLE (MOD_0F72_REG_2) },	2691 { MOD_TABLE (MOD_0F72_REG_2) },

2319 { "(bad)",» { XX } },	2692 { Bad_Opcode },

2320 { MOD_TABLE (MOD_0F72_REG_4) },	2693 { MOD_TABLE (MOD_0F72_REG_4) },

2321 { "(bad)",» { XX } },	2694 { Bad_Opcode },

2322 { MOD_TABLE (MOD_0F72_REG_6) },	2695 { MOD_TABLE (MOD_0F72_REG_6) },

2323 { "(bad)", { XX } },

2324 },	2696 },

2325 /* REG_0F73 */	2697 /* REG_0F73 */

2326 {	2698 {

2327 { "(bad)",» { XX } },	2699 { Bad_Opcode },

2328 { "(bad)",» { XX } },	2700 { Bad_Opcode },

2329 { MOD_TABLE (MOD_0F73_REG_2) },	2701 { MOD_TABLE (MOD_0F73_REG_2) },

2330 { MOD_TABLE (MOD_0F73_REG_3) },	2702 { MOD_TABLE (MOD_0F73_REG_3) },

2331 { "(bad)",» { XX } },	2703 { Bad_Opcode },

2332 { "(bad)",» { XX } },	2704 { Bad_Opcode },

2333 { MOD_TABLE (MOD_0F73_REG_6) },	2705 { MOD_TABLE (MOD_0F73_REG_6) },

2334 { MOD_TABLE (MOD_0F73_REG_7) },	2706 { MOD_TABLE (MOD_0F73_REG_7) },

2335 },	2707 },

2336 /* REG_0FA6 */	2708 /* REG_0FA6 */

2337 {	2709 {

2338 { "montmul", { { OP_0f07, 0 } } },	2710 { "montmul", { { OP_0f07, 0 } } },

2339 { "xsha1", { { OP_0f07, 0 } } },	2711 { "xsha1", { { OP_0f07, 0 } } },

2340 { "xsha256", { { OP_0f07, 0 } } },	2712 { "xsha256", { { OP_0f07, 0 } } },

2341 { "(bad)", { { OP_0f07, 0 } } },

2342 { "(bad)", { { OP_0f07, 0 } } },

2343 { "(bad)", { { OP_0f07, 0 } } },

2344 { "(bad)", { { OP_0f07, 0 } } },

2345 { "(bad)", { { OP_0f07, 0 } } },

2346 },	2713 },

2347 /* REG_0FA7 */	2714 /* REG_0FA7 */

2348 {	2715 {

2349 { "xstore-rng", { { OP_0f07, 0 } } },	2716 { "xstore-rng", { { OP_0f07, 0 } } },

2350 { "xcrypt-ecb", { { OP_0f07, 0 } } },	2717 { "xcrypt-ecb", { { OP_0f07, 0 } } },

2351 { "xcrypt-cbc", { { OP_0f07, 0 } } },	2718 { "xcrypt-cbc", { { OP_0f07, 0 } } },

2352 { "xcrypt-ctr", { { OP_0f07, 0 } } },	2719 { "xcrypt-ctr", { { OP_0f07, 0 } } },

2353 { "xcrypt-cfb", { { OP_0f07, 0 } } },	2720 { "xcrypt-cfb", { { OP_0f07, 0 } } },

2354 { "xcrypt-ofb", { { OP_0f07, 0 } } },	2721 { "xcrypt-ofb", { { OP_0f07, 0 } } },

2355 { "(bad)", { { OP_0f07, 0 } } },

2356 { "(bad)", { { OP_0f07, 0 } } },

2357 },	2722 },

2358 /* REG_0FAE */	2723 /* REG_0FAE */

2359 {	2724 {

2360 { MOD_TABLE (MOD_0FAE_REG_0) },	2725 { MOD_TABLE (MOD_0FAE_REG_0) },

2361 { MOD_TABLE (MOD_0FAE_REG_1) },	2726 { MOD_TABLE (MOD_0FAE_REG_1) },

2362 { MOD_TABLE (MOD_0FAE_REG_2) },	2727 { MOD_TABLE (MOD_0FAE_REG_2) },

2363 { MOD_TABLE (MOD_0FAE_REG_3) },	2728 { MOD_TABLE (MOD_0FAE_REG_3) },

2364 { MOD_TABLE (MOD_0FAE_REG_4) },	2729 { MOD_TABLE (MOD_0FAE_REG_4) },

2365 { MOD_TABLE (MOD_0FAE_REG_5) },	2730 { MOD_TABLE (MOD_0FAE_REG_5) },

2366 { MOD_TABLE (MOD_0FAE_REG_6) },	2731 { MOD_TABLE (MOD_0FAE_REG_6) },

2367 { MOD_TABLE (MOD_0FAE_REG_7) },	2732 { MOD_TABLE (MOD_0FAE_REG_7) },

2368 },	2733 },

2369 /* REG_0FBA */	2734 /* REG_0FBA */

2370 {	2735 {

2371 { "(bad)",» { XX } },	2736 { Bad_Opcode },

2372 { "(bad)",» { XX } },	2737 { Bad_Opcode },

2373 { "(bad)",» { XX } },	2738 { Bad_Opcode },

2374 { "(bad)",» { XX } },	2739 { Bad_Opcode },

2375 { "btQ", { Ev, Ib } },	2740 { "btQ", { Ev, Ib } },

2376 { "btsQ",» { Ev, Ib } },	2741 { "btsQ",» { Evh1, Ib } },

2377 { "btrQ",» { Ev, Ib } },	2742 { "btrQ",» { Evh1, Ib } },

2378 { "btcQ",» { Ev, Ib } },	2743 { "btcQ",» { Evh1, Ib } },

2379 },	2744 },

2380 /* REG_0FC7 */	2745 /* REG_0FC7 */

2381 {	2746 {

2382 { "(bad)",» { XX } },	2747 { Bad_Opcode },

2383 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },	2748 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },

2384 { "(bad)",» { XX } },	2749 { Bad_Opcode },

2385 { "(bad)",» { XX } },	2750 { Bad_Opcode },

2386 { "(bad)",» { XX } },	2751 { Bad_Opcode },

2387 { "(bad)",» { XX } },	2752 { Bad_Opcode },

2388 { MOD_TABLE (MOD_0FC7_REG_6) },	2753 { MOD_TABLE (MOD_0FC7_REG_6) },

2389 { MOD_TABLE (MOD_0FC7_REG_7) },	2754 { MOD_TABLE (MOD_0FC7_REG_7) },

2390 },	2755 },

2391 /* REG_VEX_71 */	2756 /* REG_VEX_0F71 */

2392 {	2757 {

2393 { "(bad)",» { XX } },	2758 { Bad_Opcode },

2394 { "(bad)",» { XX } },	2759 { Bad_Opcode },

2395 { MOD_TABLE (MOD_VEX_71_REG_2) },	2760 { MOD_TABLE (MOD_VEX_0F71_REG_2) },

2396 { "(bad)",» { XX } },	2761 { Bad_Opcode },

2397 { MOD_TABLE (MOD_VEX_71_REG_4) },	2762 { MOD_TABLE (MOD_VEX_0F71_REG_4) },

2398 { "(bad)",» { XX } },	2763 { Bad_Opcode },

2399 { MOD_TABLE (MOD_VEX_71_REG_6) },	2764 { MOD_TABLE (MOD_VEX_0F71_REG_6) },

2400 { "(bad)",» { XX } },

2401 },	2765 },

2402 /* REG_VEX_72 */	2766 /* REG_VEX_0F72 */

2403 {	2767 {

2404 { "(bad)",» { XX } },	2768 { Bad_Opcode },

2405 { "(bad)",» { XX } },	2769 { Bad_Opcode },

2406 { MOD_TABLE (MOD_VEX_72_REG_2) },	2770 { MOD_TABLE (MOD_VEX_0F72_REG_2) },

2407 { "(bad)",» { XX } },	2771 { Bad_Opcode },

2408 { MOD_TABLE (MOD_VEX_72_REG_4) },	2772 { MOD_TABLE (MOD_VEX_0F72_REG_4) },

2409 { "(bad)",» { XX } },	2773 { Bad_Opcode },

2410 { MOD_TABLE (MOD_VEX_72_REG_6) },	2774 { MOD_TABLE (MOD_VEX_0F72_REG_6) },

2411 { "(bad)",» { XX } },

2412 },	2775 },

2413 /* REG_VEX_73 */	2776 /* REG_VEX_0F73 */

2414 {	2777 {

2415 { "(bad)",» { XX } },	2778 { Bad_Opcode },

2416 { "(bad)",» { XX } },	2779 { Bad_Opcode },

2417 { MOD_TABLE (MOD_VEX_73_REG_2) },	2780 { MOD_TABLE (MOD_VEX_0F73_REG_2) },

2418 { MOD_TABLE (MOD_VEX_73_REG_3) },	2781 { MOD_TABLE (MOD_VEX_0F73_REG_3) },

2419 { "(bad)",» { XX } },	2782 { Bad_Opcode },

2420 { "(bad)",» { XX } },	2783 { Bad_Opcode },

2421 { MOD_TABLE (MOD_VEX_73_REG_6) },	2784 { MOD_TABLE (MOD_VEX_0F73_REG_6) },

2422 { MOD_TABLE (MOD_VEX_73_REG_7) },	2785 { MOD_TABLE (MOD_VEX_0F73_REG_7) },

2423 },	2786 },

2424 /* REG_VEX_AE */	2787 /* REG_VEX_0FAE */

2425 {	2788 {

2426 { "(bad)",» { XX } },	2789 { Bad_Opcode },

2427 { "(bad)",» { XX } },	2790 { Bad_Opcode },

2428 { MOD_TABLE (MOD_VEX_AE_REG_2) },	2791 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },

2429 { MOD_TABLE (MOD_VEX_AE_REG_3) },	2792 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },

2430 { "(bad)",» { XX } },	2793 },

2431 { "(bad)",» { XX } },	2794 /* REG_VEX_0F38F3 */

2432 { "(bad)",» { XX } },	2795 {

2433 { "(bad)",» { XX } },	2796 { Bad_Opcode },

	2797 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },

	2798 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },

	2799 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },

	2800 },

	2801 /* REG_XOP_LWPCB */

	2802 {

	2803 { "llwpcb", { { OP_LWPCB_E, 0 } } },

	2804 { "slwpcb",»{ { OP_LWPCB_E, 0 } } },

	2805 },

	2806 /* REG_XOP_LWP */

	2807 {

	2808 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },

	2809 { "lwpval",»{ { OP_LWP_E, 0 }, Ed, Iq } },

	2810 },

	2811 /* REG_XOP_TBM_01 */

	2812 {

	2813 { Bad_Opcode },

	2814 { "blcfill",» { { OP_LWP_E, 0 }, Ev } },

	2815 { "blsfill",» { { OP_LWP_E, 0 }, Ev } },

	2816 { "blcs",» { { OP_LWP_E, 0 }, Ev } },

	2817 { "tzmsk",» { { OP_LWP_E, 0 }, Ev } },

	2818 { "blcic",» { { OP_LWP_E, 0 }, Ev } },

	2819 { "blsic",» { { OP_LWP_E, 0 }, Ev } },

	2820 { "t1mskc",»{ { OP_LWP_E, 0 }, Ev } },

	2821 },

	2822 /* REG_XOP_TBM_02 */

	2823 {

	2824 { Bad_Opcode },

	2825 { "blcmsk",»{ { OP_LWP_E, 0 }, Ev } },

	2826 { Bad_Opcode },

	2827 { Bad_Opcode },

	2828 { Bad_Opcode },

	2829 { Bad_Opcode },

	2830 { "blci",» { { OP_LWP_E, 0 }, Ev } },

2434 },	2831 },

2435 };	2832 };

2436	2833

2437 static const struct dis386 prefix_table[][4] = {	2834 static const struct dis386 prefix_table[][4] = {

2438 /* PREFIX_90 */	2835 /* PREFIX_90 */

2439 {	2836 {

2440 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },	2837 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },

2441 { "pause", { XX } },	2838 { "pause", { XX } },

2442 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },	2839 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },

2443 { "(bad)", { XX } },

2444 },	2840 },

2445	2841

2446 /* PREFIX_0F10 */	2842 /* PREFIX_0F10 */

2447 {	2843 {

2448 { "movups", { XM, EXx } },	2844 { "movups", { XM, EXx } },

2449 { "movss", { XM, EXd } },	2845 { "movss", { XM, EXd } },

2450 { "movupd", { XM, EXx } },	2846 { "movupd", { XM, EXx } },

2451 { "movsd", { XM, EXq } },	2847 { "movsd", { XM, EXq } },

2452 },	2848 },

2453	2849

(...skipping 11 matching lines...) Expand all Loading...
2465 { "movsldup", { XM, EXx } },	2861 { "movsldup", { XM, EXx } },

2466 { "movlpd", { XM, EXq } },	2862 { "movlpd", { XM, EXq } },

2467 { "movddup", { XM, EXq } },	2863 { "movddup", { XM, EXq } },

2468 },	2864 },

2469	2865

2470 /* PREFIX_0F16 */	2866 /* PREFIX_0F16 */

2471 {	2867 {

2472 { MOD_TABLE (MOD_0F16_PREFIX_0) },	2868 { MOD_TABLE (MOD_0F16_PREFIX_0) },

2473 { "movshdup", { XM, EXx } },	2869 { "movshdup", { XM, EXx } },

2474 { "movhpd", { XM, EXq } },	2870 { "movhpd", { XM, EXq } },

2475 { "(bad)", { XX } },

2476 },	2871 },

2477	2872

2478 /* PREFIX_0F2A */	2873 /* PREFIX_0F2A */

2479 {	2874 {

2480 { "cvtpi2ps", { XM, EMCq } },	2875 { "cvtpi2ps", { XM, EMCq } },

2481 { "cvtsi2ss%LQ", { XM, Ev } },	2876 { "cvtsi2ss%LQ", { XM, Ev } },

2482 { "cvtpi2pd", { XM, EMCq } },	2877 { "cvtpi2pd", { XM, EMCq } },

2483 { "cvtsi2sd%LQ", { XM, Ev } },	2878 { "cvtsi2sd%LQ", { XM, Ev } },

2484 },	2879 },

2485	2880

(...skipping 17 matching lines...) Expand all Loading...
2503 {	2898 {

2504 { "cvtps2pi", { MXC, EXq } },	2899 { "cvtps2pi", { MXC, EXq } },

2505 { "cvtss2siY", { Gv, EXd } },	2900 { "cvtss2siY", { Gv, EXd } },

2506 { "cvtpd2pi", { MXC, EXx } },	2901 { "cvtpd2pi", { MXC, EXx } },

2507 { "cvtsd2siY", { Gv, EXq } },	2902 { "cvtsd2siY", { Gv, EXq } },

2508 },	2903 },

2509	2904

2510 /* PREFIX_0F2E */	2905 /* PREFIX_0F2E */

2511 {	2906 {

2512 { "ucomiss",{ XM, EXd } },	2907 { "ucomiss",{ XM, EXd } },

2513 { "(bad)",» { XX } },	2908 { Bad_Opcode },

2514 { "ucomisd",{ XM, EXq } },	2909 { "ucomisd",{ XM, EXq } },

2515 { "(bad)", { XX } },

2516 },	2910 },

2517	2911

2518 /* PREFIX_0F2F */	2912 /* PREFIX_0F2F */

2519 {	2913 {

2520 { "comiss", { XM, EXd } },	2914 { "comiss", { XM, EXd } },

2521 { "(bad)",» { XX } },	2915 { Bad_Opcode },

2522 { "comisd", { XM, EXq } },	2916 { "comisd", { XM, EXq } },

2523 { "(bad)", { XX } },

2524 },	2917 },

2525	2918

2526 /* PREFIX_0F51 */	2919 /* PREFIX_0F51 */

2527 {	2920 {

2528 { "sqrtps", { XM, EXx } },	2921 { "sqrtps", { XM, EXx } },

2529 { "sqrtss", { XM, EXd } },	2922 { "sqrtss", { XM, EXd } },

2530 { "sqrtpd", { XM, EXx } },	2923 { "sqrtpd", { XM, EXx } },

2531 { "sqrtsd", { XM, EXq } },	2924 { "sqrtsd", { XM, EXq } },

2532 },	2925 },

2533	2926

2534 /* PREFIX_0F52 */	2927 /* PREFIX_0F52 */

2535 {	2928 {

2536 { "rsqrtps",{ XM, EXx } },	2929 { "rsqrtps",{ XM, EXx } },

2537 { "rsqrtss",{ XM, EXd } },	2930 { "rsqrtss",{ XM, EXd } },

2538 { "(bad)", { XX } },

2539 { "(bad)", { XX } },

2540 },	2931 },

2541	2932

2542 /* PREFIX_0F53 */	2933 /* PREFIX_0F53 */

2543 {	2934 {

2544 { "rcpps", { XM, EXx } },	2935 { "rcpps", { XM, EXx } },

2545 { "rcpss", { XM, EXd } },	2936 { "rcpss", { XM, EXd } },

2546 { "(bad)", { XX } },

2547 { "(bad)", { XX } },

2548 },	2937 },

2549	2938

2550 /* PREFIX_0F58 */	2939 /* PREFIX_0F58 */

2551 {	2940 {

2552 { "addps", { XM, EXx } },	2941 { "addps", { XM, EXx } },

2553 { "addss", { XM, EXd } },	2942 { "addss", { XM, EXd } },

2554 { "addpd", { XM, EXx } },	2943 { "addpd", { XM, EXx } },

2555 { "addsd", { XM, EXq } },	2944 { "addsd", { XM, EXq } },

2556 },	2945 },

2557	2946

(...skipping 11 matching lines...) Expand all Loading...
2569 { "cvtss2sd", { XM, EXd } },	2958 { "cvtss2sd", { XM, EXd } },

2570 { "cvtpd2ps", { XM, EXx } },	2959 { "cvtpd2ps", { XM, EXx } },

2571 { "cvtsd2ss", { XM, EXq } },	2960 { "cvtsd2ss", { XM, EXq } },

2572 },	2961 },

2573	2962

2574 /* PREFIX_0F5B */	2963 /* PREFIX_0F5B */

2575 {	2964 {

2576 { "cvtdq2ps", { XM, EXx } },	2965 { "cvtdq2ps", { XM, EXx } },

2577 { "cvttps2dq", { XM, EXx } },	2966 { "cvttps2dq", { XM, EXx } },

2578 { "cvtps2dq", { XM, EXx } },	2967 { "cvtps2dq", { XM, EXx } },

2579 { "(bad)", { XX } },

2580 },	2968 },

2581	2969

2582 /* PREFIX_0F5C */	2970 /* PREFIX_0F5C */

2583 {	2971 {

2584 { "subps", { XM, EXx } },	2972 { "subps", { XM, EXx } },

2585 { "subss", { XM, EXd } },	2973 { "subss", { XM, EXd } },

2586 { "subpd", { XM, EXx } },	2974 { "subpd", { XM, EXx } },

2587 { "subsd", { XM, EXq } },	2975 { "subsd", { XM, EXq } },

2588 },	2976 },

2589	2977

(...skipping 17 matching lines...) Expand all Loading...
2607 {	2995 {

2608 { "maxps", { XM, EXx } },	2996 { "maxps", { XM, EXx } },

2609 { "maxss", { XM, EXd } },	2997 { "maxss", { XM, EXd } },

2610 { "maxpd", { XM, EXx } },	2998 { "maxpd", { XM, EXx } },

2611 { "maxsd", { XM, EXq } },	2999 { "maxsd", { XM, EXq } },

2612 },	3000 },

2613	3001

2614 /* PREFIX_0F60 */	3002 /* PREFIX_0F60 */

2615 {	3003 {

2616 { "punpcklbw",{ MX, EMd } },	3004 { "punpcklbw",{ MX, EMd } },

2617 { "(bad)",» { XX } },	3005 { Bad_Opcode },

2618 { "punpcklbw",{ MX, EMx } },	3006 { "punpcklbw",{ MX, EMx } },

2619 { "(bad)", { XX } },

2620 },	3007 },

2621	3008

2622 /* PREFIX_0F61 */	3009 /* PREFIX_0F61 */

2623 {	3010 {

2624 { "punpcklwd",{ MX, EMd } },	3011 { "punpcklwd",{ MX, EMd } },

2625 { "(bad)",» { XX } },	3012 { Bad_Opcode },

2626 { "punpcklwd",{ MX, EMx } },	3013 { "punpcklwd",{ MX, EMx } },

2627 { "(bad)", { XX } },

2628 },	3014 },

2629	3015

2630 /* PREFIX_0F62 */	3016 /* PREFIX_0F62 */

2631 {	3017 {

2632 { "punpckldq",{ MX, EMd } },	3018 { "punpckldq",{ MX, EMd } },

2633 { "(bad)",» { XX } },	3019 { Bad_Opcode },

2634 { "punpckldq",{ MX, EMx } },	3020 { "punpckldq",{ MX, EMx } },

2635 { "(bad)", { XX } },

2636 },	3021 },

2637	3022

2638 /* PREFIX_0F6C */	3023 /* PREFIX_0F6C */

2639 {	3024 {

2640 { "(bad)",» { XX } },	3025 { Bad_Opcode },

2641 { "(bad)",» { XX } },	3026 { Bad_Opcode },

2642 { "punpcklqdq", { XM, EXx } },	3027 { "punpcklqdq", { XM, EXx } },

2643 { "(bad)", { XX } },

2644 },	3028 },

2645	3029

2646 /* PREFIX_0F6D */	3030 /* PREFIX_0F6D */

2647 {	3031 {

2648 { "(bad)",» { XX } },	3032 { Bad_Opcode },

2649 { "(bad)",» { XX } },	3033 { Bad_Opcode },

2650 { "punpckhqdq", { XM, EXx } },	3034 { "punpckhqdq", { XM, EXx } },

2651 { "(bad)", { XX } },

2652 },	3035 },

2653	3036

2654 /* PREFIX_0F6F */	3037 /* PREFIX_0F6F */

2655 {	3038 {

2656 { "movq", { MX, EM } },	3039 { "movq", { MX, EM } },

2657 { "movdqu", { XM, EXx } },	3040 { "movdqu", { XM, EXx } },

2658 { "movdqa", { XM, EXx } },	3041 { "movdqa", { XM, EXx } },

2659 { "(bad)", { XX } },

2660 },	3042 },

2661	3043

2662 /* PREFIX_0F70 */	3044 /* PREFIX_0F70 */

2663 {	3045 {

2664 { "pshufw", { MX, EM, Ib } },	3046 { "pshufw", { MX, EM, Ib } },

2665 { "pshufhw",{ XM, EXx, Ib } },	3047 { "pshufhw",{ XM, EXx, Ib } },

2666 { "pshufd", { XM, EXx, Ib } },	3048 { "pshufd", { XM, EXx, Ib } },

2667 { "pshuflw",{ XM, EXx, Ib } },	3049 { "pshuflw",{ XM, EXx, Ib } },

2668 },	3050 },

2669	3051

2670 /* PREFIX_0F73_REG_3 */	3052 /* PREFIX_0F73_REG_3 */

2671 {	3053 {

2672 { "(bad)",» { XX } },	3054 { Bad_Opcode },

2673 { "(bad)",» { XX } },	3055 { Bad_Opcode },

2674 { "psrldq", { XS, Ib } },	3056 { "psrldq", { XS, Ib } },

2675 { "(bad)", { XX } },

2676 },	3057 },

2677	3058

2678 /* PREFIX_0F73_REG_7 */	3059 /* PREFIX_0F73_REG_7 */

2679 {	3060 {

2680 { "(bad)",» { XX } },	3061 { Bad_Opcode },

2681 { "(bad)",» { XX } },	3062 { Bad_Opcode },

2682 { "pslldq", { XS, Ib } },	3063 { "pslldq", { XS, Ib } },

2683 { "(bad)", { XX } },

2684 },	3064 },

2685	3065

2686 /* PREFIX_0F78 */	3066 /* PREFIX_0F78 */

2687 {	3067 {

2688 {"vmread", { Em, Gm } },	3068 {"vmread", { Em, Gm } },

2689 {"(bad)",» { XX } },	3069 { Bad_Opcode },

2690 {"extrq", { XS, Ib, Ib } },	3070 {"extrq", { XS, Ib, Ib } },

2691 {"insertq", { XM, XS, Ib, Ib } },	3071 {"insertq", { XM, XS, Ib, Ib } },

2692 },	3072 },

2693	3073

2694 /* PREFIX_0F79 */	3074 /* PREFIX_0F79 */

2695 {	3075 {

2696 {"vmwrite", { Gm, Em } },	3076 {"vmwrite", { Gm, Em } },

2697 {"(bad)",» { XX } },	3077 { Bad_Opcode },

2698 {"extrq", { XM, XS } },	3078 {"extrq", { XM, XS } },

2699 {"insertq", { XM, XS } },	3079 {"insertq", { XM, XS } },

2700 },	3080 },

2701	3081

2702 /* PREFIX_0F7C */	3082 /* PREFIX_0F7C */

2703 {	3083 {

2704 { "(bad)",» { XX } },	3084 { Bad_Opcode },

2705 { "(bad)",» { XX } },	3085 { Bad_Opcode },

2706 { "haddpd", { XM, EXx } },	3086 { "haddpd", { XM, EXx } },

2707 { "haddps", { XM, EXx } },	3087 { "haddps", { XM, EXx } },

2708 },	3088 },

2709	3089

2710 /* PREFIX_0F7D */	3090 /* PREFIX_0F7D */

2711 {	3091 {

2712 { "(bad)",» { XX } },	3092 { Bad_Opcode },

2713 { "(bad)",» { XX } },	3093 { Bad_Opcode },

2714 { "hsubpd", { XM, EXx } },	3094 { "hsubpd", { XM, EXx } },

2715 { "hsubps", { XM, EXx } },	3095 { "hsubps", { XM, EXx } },

2716 },	3096 },

2717	3097

2718 /* PREFIX_0F7E */	3098 /* PREFIX_0F7E */

2719 {	3099 {

2720 { "movK", { Edq, MX } },	3100 { "movK", { Edq, MX } },

2721 { "movq", { XM, EXq } },	3101 { "movq", { XM, EXq } },

2722 { "movK", { Edq, XM } },	3102 { "movK", { Edq, XM } },

2723 { "(bad)", { XX } },

2724 },	3103 },

2725	3104

2726 /* PREFIX_0F7F */	3105 /* PREFIX_0F7F */

2727 {	3106 {

2728 { "movq", { EMS, MX } },	3107 { "movq", { EMS, MX } },

2729 { "movdqu", { EXxS, XM } },	3108 { "movdqu", { EXxS, XM } },

2730 { "movdqa", { EXxS, XM } },	3109 { "movdqa", { EXxS, XM } },

2731 { "(bad)",» { XX } },	3110 },

	3111

	3112 /* PREFIX_0FAE_REG_0 */

	3113 {

	3114 { Bad_Opcode },

	3115 { "rdfsbase", { Ev } },

	3116 },

	3117

	3118 /* PREFIX_0FAE_REG_1 */

	3119 {

	3120 { Bad_Opcode },

	3121 { "rdgsbase", { Ev } },

	3122 },

	3123

	3124 /* PREFIX_0FAE_REG_2 */

	3125 {

	3126 { Bad_Opcode },

	3127 { "wrfsbase", { Ev } },

	3128 },

	3129

	3130 /* PREFIX_0FAE_REG_3 */

	3131 {

	3132 { Bad_Opcode },

	3133 { "wrgsbase", { Ev } },

2732 },	3134 },

2733	3135

2734 /* PREFIX_0FB8 */	3136 /* PREFIX_0FB8 */

2735 {	3137 {

2736 { "(bad)", { XX } },	3138 { Bad_Opcode },

2737 { "popcntS", { Gv, Ev } },	3139 { "popcntS", { Gv, Ev } },

2738 { "(bad)", { XX } },	3140 },

2739 { "(bad)", { XX } },	3141

	3142 /* PREFIX_0FBC */

	3143 {

	3144 { "bsfS",» { Gv, Ev } },

	3145 { "tzcntS",»{ Gv, Ev } },

	3146 { "bsfS",» { Gv, Ev } },

2740 },	3147 },

2741	3148

2742 /* PREFIX_0FBD */	3149 /* PREFIX_0FBD */

2743 {	3150 {

2744 { "bsrS", { Gv, Ev } },	3151 { "bsrS", { Gv, Ev } },

2745 { "lzcntS", { Gv, Ev } },	3152 { "lzcntS", { Gv, Ev } },

2746 { "bsrS", { Gv, Ev } },	3153 { "bsrS", { Gv, Ev } },

2747 { "(bad)", { XX } },

2748 },	3154 },

2749	3155

2750 /* PREFIX_0FC2 */	3156 /* PREFIX_0FC2 */

2751 {	3157 {

2752 { "cmpps", { XM, EXx, CMP } },	3158 { "cmpps", { XM, EXx, CMP } },

2753 { "cmpss", { XM, EXd, CMP } },	3159 { "cmpss", { XM, EXd, CMP } },

2754 { "cmppd", { XM, EXx, CMP } },	3160 { "cmppd", { XM, EXx, CMP } },

2755 { "cmpsd", { XM, EXq, CMP } },	3161 { "cmpsd", { XM, EXq, CMP } },

2756 },	3162 },

2757	3163

2758 /* PREFIX_0FC3 */	3164 /* PREFIX_0FC3 */

2759 {	3165 {

2760 { "movntiS", { Ma, Gv } },	3166 { "movntiS", { Ma, Gv } },

2761 { "(bad)", { XX } },

2762 { "(bad)", { XX } },

2763 { "(bad)", { XX } },

2764 },	3167 },

2765	3168

2766 /* PREFIX_0FC7_REG_6 */	3169 /* PREFIX_0FC7_REG_6 */

2767 {	3170 {

2768 { "vmptrld",{ Mq } },	3171 { "vmptrld",{ Mq } },

2769 { "vmxon", { Mq } },	3172 { "vmxon", { Mq } },

2770 { "vmclear",{ Mq } },	3173 { "vmclear",{ Mq } },

2771 { "(bad)", { XX } },

2772 },	3174 },

2773	3175

2774 /* PREFIX_0FD0 */	3176 /* PREFIX_0FD0 */

2775 {	3177 {

2776 { "(bad)",» { XX } },	3178 { Bad_Opcode },

2777 { "(bad)",» { XX } },	3179 { Bad_Opcode },

2778 { "addsubpd", { XM, EXx } },	3180 { "addsubpd", { XM, EXx } },

2779 { "addsubps", { XM, EXx } },	3181 { "addsubps", { XM, EXx } },

2780 },	3182 },

2781	3183

2782 /* PREFIX_0FD6 */	3184 /* PREFIX_0FD6 */

2783 {	3185 {

2784 { "(bad)",» { XX } },	3186 { Bad_Opcode },

2785 { "movq2dq",{ XM, MS } },	3187 { "movq2dq",{ XM, MS } },

2786 { "movq", { EXqS, XM } },	3188 { "movq", { EXqS, XM } },

2787 { "movdq2q",{ MX, XS } },	3189 { "movdq2q",{ MX, XS } },

2788 },	3190 },

2789	3191

2790 /* PREFIX_0FE6 */	3192 /* PREFIX_0FE6 */

2791 {	3193 {

2792 { "(bad)",» { XX } },	3194 { Bad_Opcode },

2793 { "cvtdq2pd", { XM, EXq } },	3195 { "cvtdq2pd", { XM, EXq } },

2794 { "cvttpd2dq", { XM, EXx } },	3196 { "cvttpd2dq", { XM, EXx } },

2795 { "cvtpd2dq", { XM, EXx } },	3197 { "cvtpd2dq", { XM, EXx } },

2796 },	3198 },

2797	3199

2798 /* PREFIX_0FE7 */	3200 /* PREFIX_0FE7 */

2799 {	3201 {

2800 { "movntq", { Mq, MX } },	3202 { "movntq", { Mq, MX } },

2801 { "(bad)",» { XX } },	3203 { Bad_Opcode },

2802 { MOD_TABLE (MOD_0FE7_PREFIX_2) },	3204 { MOD_TABLE (MOD_0FE7_PREFIX_2) },

2803 { "(bad)", { XX } },

2804 },	3205 },

2805	3206

2806 /* PREFIX_0FF0 */	3207 /* PREFIX_0FF0 */

2807 {	3208 {

2808 { "(bad)",» { XX } },	3209 { Bad_Opcode },

2809 { "(bad)",» { XX } },	3210 { Bad_Opcode },

2810 { "(bad)",» { XX } },	3211 { Bad_Opcode },

2811 { MOD_TABLE (MOD_0FF0_PREFIX_3) },	3212 { MOD_TABLE (MOD_0FF0_PREFIX_3) },

2812 },	3213 },

2813	3214

2814 /* PREFIX_0FF7 */	3215 /* PREFIX_0FF7 */

2815 {	3216 {

2816 { "maskmovq", { MX, MS } },	3217 { "maskmovq", { MX, MS } },

2817 { "(bad)",» { XX } },	3218 { Bad_Opcode },

2818 { "maskmovdqu", { XM, XS } },	3219 { "maskmovdqu", { XM, XS } },

2819 { "(bad)", { XX } },

2820 },	3220 },

2821	3221

2822 /* PREFIX_0F3810 */	3222 /* PREFIX_0F3810 */

2823 {	3223 {

2824 { "(bad)",» { XX } },	3224 { Bad_Opcode },

2825 { "(bad)",» { XX } },	3225 { Bad_Opcode },

2826 { "pblendvb", { XM, EXx, XMM0 } },	3226 { "pblendvb", { XM, EXx, XMM0 } },

2827 { "(bad)", { XX } },

2828 },	3227 },

2829	3228

2830 /* PREFIX_0F3814 */	3229 /* PREFIX_0F3814 */

2831 {	3230 {

2832 { "(bad)",» { XX } },	3231 { Bad_Opcode },

2833 { "(bad)",» { XX } },	3232 { Bad_Opcode },

2834 { "blendvps", { XM, EXx, XMM0 } },	3233 { "blendvps", { XM, EXx, XMM0 } },

2835 { "(bad)", { XX } },

2836 },	3234 },

2837	3235

2838 /* PREFIX_0F3815 */	3236 /* PREFIX_0F3815 */

2839 {	3237 {

2840 { "(bad)",» { XX } },	3238 { Bad_Opcode },

2841 { "(bad)",» { XX } },	3239 { Bad_Opcode },

2842 { "blendvpd", { XM, EXx, XMM0 } },	3240 { "blendvpd", { XM, EXx, XMM0 } },

2843 { "(bad)", { XX } },

2844 },	3241 },

2845	3242

2846 /* PREFIX_0F3817 */	3243 /* PREFIX_0F3817 */

2847 {	3244 {

2848 { "(bad)",» { XX } },	3245 { Bad_Opcode },

2849 { "(bad)",» { XX } },	3246 { Bad_Opcode },

2850 { "ptest", { XM, EXx } },	3247 { "ptest", { XM, EXx } },

2851 { "(bad)", { XX } },

2852 },	3248 },

2853	3249

2854 /* PREFIX_0F3820 */	3250 /* PREFIX_0F3820 */

2855 {	3251 {

2856 { "(bad)",» { XX } },	3252 { Bad_Opcode },

2857 { "(bad)",» { XX } },	3253 { Bad_Opcode },

2858 { "pmovsxbw", { XM, EXq } },	3254 { "pmovsxbw", { XM, EXq } },

2859 { "(bad)", { XX } },

2860 },	3255 },

2861	3256

2862 /* PREFIX_0F3821 */	3257 /* PREFIX_0F3821 */

2863 {	3258 {

2864 { "(bad)",» { XX } },	3259 { Bad_Opcode },

2865 { "(bad)",» { XX } },	3260 { Bad_Opcode },

2866 { "pmovsxbd", { XM, EXd } },	3261 { "pmovsxbd", { XM, EXd } },

2867 { "(bad)", { XX } },

2868 },	3262 },

2869	3263

2870 /* PREFIX_0F3822 */	3264 /* PREFIX_0F3822 */

2871 {	3265 {

2872 { "(bad)",» { XX } },	3266 { Bad_Opcode },

2873 { "(bad)",» { XX } },	3267 { Bad_Opcode },

2874 { "pmovsxbq", { XM, EXw } },	3268 { "pmovsxbq", { XM, EXw } },

2875 { "(bad)", { XX } },

2876 },	3269 },

2877	3270

2878 /* PREFIX_0F3823 */	3271 /* PREFIX_0F3823 */

2879 {	3272 {

2880 { "(bad)",» { XX } },	3273 { Bad_Opcode },

2881 { "(bad)",» { XX } },	3274 { Bad_Opcode },

2882 { "pmovsxwd", { XM, EXq } },	3275 { "pmovsxwd", { XM, EXq } },

2883 { "(bad)", { XX } },

2884 },	3276 },

2885	3277

2886 /* PREFIX_0F3824 */	3278 /* PREFIX_0F3824 */

2887 {	3279 {

2888 { "(bad)",» { XX } },	3280 { Bad_Opcode },

2889 { "(bad)",» { XX } },	3281 { Bad_Opcode },

2890 { "pmovsxwq", { XM, EXd } },	3282 { "pmovsxwq", { XM, EXd } },

2891 { "(bad)", { XX } },

2892 },	3283 },

2893	3284

2894 /* PREFIX_0F3825 */	3285 /* PREFIX_0F3825 */

2895 {	3286 {

2896 { "(bad)",» { XX } },	3287 { Bad_Opcode },

2897 { "(bad)",» { XX } },	3288 { Bad_Opcode },

2898 { "pmovsxdq", { XM, EXq } },	3289 { "pmovsxdq", { XM, EXq } },

2899 { "(bad)", { XX } },

2900 },	3290 },

2901	3291

2902 /* PREFIX_0F3828 */	3292 /* PREFIX_0F3828 */

2903 {	3293 {

2904 { "(bad)",» { XX } },	3294 { Bad_Opcode },

2905 { "(bad)",» { XX } },	3295 { Bad_Opcode },

2906 { "pmuldq", { XM, EXx } },	3296 { "pmuldq", { XM, EXx } },

2907 { "(bad)", { XX } },

2908 },	3297 },

2909	3298

2910 /* PREFIX_0F3829 */	3299 /* PREFIX_0F3829 */

2911 {	3300 {

2912 { "(bad)",» { XX } },	3301 { Bad_Opcode },

2913 { "(bad)",» { XX } },	3302 { Bad_Opcode },

2914 { "pcmpeqq", { XM, EXx } },	3303 { "pcmpeqq", { XM, EXx } },

2915 { "(bad)", { XX } },

2916 },	3304 },

2917	3305

2918 /* PREFIX_0F382A */	3306 /* PREFIX_0F382A */

2919 {	3307 {

2920 { "(bad)",» { XX } },	3308 { Bad_Opcode },

2921 { "(bad)",» { XX } },	3309 { Bad_Opcode },

2922 { MOD_TABLE (MOD_0F382A_PREFIX_2) },	3310 { MOD_TABLE (MOD_0F382A_PREFIX_2) },

2923 { "(bad)", { XX } },

2924 },	3311 },

2925	3312

2926 /* PREFIX_0F382B */	3313 /* PREFIX_0F382B */

2927 {	3314 {

2928 { "(bad)",» { XX } },	3315 { Bad_Opcode },

2929 { "(bad)",» { XX } },	3316 { Bad_Opcode },

2930 { "packusdw", { XM, EXx } },	3317 { "packusdw", { XM, EXx } },

2931 { "(bad)", { XX } },

2932 },	3318 },

2933	3319

2934 /* PREFIX_0F3830 */	3320 /* PREFIX_0F3830 */

2935 {	3321 {

2936 { "(bad)",» { XX } },	3322 { Bad_Opcode },

2937 { "(bad)",» { XX } },	3323 { Bad_Opcode },

2938 { "pmovzxbw", { XM, EXq } },	3324 { "pmovzxbw", { XM, EXq } },

2939 { "(bad)", { XX } },

2940 },	3325 },

2941	3326

2942 /* PREFIX_0F3831 */	3327 /* PREFIX_0F3831 */

2943 {	3328 {

2944 { "(bad)",» { XX } },	3329 { Bad_Opcode },

2945 { "(bad)",» { XX } },	3330 { Bad_Opcode },

2946 { "pmovzxbd", { XM, EXd } },	3331 { "pmovzxbd", { XM, EXd } },

2947 { "(bad)", { XX } },

2948 },	3332 },

2949	3333

2950 /* PREFIX_0F3832 */	3334 /* PREFIX_0F3832 */

2951 {	3335 {

2952 { "(bad)",» { XX } },	3336 { Bad_Opcode },

2953 { "(bad)",» { XX } },	3337 { Bad_Opcode },

2954 { "pmovzxbq", { XM, EXw } },	3338 { "pmovzxbq", { XM, EXw } },

2955 { "(bad)", { XX } },

2956 },	3339 },

2957	3340

2958 /* PREFIX_0F3833 */	3341 /* PREFIX_0F3833 */

2959 {	3342 {

2960 { "(bad)",» { XX } },	3343 { Bad_Opcode },

2961 { "(bad)",» { XX } },	3344 { Bad_Opcode },

2962 { "pmovzxwd", { XM, EXq } },	3345 { "pmovzxwd", { XM, EXq } },

2963 { "(bad)", { XX } },

2964 },	3346 },

2965	3347

2966 /* PREFIX_0F3834 */	3348 /* PREFIX_0F3834 */

2967 {	3349 {

2968 { "(bad)",» { XX } },	3350 { Bad_Opcode },

2969 { "(bad)",» { XX } },	3351 { Bad_Opcode },

2970 { "pmovzxwq", { XM, EXd } },	3352 { "pmovzxwq", { XM, EXd } },

2971 { "(bad)", { XX } },

2972 },	3353 },

2973	3354

2974 /* PREFIX_0F3835 */	3355 /* PREFIX_0F3835 */

2975 {	3356 {

2976 { "(bad)",» { XX } },	3357 { Bad_Opcode },

2977 { "(bad)",» { XX } },	3358 { Bad_Opcode },

2978 { "pmovzxdq", { XM, EXq } },	3359 { "pmovzxdq", { XM, EXq } },

2979 { "(bad)", { XX } },

2980 },	3360 },

2981	3361

2982 /* PREFIX_0F3837 */	3362 /* PREFIX_0F3837 */

2983 {	3363 {

2984 { "(bad)",» { XX } },	3364 { Bad_Opcode },

2985 { "(bad)",» { XX } },	3365 { Bad_Opcode },

2986 { "pcmpgtq", { XM, EXx } },	3366 { "pcmpgtq", { XM, EXx } },

2987 { "(bad)", { XX } },

2988 },	3367 },

2989	3368

2990 /* PREFIX_0F3838 */	3369 /* PREFIX_0F3838 */

2991 {	3370 {

2992 { "(bad)",» { XX } },	3371 { Bad_Opcode },

2993 { "(bad)",» { XX } },	3372 { Bad_Opcode },

2994 { "pminsb", { XM, EXx } },	3373 { "pminsb", { XM, EXx } },

2995 { "(bad)", { XX } },

2996 },	3374 },

2997	3375

2998 /* PREFIX_0F3839 */	3376 /* PREFIX_0F3839 */

2999 {	3377 {

3000 { "(bad)",» { XX } },	3378 { Bad_Opcode },

3001 { "(bad)",» { XX } },	3379 { Bad_Opcode },

3002 { "pminsd", { XM, EXx } },	3380 { "pminsd", { XM, EXx } },

3003 { "(bad)", { XX } },

3004 },	3381 },

3005	3382

3006 /* PREFIX_0F383A */	3383 /* PREFIX_0F383A */

3007 {	3384 {

3008 { "(bad)",» { XX } },	3385 { Bad_Opcode },

3009 { "(bad)",» { XX } },	3386 { Bad_Opcode },

3010 { "pminuw", { XM, EXx } },	3387 { "pminuw", { XM, EXx } },

3011 { "(bad)", { XX } },

3012 },	3388 },

3013	3389

3014 /* PREFIX_0F383B */	3390 /* PREFIX_0F383B */

3015 {	3391 {

3016 { "(bad)",» { XX } },	3392 { Bad_Opcode },

3017 { "(bad)",» { XX } },	3393 { Bad_Opcode },

3018 { "pminud", { XM, EXx } },	3394 { "pminud", { XM, EXx } },

3019 { "(bad)", { XX } },

3020 },	3395 },

3021	3396

3022 /* PREFIX_0F383C */	3397 /* PREFIX_0F383C */

3023 {	3398 {

3024 { "(bad)",» { XX } },	3399 { Bad_Opcode },

3025 { "(bad)",» { XX } },	3400 { Bad_Opcode },

3026 { "pmaxsb", { XM, EXx } },	3401 { "pmaxsb", { XM, EXx } },

3027 { "(bad)", { XX } },

3028 },	3402 },

3029	3403

3030 /* PREFIX_0F383D */	3404 /* PREFIX_0F383D */

3031 {	3405 {

3032 { "(bad)",» { XX } },	3406 { Bad_Opcode },

3033 { "(bad)",» { XX } },	3407 { Bad_Opcode },

3034 { "pmaxsd", { XM, EXx } },	3408 { "pmaxsd", { XM, EXx } },

3035 { "(bad)", { XX } },

3036 },	3409 },

3037	3410

3038 /* PREFIX_0F383E */	3411 /* PREFIX_0F383E */

3039 {	3412 {

3040 { "(bad)",» { XX } },	3413 { Bad_Opcode },

3041 { "(bad)",» { XX } },	3414 { Bad_Opcode },

3042 { "pmaxuw", { XM, EXx } },	3415 { "pmaxuw", { XM, EXx } },

3043 { "(bad)", { XX } },

3044 },	3416 },

3045	3417

3046 /* PREFIX_0F383F */	3418 /* PREFIX_0F383F */

3047 {	3419 {

3048 { "(bad)",» { XX } },	3420 { Bad_Opcode },

3049 { "(bad)",» { XX } },	3421 { Bad_Opcode },

3050 { "pmaxud", { XM, EXx } },	3422 { "pmaxud", { XM, EXx } },

3051 { "(bad)", { XX } },

3052 },	3423 },

3053	3424

3054 /* PREFIX_0F3840 */	3425 /* PREFIX_0F3840 */

3055 {	3426 {

3056 { "(bad)",» { XX } },	3427 { Bad_Opcode },

3057 { "(bad)",» { XX } },	3428 { Bad_Opcode },

3058 { "pmulld", { XM, EXx } },	3429 { "pmulld", { XM, EXx } },

3059 { "(bad)", { XX } },

3060 },	3430 },

3061	3431

3062 /* PREFIX_0F3841 */	3432 /* PREFIX_0F3841 */

3063 {	3433 {

3064 { "(bad)",» { XX } },	3434 { Bad_Opcode },

3065 { "(bad)",» { XX } },	3435 { Bad_Opcode },

3066 { "phminposuw", { XM, EXx } },	3436 { "phminposuw", { XM, EXx } },

3067 { "(bad)", { XX } },

3068 },	3437 },

3069	3438

3070 /* PREFIX_0F3880 */	3439 /* PREFIX_0F3880 */

3071 {	3440 {

3072 { "(bad)",» { XX } },	3441 { Bad_Opcode },

3073 { "(bad)",» { XX } },	3442 { Bad_Opcode },

3074 { "invept", { Gm, Mo } },	3443 { "invept", { Gm, Mo } },

3075 { "(bad)", { XX } },

3076 },	3444 },

3077	3445

3078 /* PREFIX_0F3881 */	3446 /* PREFIX_0F3881 */

3079 {	3447 {

3080 { "(bad)",» { XX } },	3448 { Bad_Opcode },

3081 { "(bad)",» { XX } },	3449 { Bad_Opcode },

3082 { "invvpid", { Gm, Mo } },	3450 { "invvpid", { Gm, Mo } },

3083 { "(bad)",» { XX } },	3451 },

	3452

	3453 /* PREFIX_0F3882 */

	3454 {

	3455 { Bad_Opcode },

	3456 { Bad_Opcode },

	3457 { "invpcid", { Gm, M } },

3084 },	3458 },

3085	3459

3086 /* PREFIX_0F38DB */	3460 /* PREFIX_0F38DB */

3087 {	3461 {

3088 { "(bad)",» { XX } },	3462 { Bad_Opcode },

3089 { "(bad)",» { XX } },	3463 { Bad_Opcode },

3090 { "aesimc", { XM, EXx } },	3464 { "aesimc", { XM, EXx } },

3091 { "(bad)", { XX } },

3092 },	3465 },

3093	3466

3094 /* PREFIX_0F38DC */	3467 /* PREFIX_0F38DC */

3095 {	3468 {

3096 { "(bad)",» { XX } },	3469 { Bad_Opcode },

3097 { "(bad)",» { XX } },	3470 { Bad_Opcode },

3098 { "aesenc", { XM, EXx } },	3471 { "aesenc", { XM, EXx } },

3099 { "(bad)", { XX } },

3100 },	3472 },

3101	3473

3102 /* PREFIX_0F38DD */	3474 /* PREFIX_0F38DD */

3103 {	3475 {

3104 { "(bad)",» { XX } },	3476 { Bad_Opcode },

3105 { "(bad)",» { XX } },	3477 { Bad_Opcode },

3106 { "aesenclast", { XM, EXx } },	3478 { "aesenclast", { XM, EXx } },

3107 { "(bad)", { XX } },

3108 },	3479 },

3109	3480

3110 /* PREFIX_0F38DE */	3481 /* PREFIX_0F38DE */

3111 {	3482 {

3112 { "(bad)",» { XX } },	3483 { Bad_Opcode },

3113 { "(bad)",» { XX } },	3484 { Bad_Opcode },

3114 { "aesdec", { XM, EXx } },	3485 { "aesdec", { XM, EXx } },

3115 { "(bad)", { XX } },

3116 },	3486 },

3117	3487

3118 /* PREFIX_0F38DF */	3488 /* PREFIX_0F38DF */

3119 {	3489 {

3120 { "(bad)",» { XX } },	3490 { Bad_Opcode },

3121 { "(bad)",» { XX } },	3491 { Bad_Opcode },

3122 { "aesdeclast", { XM, EXx } },	3492 { "aesdeclast", { XM, EXx } },

3123 { "(bad)", { XX } },

3124 },	3493 },

3125	3494

3126 /* PREFIX_0F38F0 */	3495 /* PREFIX_0F38F0 */

3127 {	3496 {

3128 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },	3497 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },

3129 { "(bad)",» { XX } },	3498 { Bad_Opcode },

3130 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },	3499 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },

3131 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },	3500 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },

3132 },	3501 },

3133	3502

3134 /* PREFIX_0F38F1 */	3503 /* PREFIX_0F38F1 */

3135 {	3504 {

3136 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },	3505 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },

3137 { "(bad)",» { XX } },	3506 { Bad_Opcode },

3138 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },	3507 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },

3139 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },	3508 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },

3140 },	3509 },

3141	3510

	3511 /* PREFIX_0F38F6 */

	3512 {

	3513 { Bad_Opcode },

	3514 { "adoxS", { Gdq, Edq} },

	3515 { "adcxS", { Gdq, Edq} },

	3516 { Bad_Opcode },

	3517 },

	3518

3142 /* PREFIX_0F3A08 */	3519 /* PREFIX_0F3A08 */

3143 {	3520 {

3144 { "(bad)",» { XX } },	3521 { Bad_Opcode },

3145 { "(bad)",» { XX } },	3522 { Bad_Opcode },

3146 { "roundps", { XM, EXx, Ib } },	3523 { "roundps", { XM, EXx, Ib } },

3147 { "(bad)", { XX } },

3148 },	3524 },

3149	3525

3150 /* PREFIX_0F3A09 */	3526 /* PREFIX_0F3A09 */

3151 {	3527 {

3152 { "(bad)",» { XX } },	3528 { Bad_Opcode },

3153 { "(bad)",» { XX } },	3529 { Bad_Opcode },

3154 { "roundpd", { XM, EXx, Ib } },	3530 { "roundpd", { XM, EXx, Ib } },

3155 { "(bad)", { XX } },

3156 },	3531 },

3157	3532

3158 /* PREFIX_0F3A0A */	3533 /* PREFIX_0F3A0A */

3159 {	3534 {

3160 { "(bad)",» { XX } },	3535 { Bad_Opcode },

3161 { "(bad)",» { XX } },	3536 { Bad_Opcode },

3162 { "roundss", { XM, EXd, Ib } },	3537 { "roundss", { XM, EXd, Ib } },

3163 { "(bad)", { XX } },

3164 },	3538 },

3165	3539

3166 /* PREFIX_0F3A0B */	3540 /* PREFIX_0F3A0B */

3167 {	3541 {

3168 { "(bad)",» { XX } },	3542 { Bad_Opcode },

3169 { "(bad)",» { XX } },	3543 { Bad_Opcode },

3170 { "roundsd", { XM, EXq, Ib } },	3544 { "roundsd", { XM, EXq, Ib } },

3171 { "(bad)", { XX } },

3172 },	3545 },

3173	3546

3174 /* PREFIX_0F3A0C */	3547 /* PREFIX_0F3A0C */

3175 {	3548 {

3176 { "(bad)",» { XX } },	3549 { Bad_Opcode },

3177 { "(bad)",» { XX } },	3550 { Bad_Opcode },

3178 { "blendps", { XM, EXx, Ib } },	3551 { "blendps", { XM, EXx, Ib } },

3179 { "(bad)", { XX } },

3180 },	3552 },

3181	3553

3182 /* PREFIX_0F3A0D */	3554 /* PREFIX_0F3A0D */

3183 {	3555 {

3184 { "(bad)",» { XX } },	3556 { Bad_Opcode },

3185 { "(bad)",» { XX } },	3557 { Bad_Opcode },

3186 { "blendpd", { XM, EXx, Ib } },	3558 { "blendpd", { XM, EXx, Ib } },

3187 { "(bad)", { XX } },

3188 },	3559 },

3189	3560

3190 /* PREFIX_0F3A0E */	3561 /* PREFIX_0F3A0E */

3191 {	3562 {

3192 { "(bad)",» { XX } },	3563 { Bad_Opcode },

3193 { "(bad)",» { XX } },	3564 { Bad_Opcode },

3194 { "pblendw", { XM, EXx, Ib } },	3565 { "pblendw", { XM, EXx, Ib } },

3195 { "(bad)", { XX } },

3196 },	3566 },

3197	3567

3198 /* PREFIX_0F3A14 */	3568 /* PREFIX_0F3A14 */

3199 {	3569 {

3200 { "(bad)",» { XX } },	3570 { Bad_Opcode },

3201 { "(bad)",» { XX } },	3571 { Bad_Opcode },

3202 { "pextrb", { Edqb, XM, Ib } },	3572 { "pextrb", { Edqb, XM, Ib } },

3203 { "(bad)", { XX } },

3204 },	3573 },

3205	3574

3206 /* PREFIX_0F3A15 */	3575 /* PREFIX_0F3A15 */

3207 {	3576 {

3208 { "(bad)",» { XX } },	3577 { Bad_Opcode },

3209 { "(bad)",» { XX } },	3578 { Bad_Opcode },

3210 { "pextrw", { Edqw, XM, Ib } },	3579 { "pextrw", { Edqw, XM, Ib } },

3211 { "(bad)", { XX } },

3212 },	3580 },

3213	3581

3214 /* PREFIX_0F3A16 */	3582 /* PREFIX_0F3A16 */

3215 {	3583 {

3216 { "(bad)",» { XX } },	3584 { Bad_Opcode },

3217 { "(bad)",» { XX } },	3585 { Bad_Opcode },

3218 { "pextrK", { Edq, XM, Ib } },	3586 { "pextrK", { Edq, XM, Ib } },

3219 { "(bad)", { XX } },

3220 },	3587 },

3221	3588

3222 /* PREFIX_0F3A17 */	3589 /* PREFIX_0F3A17 */

3223 {	3590 {

3224 { "(bad)",» { XX } },	3591 { Bad_Opcode },

3225 { "(bad)",» { XX } },	3592 { Bad_Opcode },

3226 { "extractps", { Edqd, XM, Ib } },	3593 { "extractps", { Edqd, XM, Ib } },

3227 { "(bad)", { XX } },

3228 },	3594 },

3229	3595

3230 /* PREFIX_0F3A20 */	3596 /* PREFIX_0F3A20 */

3231 {	3597 {

3232 { "(bad)",» { XX } },	3598 { Bad_Opcode },

3233 { "(bad)",» { XX } },	3599 { Bad_Opcode },

3234 { "pinsrb", { XM, Edqb, Ib } },	3600 { "pinsrb", { XM, Edqb, Ib } },

3235 { "(bad)", { XX } },

3236 },	3601 },

3237	3602

3238 /* PREFIX_0F3A21 */	3603 /* PREFIX_0F3A21 */

3239 {	3604 {

3240 { "(bad)",» { XX } },	3605 { Bad_Opcode },

3241 { "(bad)",» { XX } },	3606 { Bad_Opcode },

3242 { "insertps", { XM, EXd, Ib } },	3607 { "insertps", { XM, EXd, Ib } },

3243 { "(bad)", { XX } },

3244 },	3608 },

3245	3609

3246 /* PREFIX_0F3A22 */	3610 /* PREFIX_0F3A22 */

3247 {	3611 {

3248 { "(bad)",» { XX } },	3612 { Bad_Opcode },

3249 { "(bad)",» { XX } },	3613 { Bad_Opcode },

3250 { "pinsrK", { XM, Edq, Ib } },	3614 { "pinsrK", { XM, Edq, Ib } },

3251 { "(bad)", { XX } },

3252 },	3615 },

3253	3616

3254 /* PREFIX_0F3A40 */	3617 /* PREFIX_0F3A40 */

3255 {	3618 {

3256 { "(bad)",» { XX } },	3619 { Bad_Opcode },

3257 { "(bad)",» { XX } },	3620 { Bad_Opcode },

3258 { "dpps", { XM, EXx, Ib } },	3621 { "dpps", { XM, EXx, Ib } },

3259 { "(bad)", { XX } },

3260 },	3622 },

3261	3623

3262 /* PREFIX_0F3A41 */	3624 /* PREFIX_0F3A41 */

3263 {	3625 {

3264 { "(bad)",» { XX } },	3626 { Bad_Opcode },

3265 { "(bad)",» { XX } },	3627 { Bad_Opcode },

3266 { "dppd", { XM, EXx, Ib } },	3628 { "dppd", { XM, EXx, Ib } },

3267 { "(bad)", { XX } },

3268 },	3629 },

3269	3630

3270 /* PREFIX_0F3A42 */	3631 /* PREFIX_0F3A42 */

3271 {	3632 {

3272 { "(bad)",» { XX } },	3633 { Bad_Opcode },

3273 { "(bad)",» { XX } },	3634 { Bad_Opcode },

3274 { "mpsadbw", { XM, EXx, Ib } },	3635 { "mpsadbw", { XM, EXx, Ib } },

3275 { "(bad)", { XX } },

3276 },	3636 },

3277	3637

3278 /* PREFIX_0F3A44 */	3638 /* PREFIX_0F3A44 */

3279 {	3639 {

3280 { "(bad)",» { XX } },	3640 { Bad_Opcode },

3281 { "(bad)",» { XX } },	3641 { Bad_Opcode },

3282 { "pclmulqdq", { XM, EXx, PCLMUL } },	3642 { "pclmulqdq", { XM, EXx, PCLMUL } },

3283 { "(bad)", { XX } },

3284 },	3643 },

3285	3644

3286 /* PREFIX_0F3A60 */	3645 /* PREFIX_0F3A60 */

3287 {	3646 {

3288 { "(bad)",» { XX } },	3647 { Bad_Opcode },

3289 { "(bad)",» { XX } },	3648 { Bad_Opcode },

3290 { "pcmpestrm", { XM, EXx, Ib } },	3649 { "pcmpestrm", { XM, EXx, Ib } },

3291 { "(bad)", { XX } },

3292 },	3650 },

3293	3651

3294 /* PREFIX_0F3A61 */	3652 /* PREFIX_0F3A61 */

3295 {	3653 {

3296 { "(bad)",» { XX } },	3654 { Bad_Opcode },

3297 { "(bad)",» { XX } },	3655 { Bad_Opcode },

3298 { "pcmpestri", { XM, EXx, Ib } },	3656 { "pcmpestri", { XM, EXx, Ib } },

3299 { "(bad)", { XX } },

3300 },	3657 },

3301	3658

3302 /* PREFIX_0F3A62 */	3659 /* PREFIX_0F3A62 */

3303 {	3660 {

3304 { "(bad)",» { XX } },	3661 { Bad_Opcode },

3305 { "(bad)",» { XX } },	3662 { Bad_Opcode },

3306 { "pcmpistrm", { XM, EXx, Ib } },	3663 { "pcmpistrm", { XM, EXx, Ib } },

3307 { "(bad)", { XX } },

3308 },	3664 },

3309	3665

3310 /* PREFIX_0F3A63 */	3666 /* PREFIX_0F3A63 */

3311 {	3667 {

3312 { "(bad)",» { XX } },	3668 { Bad_Opcode },

3313 { "(bad)",» { XX } },	3669 { Bad_Opcode },

3314 { "pcmpistri", { XM, EXx, Ib } },	3670 { "pcmpistri", { XM, EXx, Ib } },

3315 { "(bad)", { XX } },

3316 },	3671 },

3317	3672

3318 /* PREFIX_0F3ADF */	3673 /* PREFIX_0F3ADF */

3319 {	3674 {

3320 { "(bad)",» { XX } },	3675 { Bad_Opcode },

3321 { "(bad)",» { XX } },	3676 { Bad_Opcode },

3322 { "aeskeygenassist", { XM, EXx, Ib } },	3677 { "aeskeygenassist", { XM, EXx, Ib } },

3323 { "(bad)",» { XX } },	3678 },

3324 },	3679

3325	3680 /* PREFIX_VEX_0F10 */

3326 /* PREFIX_VEX_10 */	3681 {

3327 {	3682 { VEX_W_TABLE (VEX_W_0F10_P_0) },

3328 { "vmovups", { XM, EXx } },	3683 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },

3329 { VEX_LEN_TABLE (VEX_LEN_10_P_1) },	3684 { VEX_W_TABLE (VEX_W_0F10_P_2) },

3330 { "vmovupd", { XM, EXx } },	3685 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },

3331 { VEX_LEN_TABLE (VEX_LEN_10_P_3) },	3686 },

3332 },	3687

3333	3688 /* PREFIX_VEX_0F11 */

3334 /* PREFIX_VEX_11 */	3689 {

3335 {	3690 { VEX_W_TABLE (VEX_W_0F11_P_0) },

3336 { "vmovups", { EXxS, XM } },	3691 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },

3337 { VEX_LEN_TABLE (VEX_LEN_11_P_1) },	3692 { VEX_W_TABLE (VEX_W_0F11_P_2) },

3338 { "vmovupd", { EXxS, XM } },	3693 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },

3339 { VEX_LEN_TABLE (VEX_LEN_11_P_3) },	3694 },

3340 },	3695

3341	3696 /* PREFIX_VEX_0F12 */

3342 /* PREFIX_VEX_12 */	3697 {

3343 {	3698 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },

3344 { MOD_TABLE (MOD_VEX_12_PREFIX_0) },	3699 { VEX_W_TABLE (VEX_W_0F12_P_1) },

3345 { "vmovsldup", { XM, EXx } },	3700 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },

3346 { VEX_LEN_TABLE (VEX_LEN_12_P_2) },	3701 { VEX_W_TABLE (VEX_W_0F12_P_3) },

3347 { "vmovddup", { XM, EXymmq } },	3702 },

3348 },	3703

3349	3704 /* PREFIX_VEX_0F16 */

3350 /* PREFIX_VEX_16 */	3705 {

3351 {	3706 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },

3352 { MOD_TABLE (MOD_VEX_16_PREFIX_0) },	3707 { VEX_W_TABLE (VEX_W_0F16_P_1) },

3353 { "vmovshdup", { XM, EXx } },	3708 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },

3354 { VEX_LEN_TABLE (VEX_LEN_16_P_2) },	3709 },

3355 { "(bad)",» { XX } },	3710

3356 },	3711 /* PREFIX_VEX_0F2A */

3357	3712 {

3358 /* PREFIX_VEX_2A */	3713 { Bad_Opcode },

3359 {	3714 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },

3360 { "(bad)",» { XX } },	3715 { Bad_Opcode },

3361 { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },	3716 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },

3362 { "(bad)",» { XX } },	3717 },

3363 { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },	3718

3364 },	3719 /* PREFIX_VEX_0F2C */

3365	3720 {

3366 /* PREFIX_VEX_2C */	3721 { Bad_Opcode },

3367 {	3722 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },

3368 { "(bad)",» { XX } },	3723 { Bad_Opcode },

3369 { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },	3724 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },

3370 { "(bad)",» { XX } },	3725 },

3371 { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },	3726

3372 },	3727 /* PREFIX_VEX_0F2D */

3373	3728 {

3374 /* PREFIX_VEX_2D */	3729 { Bad_Opcode },

3375 {	3730 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },

3376 { "(bad)",» { XX } },	3731 { Bad_Opcode },

3377 { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },	3732 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },

3378 { "(bad)",» { XX } },	3733 },

3379 { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },	3734

3380 },	3735 /* PREFIX_VEX_0F2E */

3381	3736 {

3382 /* PREFIX_VEX_2E */	3737 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },

3383 {	3738 { Bad_Opcode },

3384 { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },	3739 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },

3385 { "(bad)",» { XX } },	3740 },

3386 { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },	3741

3387 { "(bad)",» { XX } },	3742 /* PREFIX_VEX_0F2F */

3388 },	3743 {

3389	3744 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },

3390 /* PREFIX_VEX_2F */	3745 { Bad_Opcode },

3391 {	3746 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },

3392 { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },	3747 },

3393 { "(bad)",» { XX } },	3748

3394 { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },	3749 /* PREFIX_VEX_0F51 */

3395 { "(bad)",» { XX } },	3750 {

3396 },	3751 { VEX_W_TABLE (VEX_W_0F51_P_0) },

3397	3752 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },

3398 /* PREFIX_VEX_51 */	3753 { VEX_W_TABLE (VEX_W_0F51_P_2) },

3399 {	3754 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },

3400 { "vsqrtps", { XM, EXx } },	3755 },

3401 { VEX_LEN_TABLE (VEX_LEN_51_P_1) },	3756

3402 { "vsqrtpd", { XM, EXx } },	3757 /* PREFIX_VEX_0F52 */

3403 { VEX_LEN_TABLE (VEX_LEN_51_P_3) },	3758 {

3404 },	3759 { VEX_W_TABLE (VEX_W_0F52_P_0) },

3405	3760 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },

3406 /* PREFIX_VEX_52 */	3761 },

3407 {	3762

3408 { "vrsqrtps", { XM, EXx } },	3763 /* PREFIX_VEX_0F53 */

3409 { VEX_LEN_TABLE (VEX_LEN_52_P_1) },	3764 {

3410 { "(bad)",» { XX } },	3765 { VEX_W_TABLE (VEX_W_0F53_P_0) },

3411 { "(bad)",» { XX } },	3766 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },

3412 },	3767 },

3413	3768

3414 /* PREFIX_VEX_53 */	3769 /* PREFIX_VEX_0F58 */

3415 {	3770 {

3416 { "vrcpps",»{ XM, EXx } },	3771 { VEX_W_TABLE (VEX_W_0F58_P_0) },

3417 { VEX_LEN_TABLE (VEX_LEN_53_P_1) },	3772 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },

3418 { "(bad)",» { XX } },	3773 { VEX_W_TABLE (VEX_W_0F58_P_2) },

3419 { "(bad)",» { XX } },	3774 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },

3420 },	3775 },

3421	3776

3422 /* PREFIX_VEX_58 */	3777 /* PREFIX_VEX_0F59 */

3423 {	3778 {

3424 { "vaddps",»{ XM, Vex, EXx } },	3779 { VEX_W_TABLE (VEX_W_0F59_P_0) },

3425 { VEX_LEN_TABLE (VEX_LEN_58_P_1) },	3780 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },

3426 { "vaddpd",»{ XM, Vex, EXx } },	3781 { VEX_W_TABLE (VEX_W_0F59_P_2) },

3427 { VEX_LEN_TABLE (VEX_LEN_58_P_3) },	3782 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },

3428 },	3783 },

3429	3784

3430 /* PREFIX_VEX_59 */	3785 /* PREFIX_VEX_0F5A */

3431 {	3786 {

3432 { "vmulps",»{ XM, Vex, EXx } },	3787 { VEX_W_TABLE (VEX_W_0F5A_P_0) },

3433 { VEX_LEN_TABLE (VEX_LEN_59_P_1) },	3788 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },

3434 { "vmulpd",»{ XM, Vex, EXx } },

3435 { VEX_LEN_TABLE (VEX_LEN_59_P_3) },

3436 },

3437

3438 /* PREFIX_VEX_5A */

3439 {

3440 { "vcvtps2pd", { XM, EXxmmq } },

3441 { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },

3442 { "vcvtpd2ps%XY", { XMM, EXx } },	3789 { "vcvtpd2ps%XY", { XMM, EXx } },

3443 { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },	3790 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },

3444 },	3791 },

3445	3792

3446 /* PREFIX_VEX_5B */	3793 /* PREFIX_VEX_0F5B */

3447 {	3794 {

3448 { "vcvtdq2ps", { XM, EXx } },	3795 { VEX_W_TABLE (VEX_W_0F5B_P_0) },

3449 { "vcvttps2dq", { XM, EXx } },	3796 { VEX_W_TABLE (VEX_W_0F5B_P_1) },

3450 { "vcvtps2dq", { XM, EXx } },	3797 { VEX_W_TABLE (VEX_W_0F5B_P_2) },

3451 { "(bad)", { XX } },	3798 },

3452 },	3799

3453	3800 /* PREFIX_VEX_0F5C */

3454 /* PREFIX_VEX_5C */	3801 {

3455 {	3802 { VEX_W_TABLE (VEX_W_0F5C_P_0) },

3456 { "vsubps", { XM, Vex, EXx } },	3803 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },

3457 { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },	3804 { VEX_W_TABLE (VEX_W_0F5C_P_2) },

3458 { "vsubpd", { XM, Vex, EXx } },	3805 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },

3459 { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },	3806 },

3460 },	3807

3461	3808 /* PREFIX_VEX_0F5D */

3462 /* PREFIX_VEX_5D */	3809 {

3463 {	3810 { VEX_W_TABLE (VEX_W_0F5D_P_0) },

3464 { "vminps", { XM, Vex, EXx } },	3811 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },

3465 { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },	3812 { VEX_W_TABLE (VEX_W_0F5D_P_2) },

3466 { "vminpd", { XM, Vex, EXx } },	3813 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },

3467 { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },	3814 },

3468 },	3815

3469	3816 /* PREFIX_VEX_0F5E */

3470 /* PREFIX_VEX_5E */	3817 {

3471 {	3818 { VEX_W_TABLE (VEX_W_0F5E_P_0) },

3472 { "vdivps", { XM, Vex, EXx } },	3819 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },

3473 { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },	3820 { VEX_W_TABLE (VEX_W_0F5E_P_2) },

3474 { "vdivpd", { XM, Vex, EXx } },	3821 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },

3475 { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },	3822 },

3476 },	3823

3477	3824 /* PREFIX_VEX_0F5F */

3478 /* PREFIX_VEX_5F */	3825 {

3479 {	3826 { VEX_W_TABLE (VEX_W_0F5F_P_0) },

3480 { "vmaxps", { XM, Vex, EXx } },	3827 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },

3481 { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },	3828 { VEX_W_TABLE (VEX_W_0F5F_P_2) },

3482 { "vmaxpd", { XM, Vex, EXx } },	3829 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },

3483 { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },	3830 },

3484 },	3831

3485	3832 /* PREFIX_VEX_0F60 */

3486 /* PREFIX_VEX_60 */	3833 {

3487 {	3834 { Bad_Opcode },

3488 { "(bad)", { XX } },	3835 { Bad_Opcode },

3489 { "(bad)", { XX } },	3836 { VEX_W_TABLE (VEX_W_0F60_P_2) },

3490 { VEX_LEN_TABLE (VEX_LEN_60_P_2) },	3837 },

3491 { "(bad)", { XX } },	3838

3492 },	3839 /* PREFIX_VEX_0F61 */

3493	3840 {

3494 /* PREFIX_VEX_61 */	3841 { Bad_Opcode },

3495 {	3842 { Bad_Opcode },

3496 { "(bad)", { XX } },	3843 { VEX_W_TABLE (VEX_W_0F61_P_2) },

3497 { "(bad)", { XX } },	3844 },

3498 { VEX_LEN_TABLE (VEX_LEN_61_P_2) },	3845

3499 { "(bad)", { XX } },	3846 /* PREFIX_VEX_0F62 */

3500 },	3847 {

3501	3848 { Bad_Opcode },

3502 /* PREFIX_VEX_62 */	3849 { Bad_Opcode },

3503 {	3850 { VEX_W_TABLE (VEX_W_0F62_P_2) },

3504 { "(bad)", { XX } },	3851 },

3505 { "(bad)", { XX } },	3852

3506 { VEX_LEN_TABLE (VEX_LEN_62_P_2) },	3853 /* PREFIX_VEX_0F63 */

3507 { "(bad)", { XX } },	3854 {

3508 },	3855 { Bad_Opcode },

3509	3856 { Bad_Opcode },

3510 /* PREFIX_VEX_63 */	3857 { VEX_W_TABLE (VEX_W_0F63_P_2) },

3511 {	3858 },

3512 { "(bad)", { XX } },	3859

3513 { "(bad)", { XX } },	3860 /* PREFIX_VEX_0F64 */

3514 { VEX_LEN_TABLE (VEX_LEN_63_P_2) },	3861 {

3515 { "(bad)", { XX } },	3862 { Bad_Opcode },

3516 },	3863 { Bad_Opcode },

3517	3864 { VEX_W_TABLE (VEX_W_0F64_P_2) },

3518 /* PREFIX_VEX_64 */	3865 },

3519 {	3866

3520 { "(bad)", { XX } },	3867 /* PREFIX_VEX_0F65 */

3521 { "(bad)", { XX } },	3868 {

3522 { VEX_LEN_TABLE (VEX_LEN_64_P_2) },	3869 { Bad_Opcode },

3523 { "(bad)", { XX } },	3870 { Bad_Opcode },

3524 },	3871 { VEX_W_TABLE (VEX_W_0F65_P_2) },

3525	3872 },

3526 /* PREFIX_VEX_65 */	3873

3527 {	3874 /* PREFIX_VEX_0F66 */

3528 { "(bad)", { XX } },	3875 {

3529 { "(bad)", { XX } },	3876 { Bad_Opcode },

3530 { VEX_LEN_TABLE (VEX_LEN_65_P_2) },	3877 { Bad_Opcode },

3531 { "(bad)", { XX } },	3878 { VEX_W_TABLE (VEX_W_0F66_P_2) },

3532 },	3879 },

3533	3880

3534 /* PREFIX_VEX_66 */	3881 /* PREFIX_VEX_0F67 */

3535 {	3882 {

3536 { "(bad)", { XX } },	3883 { Bad_Opcode },

3537 { "(bad)", { XX } },	3884 { Bad_Opcode },

3538 { VEX_LEN_TABLE (VEX_LEN_66_P_2) },	3885 { VEX_W_TABLE (VEX_W_0F67_P_2) },

3539 { "(bad)", { XX } },	3886 },

3540 },	3887

3541	3888 /* PREFIX_VEX_0F68 */

3542 /* PREFIX_VEX_67 */	3889 {

3543 {	3890 { Bad_Opcode },

3544 { "(bad)", { XX } },	3891 { Bad_Opcode },

3545 { "(bad)", { XX } },	3892 { VEX_W_TABLE (VEX_W_0F68_P_2) },

3546 { VEX_LEN_TABLE (VEX_LEN_67_P_2) },	3893 },

3547 { "(bad)", { XX } },	3894

3548 },	3895 /* PREFIX_VEX_0F69 */

3549	3896 {

3550 /* PREFIX_VEX_68 */	3897 { Bad_Opcode },

3551 {	3898 { Bad_Opcode },

3552 { "(bad)", { XX } },	3899 { VEX_W_TABLE (VEX_W_0F69_P_2) },

3553 { "(bad)", { XX } },	3900 },

3554 { VEX_LEN_TABLE (VEX_LEN_68_P_2) },	3901

3555 { "(bad)", { XX } },	3902 /* PREFIX_VEX_0F6A */

3556 },	3903 {

3557	3904 { Bad_Opcode },

3558 /* PREFIX_VEX_69 */	3905 { Bad_Opcode },

3559 {	3906 { VEX_W_TABLE (VEX_W_0F6A_P_2) },

3560 { "(bad)", { XX } },	3907 },

3561 { "(bad)", { XX } },	3908

3562 { VEX_LEN_TABLE (VEX_LEN_69_P_2) },	3909 /* PREFIX_VEX_0F6B */

3563 { "(bad)", { XX } },	3910 {

3564 },	3911 { Bad_Opcode },

3565	3912 { Bad_Opcode },

3566 /* PREFIX_VEX_6A */	3913 { VEX_W_TABLE (VEX_W_0F6B_P_2) },

3567 {	3914 },

3568 { "(bad)", { XX } },	3915

3569 { "(bad)", { XX } },	3916 /* PREFIX_VEX_0F6C */

3570 { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },	3917 {

3571 { "(bad)", { XX } },	3918 { Bad_Opcode },

3572 },	3919 { Bad_Opcode },

3573	3920 { VEX_W_TABLE (VEX_W_0F6C_P_2) },

3574 /* PREFIX_VEX_6B */	3921 },

3575 {	3922

3576 { "(bad)", { XX } },	3923 /* PREFIX_VEX_0F6D */

3577 { "(bad)", { XX } },	3924 {

3578 { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },	3925 { Bad_Opcode },

3579 { "(bad)", { XX } },	3926 { Bad_Opcode },

3580 },	3927 { VEX_W_TABLE (VEX_W_0F6D_P_2) },

3581	3928 },

3582 /* PREFIX_VEX_6C */	3929

3583 {	3930 /* PREFIX_VEX_0F6E */

3584 { "(bad)", { XX } },	3931 {

3585 { "(bad)", { XX } },	3932 { Bad_Opcode },

3586 { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },	3933 { Bad_Opcode },

3587 { "(bad)", { XX } },	3934 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },

3588 },	3935 },

3589	3936

3590 /* PREFIX_VEX_6D */	3937 /* PREFIX_VEX_0F6F */

3591 {	3938 {

3592 { "(bad)", { XX } },	3939 { Bad_Opcode },

3593 { "(bad)", { XX } },	3940 { VEX_W_TABLE (VEX_W_0F6F_P_1) },

3594 { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },	3941 { VEX_W_TABLE (VEX_W_0F6F_P_2) },

3595 { "(bad)", { XX } },	3942 },

3596 },	3943

3597	3944 /* PREFIX_VEX_0F70 */

3598 /* PREFIX_VEX_6E */	3945 {

3599 {	3946 { Bad_Opcode },

3600 { "(bad)", { XX } },	3947 { VEX_W_TABLE (VEX_W_0F70_P_1) },

3601 { "(bad)", { XX } },	3948 { VEX_W_TABLE (VEX_W_0F70_P_2) },

3602 { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },	3949 { VEX_W_TABLE (VEX_W_0F70_P_3) },

3603 { "(bad)", { XX } },	3950 },

3604 },	3951

3605	3952 /* PREFIX_VEX_0F71_REG_2 */

3606 /* PREFIX_VEX_6F */	3953 {

3607 {	3954 { Bad_Opcode },

3608 { "(bad)", { XX } },	3955 { Bad_Opcode },

3609 { "vmovdqu", { XM, EXx } },	3956 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },

3610 { "vmovdqa", { XM, EXx } },	3957 },

3611 { "(bad)", { XX } },	3958

3612 },	3959 /* PREFIX_VEX_0F71_REG_4 */

3613	3960 {

3614 /* PREFIX_VEX_70 */	3961 { Bad_Opcode },

3615 {	3962 { Bad_Opcode },

3616 { "(bad)", { XX } },	3963 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },

3617 { VEX_LEN_TABLE (VEX_LEN_70_P_1) },	3964 },

3618 { VEX_LEN_TABLE (VEX_LEN_70_P_2) },	3965

3619 { VEX_LEN_TABLE (VEX_LEN_70_P_3) },	3966 /* PREFIX_VEX_0F71_REG_6 */

3620 },	3967 {

3621	3968 { Bad_Opcode },

3622 /* PREFIX_VEX_71_REG_2 */	3969 { Bad_Opcode },

3623 {	3970 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },

3624 { "(bad)", { XX } },	3971 },

3625 { "(bad)", { XX } },	3972

3626 { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },	3973 /* PREFIX_VEX_0F72_REG_2 */

3627 { "(bad)", { XX } },	3974 {

3628 },	3975 { Bad_Opcode },

3629	3976 { Bad_Opcode },

3630 /* PREFIX_VEX_71_REG_4 */	3977 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },

3631 {	3978 },

3632 { "(bad)", { XX } },	3979

3633 { "(bad)", { XX } },	3980 /* PREFIX_VEX_0F72_REG_4 */

3634 { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },	3981 {

3635 { "(bad)", { XX } },	3982 { Bad_Opcode },

3636 },	3983 { Bad_Opcode },

3637	3984 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },

3638 /* PREFIX_VEX_71_REG_6 */	3985 },

3639 {	3986

3640 { "(bad)", { XX } },	3987 /* PREFIX_VEX_0F72_REG_6 */

3641 { "(bad)", { XX } },	3988 {

3642 { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },	3989 { Bad_Opcode },

3643 { "(bad)", { XX } },	3990 { Bad_Opcode },

3644 },	3991 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },

3645	3992 },

3646 /* PREFIX_VEX_72_REG_2 */	3993

3647 {	3994 /* PREFIX_VEX_0F73_REG_2 */

3648 { "(bad)", { XX } },	3995 {

3649 { "(bad)", { XX } },	3996 { Bad_Opcode },

3650 { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },	3997 { Bad_Opcode },

3651 { "(bad)", { XX } },	3998 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },

3652 },	3999 },

3653	4000

3654 /* PREFIX_VEX_72_REG_4 */	4001 /* PREFIX_VEX_0F73_REG_3 */

3655 {	4002 {

3656 { "(bad)", { XX } },	4003 { Bad_Opcode },

3657 { "(bad)", { XX } },	4004 { Bad_Opcode },

3658 { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },	4005 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },

3659 { "(bad)", { XX } },	4006 },

3660 },	4007

3661	4008 /* PREFIX_VEX_0F73_REG_6 */

3662 /* PREFIX_VEX_72_REG_6 */	4009 {

3663 {	4010 { Bad_Opcode },

3664 { "(bad)", { XX } },	4011 { Bad_Opcode },

3665 { "(bad)", { XX } },	4012 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },

3666 { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },	4013 },

3667 { "(bad)", { XX } },	4014

3668 },	4015 /* PREFIX_VEX_0F73_REG_7 */

3669	4016 {

3670 /* PREFIX_VEX_73_REG_2 */	4017 { Bad_Opcode },

3671 {	4018 { Bad_Opcode },

3672 { "(bad)", { XX } },	4019 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },

3673 { "(bad)", { XX } },	4020 },

3674 { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },	4021

3675 { "(bad)", { XX } },	4022 /* PREFIX_VEX_0F74 */

3676 },	4023 {

3677	4024 { Bad_Opcode },

3678 /* PREFIX_VEX_73_REG_3 */	4025 { Bad_Opcode },

3679 {	4026 { VEX_W_TABLE (VEX_W_0F74_P_2) },

3680 { "(bad)", { XX } },	4027 },

3681 { "(bad)", { XX } },	4028

3682 { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },	4029 /* PREFIX_VEX_0F75 */

3683 { "(bad)", { XX } },	4030 {

3684 },	4031 { Bad_Opcode },

3685	4032 { Bad_Opcode },

3686 /* PREFIX_VEX_73_REG_6 */	4033 { VEX_W_TABLE (VEX_W_0F75_P_2) },

3687 {	4034 },

3688 { "(bad)", { XX } },	4035

3689 { "(bad)", { XX } },	4036 /* PREFIX_VEX_0F76 */

3690 { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },	4037 {

3691 { "(bad)", { XX } },	4038 { Bad_Opcode },

3692 },	4039 { Bad_Opcode },

3693	4040 { VEX_W_TABLE (VEX_W_0F76_P_2) },

3694 /* PREFIX_VEX_73_REG_7 */	4041 },

3695 {	4042

3696 { "(bad)", { XX } },	4043 /* PREFIX_VEX_0F77 */

3697 { "(bad)", { XX } },	4044 {

3698 { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },	4045 { VEX_W_TABLE (VEX_W_0F77_P_0) },

3699 { "(bad)", { XX } },	4046 },

3700 },	4047

3701	4048 /* PREFIX_VEX_0F7C */

3702 /* PREFIX_VEX_74 */	4049 {

3703 {	4050 { Bad_Opcode },

3704 { "(bad)", { XX } },	4051 { Bad_Opcode },

3705 { "(bad)", { XX } },	4052 { VEX_W_TABLE (VEX_W_0F7C_P_2) },

3706 { VEX_LEN_TABLE (VEX_LEN_74_P_2) },	4053 { VEX_W_TABLE (VEX_W_0F7C_P_3) },

3707 { "(bad)", { XX } },	4054 },

3708 },	4055

3709	4056 /* PREFIX_VEX_0F7D */

3710 /* PREFIX_VEX_75 */	4057 {

3711 {	4058 { Bad_Opcode },

3712 { "(bad)", { XX } },	4059 { Bad_Opcode },

3713 { "(bad)", { XX } },	4060 { VEX_W_TABLE (VEX_W_0F7D_P_2) },

3714 { VEX_LEN_TABLE (VEX_LEN_75_P_2) },	4061 { VEX_W_TABLE (VEX_W_0F7D_P_3) },

3715 { "(bad)", { XX } },	4062 },

3716 },	4063

3717	4064 /* PREFIX_VEX_0F7E */

3718 /* PREFIX_VEX_76 */	4065 {

3719 {	4066 { Bad_Opcode },

3720 { "(bad)", { XX } },	4067 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },

3721 { "(bad)", { XX } },	4068 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },

3722 { VEX_LEN_TABLE (VEX_LEN_76_P_2) },	4069 },

3723 { "(bad)", { XX } },	4070

3724 },	4071 /* PREFIX_VEX_0F7F */

3725	4072 {

3726 /* PREFIX_VEX_77 */	4073 { Bad_Opcode },

3727 {	4074 { VEX_W_TABLE (VEX_W_0F7F_P_1) },

3728 { "", { VZERO } },	4075 { VEX_W_TABLE (VEX_W_0F7F_P_2) },

3729 { "(bad)", { XX } },	4076 },

3730 { "(bad)", { XX } },	4077

3731 { "(bad)", { XX } },	4078 /* PREFIX_VEX_0FC2 */

3732 },	4079 {

3733	4080 { VEX_W_TABLE (VEX_W_0FC2_P_0) },

3734 /* PREFIX_VEX_7C */	4081 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },

3735 {	4082 { VEX_W_TABLE (VEX_W_0FC2_P_2) },

3736 { "(bad)", { XX } },	4083 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },

3737 { "(bad)", { XX } },	4084 },

3738 { "vhaddpd", { XM, Vex, EXx } },	4085

3739 { "vhaddps", { XM, Vex, EXx } },	4086 /* PREFIX_VEX_0FC4 */

3740 },	4087 {

3741	4088 { Bad_Opcode },

3742 /* PREFIX_VEX_7D */	4089 { Bad_Opcode },

3743 {	4090 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },

3744 { "(bad)", { XX } },	4091 },

3745 { "(bad)", { XX } },	4092

3746 { "vhsubpd", { XM, Vex, EXx } },	4093 /* PREFIX_VEX_0FC5 */

3747 { "vhsubps", { XM, Vex, EXx } },	4094 {

3748 },	4095 { Bad_Opcode },

3749	4096 { Bad_Opcode },

3750 /* PREFIX_VEX_7E */	4097 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },

3751 {	4098 },

3752 { "(bad)", { XX } },	4099

3753 { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },	4100 /* PREFIX_VEX_0FD0 */

3754 { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },	4101 {

3755 { "(bad)", { XX } },	4102 { Bad_Opcode },

3756 },	4103 { Bad_Opcode },

3757	4104 { VEX_W_TABLE (VEX_W_0FD0_P_2) },

3758 /* PREFIX_VEX_7F */	4105 { VEX_W_TABLE (VEX_W_0FD0_P_3) },

3759 {	4106 },

3760 { "(bad)", { XX } },	4107

3761 { "vmovdqu", { EXxS, XM } },	4108 /* PREFIX_VEX_0FD1 */

3762 { "vmovdqa", { EXxS, XM } },	4109 {

3763 { "(bad)", { XX } },	4110 { Bad_Opcode },

3764 },	4111 { Bad_Opcode },

3765	4112 { VEX_W_TABLE (VEX_W_0FD1_P_2) },

3766 /* PREFIX_VEX_C2 */	4113 },

3767 {	4114

3768 { "vcmpps", { XM, Vex, EXx, VCMP } },	4115 /* PREFIX_VEX_0FD2 */

3769 { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },	4116 {

3770 { "vcmppd", { XM, Vex, EXx, VCMP } },	4117 { Bad_Opcode },

3771 { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },	4118 { Bad_Opcode },

3772 },	4119 { VEX_W_TABLE (VEX_W_0FD2_P_2) },

3773	4120 },

3774 /* PREFIX_VEX_C4 */	4121

3775 {	4122 /* PREFIX_VEX_0FD3 */

3776 { "(bad)", { XX } },	4123 {

3777 { "(bad)", { XX } },	4124 { Bad_Opcode },

3778 { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },	4125 { Bad_Opcode },

3779 { "(bad)", { XX } },	4126 { VEX_W_TABLE (VEX_W_0FD3_P_2) },

3780 },	4127 },

3781	4128

3782 /* PREFIX_VEX_C5 */	4129 /* PREFIX_VEX_0FD4 */

3783 {	4130 {

3784 { "(bad)", { XX } },	4131 { Bad_Opcode },

3785 { "(bad)", { XX } },	4132 { Bad_Opcode },

3786 { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },	4133 { VEX_W_TABLE (VEX_W_0FD4_P_2) },

3787 { "(bad)", { XX } },	4134 },

3788 },	4135

3789	4136 /* PREFIX_VEX_0FD5 */

3790 /* PREFIX_VEX_D0 */	4137 {

3791 {	4138 { Bad_Opcode },

3792 { "(bad)", { XX } },	4139 { Bad_Opcode },

3793 { "(bad)", { XX } },	4140 { VEX_W_TABLE (VEX_W_0FD5_P_2) },

3794 { "vaddsubpd", { XM, Vex, EXx } },	4141 },

3795 { "vaddsubps", { XM, Vex, EXx } },	4142

3796 },	4143 /* PREFIX_VEX_0FD6 */

3797	4144 {

3798 /* PREFIX_VEX_D1 */	4145 { Bad_Opcode },

3799 {	4146 { Bad_Opcode },

3800 { "(bad)", { XX } },	4147 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },

3801 { "(bad)", { XX } },	4148 },

3802 { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },	4149

3803 { "(bad)", { XX } },	4150 /* PREFIX_VEX_0FD7 */

3804 },	4151 {

3805	4152 { Bad_Opcode },

3806 /* PREFIX_VEX_D2 */	4153 { Bad_Opcode },

3807 {	4154 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },

3808 { "(bad)", { XX } },	4155 },

3809 { "(bad)", { XX } },	4156

3810 { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },	4157 /* PREFIX_VEX_0FD8 */

3811 { "(bad)", { XX } },	4158 {

3812 },	4159 { Bad_Opcode },

3813	4160 { Bad_Opcode },

3814 /* PREFIX_VEX_D3 */	4161 { VEX_W_TABLE (VEX_W_0FD8_P_2) },

3815 {	4162 },

3816 { "(bad)", { XX } },	4163

3817 { "(bad)", { XX } },	4164 /* PREFIX_VEX_0FD9 */

3818 { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },	4165 {

3819 { "(bad)", { XX } },	4166 { Bad_Opcode },

3820 },	4167 { Bad_Opcode },

3821	4168 { VEX_W_TABLE (VEX_W_0FD9_P_2) },

3822 /* PREFIX_VEX_D4 */	4169 },

3823 {	4170

3824 { "(bad)", { XX } },	4171 /* PREFIX_VEX_0FDA */

3825 { "(bad)", { XX } },	4172 {

3826 { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },	4173 { Bad_Opcode },

3827 { "(bad)", { XX } },	4174 { Bad_Opcode },

3828 },	4175 { VEX_W_TABLE (VEX_W_0FDA_P_2) },

3829	4176 },

3830 /* PREFIX_VEX_D5 */	4177

3831 {	4178 /* PREFIX_VEX_0FDB */

3832 { "(bad)", { XX } },	4179 {

3833 { "(bad)", { XX } },	4180 { Bad_Opcode },

3834 { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },	4181 { Bad_Opcode },

3835 { "(bad)", { XX } },	4182 { VEX_W_TABLE (VEX_W_0FDB_P_2) },

3836 },	4183 },

3837	4184

3838 /* PREFIX_VEX_D6 */	4185 /* PREFIX_VEX_0FDC */

3839 {	4186 {

3840 { "(bad)", { XX } },	4187 { Bad_Opcode },

3841 { "(bad)", { XX } },	4188 { Bad_Opcode },

3842 { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },	4189 { VEX_W_TABLE (VEX_W_0FDC_P_2) },

3843 { "(bad)", { XX } },	4190 },

3844 },	4191

3845	4192 /* PREFIX_VEX_0FDD */

3846 /* PREFIX_VEX_D7 */	4193 {

3847 {	4194 { Bad_Opcode },

3848 { "(bad)", { XX } },	4195 { Bad_Opcode },

3849 { "(bad)", { XX } },	4196 { VEX_W_TABLE (VEX_W_0FDD_P_2) },

3850 { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },	4197 },

3851 { "(bad)", { XX } },	4198

3852 },	4199 /* PREFIX_VEX_0FDE */

3853	4200 {

3854 /* PREFIX_VEX_D8 */	4201 { Bad_Opcode },

3855 {	4202 { Bad_Opcode },

3856 { "(bad)", { XX } },	4203 { VEX_W_TABLE (VEX_W_0FDE_P_2) },

3857 { "(bad)", { XX } },	4204 },

3858 { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },	4205

3859 { "(bad)", { XX } },	4206 /* PREFIX_VEX_0FDF */

3860 },	4207 {

3861	4208 { Bad_Opcode },

3862 /* PREFIX_VEX_D9 */	4209 { Bad_Opcode },

3863 {	4210 { VEX_W_TABLE (VEX_W_0FDF_P_2) },

3864 { "(bad)", { XX } },	4211 },

3865 { "(bad)", { XX } },	4212

3866 { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },	4213 /* PREFIX_VEX_0FE0 */

3867 { "(bad)", { XX } },	4214 {

3868 },	4215 { Bad_Opcode },

3869	4216 { Bad_Opcode },

3870 /* PREFIX_VEX_DA */	4217 { VEX_W_TABLE (VEX_W_0FE0_P_2) },

3871 {	4218 },

3872 { "(bad)", { XX } },	4219

3873 { "(bad)", { XX } },	4220 /* PREFIX_VEX_0FE1 */

3874 { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },	4221 {

3875 { "(bad)", { XX } },	4222 { Bad_Opcode },

3876 },	4223 { Bad_Opcode },

3877	4224 { VEX_W_TABLE (VEX_W_0FE1_P_2) },

3878 /* PREFIX_VEX_DB */	4225 },

3879 {	4226

3880 { "(bad)", { XX } },	4227 /* PREFIX_VEX_0FE2 */

3881 { "(bad)", { XX } },	4228 {

3882 { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },	4229 { Bad_Opcode },

3883 { "(bad)", { XX } },	4230 { Bad_Opcode },

3884 },	4231 { VEX_W_TABLE (VEX_W_0FE2_P_2) },

3885	4232 },

3886 /* PREFIX_VEX_DC */	4233

3887 {	4234 /* PREFIX_VEX_0FE3 */

3888 { "(bad)", { XX } },	4235 {

3889 { "(bad)", { XX } },	4236 { Bad_Opcode },

3890 { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },	4237 { Bad_Opcode },

3891 { "(bad)", { XX } },	4238 { VEX_W_TABLE (VEX_W_0FE3_P_2) },

3892 },	4239 },

3893	4240

3894 /* PREFIX_VEX_DD */	4241 /* PREFIX_VEX_0FE4 */

3895 {	4242 {

3896 { "(bad)", { XX } },	4243 { Bad_Opcode },

3897 { "(bad)", { XX } },	4244 { Bad_Opcode },

3898 { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },	4245 { VEX_W_TABLE (VEX_W_0FE4_P_2) },

3899 { "(bad)", { XX } },	4246 },

3900 },	4247

3901	4248 /* PREFIX_VEX_0FE5 */

3902 /* PREFIX_VEX_DE */	4249 {

3903 {	4250 { Bad_Opcode },

3904 { "(bad)", { XX } },	4251 { Bad_Opcode },

3905 { "(bad)", { XX } },	4252 { VEX_W_TABLE (VEX_W_0FE5_P_2) },

3906 { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },	4253 },

3907 { "(bad)", { XX } },	4254

3908 },	4255 /* PREFIX_VEX_0FE6 */

3909	4256 {

3910 /* PREFIX_VEX_DF */	4257 { Bad_Opcode },

3911 {	4258 { VEX_W_TABLE (VEX_W_0FE6_P_1) },

3912 { "(bad)", { XX } },	4259 { VEX_W_TABLE (VEX_W_0FE6_P_2) },

3913 { "(bad)", { XX } },	4260 { VEX_W_TABLE (VEX_W_0FE6_P_3) },

3914 { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },	4261 },

3915 { "(bad)", { XX } },	4262

3916 },	4263 /* PREFIX_VEX_0FE7 */

3917	4264 {

3918 /* PREFIX_VEX_E0 */	4265 { Bad_Opcode },

3919 {	4266 { Bad_Opcode },

3920 { "(bad)", { XX } },	4267 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },

3921 { "(bad)", { XX } },	4268 },

3922 { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },	4269

3923 { "(bad)", { XX } },	4270 /* PREFIX_VEX_0FE8 */

3924 },	4271 {

3925	4272 { Bad_Opcode },

3926 /* PREFIX_VEX_E1 */	4273 { Bad_Opcode },

3927 {	4274 { VEX_W_TABLE (VEX_W_0FE8_P_2) },

3928 { "(bad)", { XX } },	4275 },

3929 { "(bad)", { XX } },	4276

3930 { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },	4277 /* PREFIX_VEX_0FE9 */

3931 { "(bad)", { XX } },	4278 {

3932 },	4279 { Bad_Opcode },

3933	4280 { Bad_Opcode },

3934 /* PREFIX_VEX_E2 */	4281 { VEX_W_TABLE (VEX_W_0FE9_P_2) },

3935 {	4282 },

3936 { "(bad)", { XX } },	4283

3937 { "(bad)", { XX } },	4284 /* PREFIX_VEX_0FEA */

3938 { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },	4285 {

3939 { "(bad)", { XX } },	4286 { Bad_Opcode },

3940 },	4287 { Bad_Opcode },

3941	4288 { VEX_W_TABLE (VEX_W_0FEA_P_2) },

3942 /* PREFIX_VEX_E3 */	4289 },

3943 {	4290

3944 { "(bad)", { XX } },	4291 /* PREFIX_VEX_0FEB */

3945 { "(bad)", { XX } },	4292 {

3946 { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },	4293 { Bad_Opcode },

3947 { "(bad)", { XX } },	4294 { Bad_Opcode },

3948 },	4295 { VEX_W_TABLE (VEX_W_0FEB_P_2) },

3949	4296 },

3950 /* PREFIX_VEX_E4 */	4297

3951 {	4298 /* PREFIX_VEX_0FEC */

3952 { "(bad)", { XX } },	4299 {

3953 { "(bad)", { XX } },	4300 { Bad_Opcode },

3954 { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },	4301 { Bad_Opcode },

3955 { "(bad)", { XX } },	4302 { VEX_W_TABLE (VEX_W_0FEC_P_2) },

3956 },	4303 },

3957	4304

3958 /* PREFIX_VEX_E5 */	4305 /* PREFIX_VEX_0FED */

3959 {	4306 {

3960 { "(bad)", { XX } },	4307 { Bad_Opcode },

3961 { "(bad)", { XX } },	4308 { Bad_Opcode },

3962 { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },	4309 { VEX_W_TABLE (VEX_W_0FED_P_2) },

3963 { "(bad)", { XX } },	4310 },

3964 },	4311

3965	4312 /* PREFIX_VEX_0FEE */

3966 /* PREFIX_VEX_E6 */	4313 {

3967 {	4314 { Bad_Opcode },

3968 { "(bad)", { XX } },	4315 { Bad_Opcode },

3969 { "vcvtdq2pd", { XM, EXxmmq } },	4316 { VEX_W_TABLE (VEX_W_0FEE_P_2) },

3970 { "vcvttpd2dq%XY", { XMM, EXx } },	4317 },

3971 { "vcvtpd2dq%XY", { XMM, EXx } },	4318

3972 },	4319 /* PREFIX_VEX_0FEF */

3973	4320 {

3974 /* PREFIX_VEX_E7 */	4321 { Bad_Opcode },

3975 {	4322 { Bad_Opcode },

3976 { "(bad)", { XX } },	4323 { VEX_W_TABLE (VEX_W_0FEF_P_2) },

3977 { "(bad)", { XX } },	4324 },

3978 { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },	4325

3979 { "(bad)", { XX } },	4326 /* PREFIX_VEX_0FF0 */

3980 },	4327 {

3981	4328 { Bad_Opcode },

3982 /* PREFIX_VEX_E8 */	4329 { Bad_Opcode },

3983 {	4330 { Bad_Opcode },

3984 { "(bad)", { XX } },	4331 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },

3985 { "(bad)", { XX } },	4332 },

3986 { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },	4333

3987 { "(bad)", { XX } },	4334 /* PREFIX_VEX_0FF1 */

3988 },	4335 {

3989	4336 { Bad_Opcode },

3990 /* PREFIX_VEX_E9 */	4337 { Bad_Opcode },

3991 {	4338 { VEX_W_TABLE (VEX_W_0FF1_P_2) },

3992 { "(bad)", { XX } },	4339 },

3993 { "(bad)", { XX } },	4340

3994 { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },	4341 /* PREFIX_VEX_0FF2 */

3995 { "(bad)", { XX } },	4342 {

3996 },	4343 { Bad_Opcode },

3997	4344 { Bad_Opcode },

3998 /* PREFIX_VEX_EA */	4345 { VEX_W_TABLE (VEX_W_0FF2_P_2) },

3999 {	4346 },

4000 { "(bad)", { XX } },	4347

4001 { "(bad)", { XX } },	4348 /* PREFIX_VEX_0FF3 */

4002 { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },	4349 {

4003 { "(bad)", { XX } },	4350 { Bad_Opcode },

4004 },	4351 { Bad_Opcode },

4005	4352 { VEX_W_TABLE (VEX_W_0FF3_P_2) },

4006 /* PREFIX_VEX_EB */	4353 },

4007 {	4354

4008 { "(bad)", { XX } },	4355 /* PREFIX_VEX_0FF4 */

4009 { "(bad)", { XX } },	4356 {

4010 { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },	4357 { Bad_Opcode },

4011 { "(bad)", { XX } },	4358 { Bad_Opcode },

4012 },	4359 { VEX_W_TABLE (VEX_W_0FF4_P_2) },

4013	4360 },

4014 /* PREFIX_VEX_EC */	4361

4015 {	4362 /* PREFIX_VEX_0FF5 */

4016 { "(bad)", { XX } },	4363 {

4017 { "(bad)", { XX } },	4364 { Bad_Opcode },

4018 { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },	4365 { Bad_Opcode },

4019 { "(bad)", { XX } },	4366 { VEX_W_TABLE (VEX_W_0FF5_P_2) },

4020 },	4367 },

4021	4368

4022 /* PREFIX_VEX_ED */	4369 /* PREFIX_VEX_0FF6 */

4023 {	4370 {

4024 { "(bad)", { XX } },	4371 { Bad_Opcode },

4025 { "(bad)", { XX } },	4372 { Bad_Opcode },

4026 { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },	4373 { VEX_W_TABLE (VEX_W_0FF6_P_2) },

4027 { "(bad)", { XX } },	4374 },

4028 },	4375

4029	4376 /* PREFIX_VEX_0FF7 */

4030 /* PREFIX_VEX_EE */	4377 {

4031 {	4378 { Bad_Opcode },

4032 { "(bad)", { XX } },	4379 { Bad_Opcode },

4033 { "(bad)", { XX } },	4380 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },

4034 { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },	4381 },

4035 { "(bad)", { XX } },	4382

4036 },	4383 /* PREFIX_VEX_0FF8 */

4037	4384 {

4038 /* PREFIX_VEX_EF */	4385 { Bad_Opcode },

4039 {	4386 { Bad_Opcode },

4040 { "(bad)", { XX } },	4387 { VEX_W_TABLE (VEX_W_0FF8_P_2) },

4041 { "(bad)", { XX } },	4388 },

4042 { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },	4389

4043 { "(bad)", { XX } },	4390 /* PREFIX_VEX_0FF9 */

4044 },	4391 {

4045	4392 { Bad_Opcode },

4046 /* PREFIX_VEX_F0 */	4393 { Bad_Opcode },

4047 {	4394 { VEX_W_TABLE (VEX_W_0FF9_P_2) },

4048 { "(bad)", { XX } },	4395 },

4049 { "(bad)", { XX } },	4396

4050 { "(bad)", { XX } },	4397 /* PREFIX_VEX_0FFA */

4051 { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },	4398 {

4052 },	4399 { Bad_Opcode },

4053	4400 { Bad_Opcode },

4054 /* PREFIX_VEX_F1 */	4401 { VEX_W_TABLE (VEX_W_0FFA_P_2) },

4055 {	4402 },

4056 { "(bad)", { XX } },	4403

4057 { "(bad)", { XX } },	4404 /* PREFIX_VEX_0FFB */

4058 { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },	4405 {

4059 { "(bad)", { XX } },	4406 { Bad_Opcode },

4060 },	4407 { Bad_Opcode },

4061	4408 { VEX_W_TABLE (VEX_W_0FFB_P_2) },

4062 /* PREFIX_VEX_F2 */	4409 },

4063 {	4410

4064 { "(bad)", { XX } },	4411 /* PREFIX_VEX_0FFC */

4065 { "(bad)", { XX } },	4412 {

4066 { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },	4413 { Bad_Opcode },

4067 { "(bad)", { XX } },	4414 { Bad_Opcode },

4068 },	4415 { VEX_W_TABLE (VEX_W_0FFC_P_2) },

4069	4416 },

4070 /* PREFIX_VEX_F3 */	4417

4071 {	4418 /* PREFIX_VEX_0FFD */

4072 { "(bad)", { XX } },	4419 {

4073 { "(bad)", { XX } },	4420 { Bad_Opcode },

4074 { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },	4421 { Bad_Opcode },

4075 { "(bad)", { XX } },	4422 { VEX_W_TABLE (VEX_W_0FFD_P_2) },

4076 },	4423 },

4077	4424

4078 /* PREFIX_VEX_F4 */	4425 /* PREFIX_VEX_0FFE */

4079 {	4426 {

4080 { "(bad)", { XX } },	4427 { Bad_Opcode },

4081 { "(bad)", { XX } },	4428 { Bad_Opcode },

4082 { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },	4429 { VEX_W_TABLE (VEX_W_0FFE_P_2) },

4083 { "(bad)", { XX } },	4430 },

4084 },	4431

4085	4432 /* PREFIX_VEX_0F3800 */

4086 /* PREFIX_VEX_F5 */	4433 {

4087 {	4434 { Bad_Opcode },

4088 { "(bad)", { XX } },	4435 { Bad_Opcode },

4089 { "(bad)", { XX } },	4436 { VEX_W_TABLE (VEX_W_0F3800_P_2) },

4090 { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },	4437 },

4091 { "(bad)", { XX } },	4438

4092 },	4439 /* PREFIX_VEX_0F3801 */

4093	4440 {

4094 /* PREFIX_VEX_F6 */	4441 { Bad_Opcode },

4095 {	4442 { Bad_Opcode },

4096 { "(bad)", { XX } },	4443 { VEX_W_TABLE (VEX_W_0F3801_P_2) },

4097 { "(bad)", { XX } },	4444 },

4098 { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },	4445

4099 { "(bad)", { XX } },	4446 /* PREFIX_VEX_0F3802 */

4100 },	4447 {

4101	4448 { Bad_Opcode },

4102 /* PREFIX_VEX_F7 */	4449 { Bad_Opcode },

4103 {	4450 { VEX_W_TABLE (VEX_W_0F3802_P_2) },

4104 { "(bad)", { XX } },	4451 },

4105 { "(bad)", { XX } },	4452

4106 { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },	4453 /* PREFIX_VEX_0F3803 */

4107 { "(bad)", { XX } },	4454 {

4108 },	4455 { Bad_Opcode },

4109	4456 { Bad_Opcode },

4110 /* PREFIX_VEX_F8 */	4457 { VEX_W_TABLE (VEX_W_0F3803_P_2) },

4111 {	4458 },

4112 { "(bad)", { XX } },	4459

4113 { "(bad)", { XX } },	4460 /* PREFIX_VEX_0F3804 */

4114 { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },	4461 {

4115 { "(bad)", { XX } },	4462 { Bad_Opcode },

4116 },	4463 { Bad_Opcode },

4117	4464 { VEX_W_TABLE (VEX_W_0F3804_P_2) },

4118 /* PREFIX_VEX_F9 */	4465 },

4119 {	4466

4120 { "(bad)", { XX } },	4467 /* PREFIX_VEX_0F3805 */

4121 { "(bad)", { XX } },	4468 {

4122 { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },	4469 { Bad_Opcode },

4123 { "(bad)", { XX } },	4470 { Bad_Opcode },

4124 },	4471 { VEX_W_TABLE (VEX_W_0F3805_P_2) },

4125	4472 },

4126 /* PREFIX_VEX_FA */	4473

4127 {	4474 /* PREFIX_VEX_0F3806 */

4128 { "(bad)", { XX } },	4475 {

4129 { "(bad)", { XX } },	4476 { Bad_Opcode },

4130 { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },	4477 { Bad_Opcode },

4131 { "(bad)", { XX } },	4478 { VEX_W_TABLE (VEX_W_0F3806_P_2) },

4132 },	4479 },

4133	4480

4134 /* PREFIX_VEX_FB */	4481 /* PREFIX_VEX_0F3807 */

4135 {	4482 {

4136 { "(bad)", { XX } },	4483 { Bad_Opcode },

4137 { "(bad)", { XX } },	4484 { Bad_Opcode },

4138 { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },	4485 { VEX_W_TABLE (VEX_W_0F3807_P_2) },

4139 { "(bad)", { XX } },	4486 },

4140 },	4487

4141	4488 /* PREFIX_VEX_0F3808 */

4142 /* PREFIX_VEX_FC */	4489 {

4143 {	4490 { Bad_Opcode },

4144 { "(bad)", { XX } },	4491 { Bad_Opcode },

4145 { "(bad)", { XX } },	4492 { VEX_W_TABLE (VEX_W_0F3808_P_2) },

4146 { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },	4493 },

4147 { "(bad)", { XX } },	4494

4148 },	4495 /* PREFIX_VEX_0F3809 */

4149	4496 {

4150 /* PREFIX_VEX_FD */	4497 { Bad_Opcode },

4151 {	4498 { Bad_Opcode },

4152 { "(bad)", { XX } },	4499 { VEX_W_TABLE (VEX_W_0F3809_P_2) },

4153 { "(bad)", { XX } },	4500 },

4154 { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },	4501

4155 { "(bad)", { XX } },	4502 /* PREFIX_VEX_0F380A */

4156 },	4503 {

4157	4504 { Bad_Opcode },

4158 /* PREFIX_VEX_FE */	4505 { Bad_Opcode },

4159 {	4506 { VEX_W_TABLE (VEX_W_0F380A_P_2) },

4160 { "(bad)", { XX } },	4507 },

4161 { "(bad)", { XX } },	4508

4162 { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },	4509 /* PREFIX_VEX_0F380B */

4163 { "(bad)", { XX } },	4510 {

4164 },	4511 { Bad_Opcode },

4165	4512 { Bad_Opcode },

4166 /* PREFIX_VEX_3800 */	4513 { VEX_W_TABLE (VEX_W_0F380B_P_2) },

4167 {	4514 },

4168 { "(bad)", { XX } },	4515

4169 { "(bad)", { XX } },	4516 /* PREFIX_VEX_0F380C */

4170 { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },	4517 {

4171 { "(bad)", { XX } },	4518 { Bad_Opcode },

4172 },	4519 { Bad_Opcode },

4173	4520 { VEX_W_TABLE (VEX_W_0F380C_P_2) },

4174 /* PREFIX_VEX_3801 */	4521 },

4175 {	4522

4176 { "(bad)", { XX } },	4523 /* PREFIX_VEX_0F380D */

4177 { "(bad)", { XX } },	4524 {

4178 { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },	4525 { Bad_Opcode },

4179 { "(bad)", { XX } },	4526 { Bad_Opcode },

4180 },	4527 { VEX_W_TABLE (VEX_W_0F380D_P_2) },

4181	4528 },

4182 /* PREFIX_VEX_3802 */	4529

4183 {	4530 /* PREFIX_VEX_0F380E */

4184 { "(bad)", { XX } },	4531 {

4185 { "(bad)", { XX } },	4532 { Bad_Opcode },

4186 { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },	4533 { Bad_Opcode },

4187 { "(bad)", { XX } },	4534 { VEX_W_TABLE (VEX_W_0F380E_P_2) },

4188 },	4535 },

4189	4536

4190 /* PREFIX_VEX_3803 */	4537 /* PREFIX_VEX_0F380F */

4191 {	4538 {

4192 { "(bad)", { XX } },	4539 { Bad_Opcode },

4193 { "(bad)", { XX } },	4540 { Bad_Opcode },

4194 { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },	4541 { VEX_W_TABLE (VEX_W_0F380F_P_2) },

4195 { "(bad)", { XX } },	4542 },

4196 },	4543

4197	4544 /* PREFIX_VEX_0F3813 */

4198 /* PREFIX_VEX_3804 */	4545 {

4199 {	4546 { Bad_Opcode },

4200 { "(bad)", { XX } },	4547 { Bad_Opcode },

4201 { "(bad)", { XX } },	4548 { "vcvtph2ps", { XM, EXxmmq } },

4202 { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },	4549 },

4203 { "(bad)", { XX } },	4550

4204 },	4551 /* PREFIX_VEX_0F3816 */

4205	4552 {

4206 /* PREFIX_VEX_3805 */	4553 { Bad_Opcode },

4207 {	4554 { Bad_Opcode },

4208 { "(bad)", { XX } },	4555 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },

4209 { "(bad)", { XX } },	4556 },

4210 { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },	4557

4211 { "(bad)", { XX } },	4558 /* PREFIX_VEX_0F3817 */

4212 },	4559 {

4213	4560 { Bad_Opcode },

4214 /* PREFIX_VEX_3806 */	4561 { Bad_Opcode },

4215 {	4562 { VEX_W_TABLE (VEX_W_0F3817_P_2) },

4216 { "(bad)", { XX } },	4563 },

4217 { "(bad)", { XX } },	4564

4218 { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },	4565 /* PREFIX_VEX_0F3818 */

4219 { "(bad)", { XX } },	4566 {

4220 },	4567 { Bad_Opcode },

4221	4568 { Bad_Opcode },

4222 /* PREFIX_VEX_3807 */	4569 { VEX_W_TABLE (VEX_W_0F3818_P_2) },

4223 {	4570 },

4224 { "(bad)", { XX } },	4571

4225 { "(bad)", { XX } },	4572 /* PREFIX_VEX_0F3819 */

4226 { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },	4573 {

4227 { "(bad)", { XX } },	4574 { Bad_Opcode },

4228 },	4575 { Bad_Opcode },

4229	4576 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },

4230 /* PREFIX_VEX_3808 */	4577 },

4231 {	4578

4232 { "(bad)", { XX } },	4579 /* PREFIX_VEX_0F381A */

4233 { "(bad)", { XX } },	4580 {

4234 { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },	4581 { Bad_Opcode },

4235 { "(bad)", { XX } },	4582 { Bad_Opcode },

4236 },	4583 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },

4237	4584 },

4238 /* PREFIX_VEX_3809 */	4585

4239 {	4586 /* PREFIX_VEX_0F381C */

4240 { "(bad)", { XX } },	4587 {

4241 { "(bad)", { XX } },	4588 { Bad_Opcode },

4242 { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },	4589 { Bad_Opcode },

4243 { "(bad)", { XX } },	4590 { VEX_W_TABLE (VEX_W_0F381C_P_2) },

4244 },	4591 },

4245	4592

4246 /* PREFIX_VEX_380A */	4593 /* PREFIX_VEX_0F381D */

4247 {	4594 {

4248 { "(bad)", { XX } },	4595 { Bad_Opcode },

4249 { "(bad)", { XX } },	4596 { Bad_Opcode },

4250 { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },	4597 { VEX_W_TABLE (VEX_W_0F381D_P_2) },

4251 { "(bad)", { XX } },	4598 },

4252 },	4599

4253	4600 /* PREFIX_VEX_0F381E */

4254 /* PREFIX_VEX_380B */	4601 {

4255 {	4602 { Bad_Opcode },

4256 { "(bad)", { XX } },	4603 { Bad_Opcode },

4257 { "(bad)", { XX } },	4604 { VEX_W_TABLE (VEX_W_0F381E_P_2) },

4258 { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },	4605 },

4259 { "(bad)", { XX } },	4606

4260 },	4607 /* PREFIX_VEX_0F3820 */

4261	4608 {

4262 /* PREFIX_VEX_380C */	4609 { Bad_Opcode },

4263 {	4610 { Bad_Opcode },

4264 { "(bad)", { XX } },	4611 { VEX_W_TABLE (VEX_W_0F3820_P_2) },

4265 { "(bad)", { XX } },	4612 },

4266 { "vpermilps", { XM, Vex, EXx } },	4613

4267 { "(bad)", { XX } },	4614 /* PREFIX_VEX_0F3821 */

4268 },	4615 {

4269	4616 { Bad_Opcode },

4270 /* PREFIX_VEX_380D */	4617 { Bad_Opcode },

4271 {	4618 { VEX_W_TABLE (VEX_W_0F3821_P_2) },

4272 { "(bad)", { XX } },	4619 },

4273 { "(bad)", { XX } },	4620

4274 { "vpermilpd", { XM, Vex, EXx } },	4621 /* PREFIX_VEX_0F3822 */

4275 { "(bad)", { XX } },	4622 {

4276 },	4623 { Bad_Opcode },

4277	4624 { Bad_Opcode },

4278 /* PREFIX_VEX_380E */	4625 { VEX_W_TABLE (VEX_W_0F3822_P_2) },

4279 {	4626 },

4280 { "(bad)", { XX } },	4627

4281 { "(bad)", { XX } },	4628 /* PREFIX_VEX_0F3823 */

4282 { "vtestps", { XM, EXx } },	4629 {

4283 { "(bad)", { XX } },	4630 { Bad_Opcode },

4284 },	4631 { Bad_Opcode },

4285	4632 { VEX_W_TABLE (VEX_W_0F3823_P_2) },

4286 /* PREFIX_VEX_380F */	4633 },

4287 {	4634

4288 { "(bad)", { XX } },	4635 /* PREFIX_VEX_0F3824 */

4289 { "(bad)", { XX } },	4636 {

4290 { "vtestpd", { XM, EXx } },	4637 { Bad_Opcode },

4291 { "(bad)", { XX } },	4638 { Bad_Opcode },

4292 },	4639 { VEX_W_TABLE (VEX_W_0F3824_P_2) },

4293	4640 },

4294 /* PREFIX_VEX_3817 */	4641

4295 {	4642 /* PREFIX_VEX_0F3825 */

4296 { "(bad)", { XX } },	4643 {

4297 { "(bad)", { XX } },	4644 { Bad_Opcode },

4298 { "vptest", { XM, EXx } },	4645 { Bad_Opcode },

4299 { "(bad)", { XX } },	4646 { VEX_W_TABLE (VEX_W_0F3825_P_2) },

4300 },	4647 },

4301	4648

4302 /* PREFIX_VEX_3818 */	4649 /* PREFIX_VEX_0F3828 */

4303 {	4650 {

4304 { "(bad)", { XX } },	4651 { Bad_Opcode },

4305 { "(bad)", { XX } },	4652 { Bad_Opcode },

4306 { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },	4653 { VEX_W_TABLE (VEX_W_0F3828_P_2) },

4307 { "(bad)", { XX } },	4654 },

4308 },	4655

4309	4656 /* PREFIX_VEX_0F3829 */

4310 /* PREFIX_VEX_3819 */	4657 {

4311 {	4658 { Bad_Opcode },

4312 { "(bad)", { XX } },	4659 { Bad_Opcode },

4313 { "(bad)", { XX } },	4660 { VEX_W_TABLE (VEX_W_0F3829_P_2) },

4314 { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },	4661 },

4315 { "(bad)", { XX } },	4662

4316 },	4663 /* PREFIX_VEX_0F382A */

4317	4664 {

4318 /* PREFIX_VEX_381A */	4665 { Bad_Opcode },

4319 {	4666 { Bad_Opcode },

4320 { "(bad)", { XX } },	4667 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },

4321 { "(bad)", { XX } },	4668 },

4322 { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },	4669

4323 { "(bad)", { XX } },	4670 /* PREFIX_VEX_0F382B */

4324 },	4671 {

4325	4672 { Bad_Opcode },

4326 /* PREFIX_VEX_381C */	4673 { Bad_Opcode },

4327 {	4674 { VEX_W_TABLE (VEX_W_0F382B_P_2) },

4328 { "(bad)", { XX } },	4675 },

4329 { "(bad)", { XX } },	4676

4330 { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },	4677 /* PREFIX_VEX_0F382C */

4331 { "(bad)", { XX } },	4678 {

4332 },	4679 { Bad_Opcode },

4333	4680 { Bad_Opcode },

4334 /* PREFIX_VEX_381D */	4681 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },

4335 {	4682 },

4336 { "(bad)", { XX } },	4683

4337 { "(bad)", { XX } },	4684 /* PREFIX_VEX_0F382D */

4338 { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },	4685 {

4339 { "(bad)", { XX } },	4686 { Bad_Opcode },

4340 },	4687 { Bad_Opcode },

4341	4688 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },

4342 /* PREFIX_VEX_381E */	4689 },

4343 {	4690

4344 { "(bad)", { XX } },	4691 /* PREFIX_VEX_0F382E */

4345 { "(bad)", { XX } },	4692 {

4346 { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },	4693 { Bad_Opcode },

4347 { "(bad)", { XX } },	4694 { Bad_Opcode },

4348 },	4695 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },

4349	4696 },

4350 /* PREFIX_VEX_3820 */	4697

4351 {	4698 /* PREFIX_VEX_0F382F */

4352 { "(bad)", { XX } },	4699 {

4353 { "(bad)", { XX } },	4700 { Bad_Opcode },

4354 { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },	4701 { Bad_Opcode },

4355 { "(bad)", { XX } },	4702 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },

4356 },	4703 },

4357	4704

4358 /* PREFIX_VEX_3821 */	4705 /* PREFIX_VEX_0F3830 */

4359 {	4706 {

4360 { "(bad)", { XX } },	4707 { Bad_Opcode },

4361 { "(bad)", { XX } },	4708 { Bad_Opcode },

4362 { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },	4709 { VEX_W_TABLE (VEX_W_0F3830_P_2) },

4363 { "(bad)", { XX } },	4710 },

4364 },	4711

4365	4712 /* PREFIX_VEX_0F3831 */

4366 /* PREFIX_VEX_3822 */	4713 {

4367 {	4714 { Bad_Opcode },

4368 { "(bad)", { XX } },	4715 { Bad_Opcode },

4369 { "(bad)", { XX } },	4716 { VEX_W_TABLE (VEX_W_0F3831_P_2) },

4370 { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },	4717 },

4371 { "(bad)", { XX } },	4718

4372 },	4719 /* PREFIX_VEX_0F3832 */

4373	4720 {

4374 /* PREFIX_VEX_3823 */	4721 { Bad_Opcode },

4375 {	4722 { Bad_Opcode },

4376 { "(bad)", { XX } },	4723 { VEX_W_TABLE (VEX_W_0F3832_P_2) },

4377 { "(bad)", { XX } },	4724 },

4378 { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },	4725

4379 { "(bad)", { XX } },	4726 /* PREFIX_VEX_0F3833 */

4380 },	4727 {

4381	4728 { Bad_Opcode },

4382 /* PREFIX_VEX_3824 */	4729 { Bad_Opcode },

4383 {	4730 { VEX_W_TABLE (VEX_W_0F3833_P_2) },

4384 { "(bad)", { XX } },	4731 },

4385 { "(bad)", { XX } },	4732

4386 { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },	4733 /* PREFIX_VEX_0F3834 */

4387 { "(bad)", { XX } },	4734 {

4388 },	4735 { Bad_Opcode },

4389	4736 { Bad_Opcode },

4390 /* PREFIX_VEX_3825 */	4737 { VEX_W_TABLE (VEX_W_0F3834_P_2) },

4391 {	4738 },

4392 { "(bad)", { XX } },	4739

4393 { "(bad)", { XX } },	4740 /* PREFIX_VEX_0F3835 */

4394 { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },	4741 {

4395 { "(bad)", { XX } },	4742 { Bad_Opcode },

4396 },	4743 { Bad_Opcode },

4397	4744 { VEX_W_TABLE (VEX_W_0F3835_P_2) },

4398 /* PREFIX_VEX_3828 */	4745 },

4399 {	4746

4400 { "(bad)", { XX } },	4747 /* PREFIX_VEX_0F3836 */

4401 { "(bad)", { XX } },	4748 {

4402 { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },	4749 { Bad_Opcode },

4403 { "(bad)", { XX } },	4750 { Bad_Opcode },

4404 },	4751 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },

4405	4752 },

4406 /* PREFIX_VEX_3829 */	4753

4407 {	4754 /* PREFIX_VEX_0F3837 */

4408 { "(bad)", { XX } },	4755 {

4409 { "(bad)", { XX } },	4756 { Bad_Opcode },

4410 { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },	4757 { Bad_Opcode },

4411 { "(bad)", { XX } },	4758 { VEX_W_TABLE (VEX_W_0F3837_P_2) },

4412 },	4759 },

4413	4760

4414 /* PREFIX_VEX_382A */	4761 /* PREFIX_VEX_0F3838 */

4415 {	4762 {

4416 { "(bad)", { XX } },	4763 { Bad_Opcode },

4417 { "(bad)", { XX } },	4764 { Bad_Opcode },

4418 { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },	4765 { VEX_W_TABLE (VEX_W_0F3838_P_2) },

4419 { "(bad)", { XX } },	4766 },

4420 },	4767

4421	4768 /* PREFIX_VEX_0F3839 */

4422 /* PREFIX_VEX_382B */	4769 {

4423 {	4770 { Bad_Opcode },

4424 { "(bad)", { XX } },	4771 { Bad_Opcode },

4425 { "(bad)", { XX } },	4772 { VEX_W_TABLE (VEX_W_0F3839_P_2) },

4426 { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },	4773 },

4427 { "(bad)", { XX } },	4774

4428 },	4775 /* PREFIX_VEX_0F383A */

4429	4776 {

4430 /* PREFIX_VEX_382C */	4777 { Bad_Opcode },

4431 {	4778 { Bad_Opcode },

4432 { "(bad)", { XX } },	4779 { VEX_W_TABLE (VEX_W_0F383A_P_2) },

4433 { "(bad)", { XX } },	4780 },

4434 { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },	4781

4435 { "(bad)", { XX } },	4782 /* PREFIX_VEX_0F383B */

4436 },	4783 {

4437	4784 { Bad_Opcode },

4438 /* PREFIX_VEX_382D */	4785 { Bad_Opcode },

4439 {	4786 { VEX_W_TABLE (VEX_W_0F383B_P_2) },

4440 { "(bad)", { XX } },	4787 },

4441 { "(bad)", { XX } },	4788

4442 { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },	4789 /* PREFIX_VEX_0F383C */

4443 { "(bad)", { XX } },	4790 {

4444 },	4791 { Bad_Opcode },

4445	4792 { Bad_Opcode },

4446 /* PREFIX_VEX_382E */	4793 { VEX_W_TABLE (VEX_W_0F383C_P_2) },

4447 {	4794 },

4448 { "(bad)", { XX } },	4795

4449 { "(bad)", { XX } },	4796 /* PREFIX_VEX_0F383D */

4450 { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },	4797 {

4451 { "(bad)", { XX } },	4798 { Bad_Opcode },

4452 },	4799 { Bad_Opcode },

4453	4800 { VEX_W_TABLE (VEX_W_0F383D_P_2) },

4454 /* PREFIX_VEX_382F */	4801 },

4455 {	4802

4456 { "(bad)", { XX } },	4803 /* PREFIX_VEX_0F383E */

4457 { "(bad)", { XX } },	4804 {

4458 { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },	4805 { Bad_Opcode },

4459 { "(bad)", { XX } },	4806 { Bad_Opcode },

4460 },	4807 { VEX_W_TABLE (VEX_W_0F383E_P_2) },

4461	4808 },

4462 /* PREFIX_VEX_3830 */	4809

4463 {	4810 /* PREFIX_VEX_0F383F */

4464 { "(bad)", { XX } },	4811 {

4465 { "(bad)", { XX } },	4812 { Bad_Opcode },

4466 { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },	4813 { Bad_Opcode },

4467 { "(bad)", { XX } },	4814 { VEX_W_TABLE (VEX_W_0F383F_P_2) },

4468 },	4815 },

4469	4816

4470 /* PREFIX_VEX_3831 */	4817 /* PREFIX_VEX_0F3840 */

4471 {	4818 {

4472 { "(bad)", { XX } },	4819 { Bad_Opcode },

4473 { "(bad)", { XX } },	4820 { Bad_Opcode },

4474 { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },	4821 { VEX_W_TABLE (VEX_W_0F3840_P_2) },

4475 { "(bad)", { XX } },	4822 },

4476 },	4823

4477	4824 /* PREFIX_VEX_0F3841 */

4478 /* PREFIX_VEX_3832 */	4825 {

4479 {	4826 { Bad_Opcode },

4480 { "(bad)", { XX } },	4827 { Bad_Opcode },

4481 { "(bad)", { XX } },	4828 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },

4482 { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },	4829 },

4483 { "(bad)", { XX } },	4830

4484 },	4831 /* PREFIX_VEX_0F3845 */

4485	4832 {

4486 /* PREFIX_VEX_3833 */	4833 { Bad_Opcode },

4487 {	4834 { Bad_Opcode },

4488 { "(bad)", { XX } },	4835 { "vpsrlv%LW", { XM, Vex, EXx } },

4489 { "(bad)", { XX } },	4836 },

4490 { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },	4837

4491 { "(bad)", { XX } },	4838 /* PREFIX_VEX_0F3846 */

4492 },	4839 {

4493	4840 { Bad_Opcode },

4494 /* PREFIX_VEX_3834 */	4841 { Bad_Opcode },

4495 {	4842 { VEX_W_TABLE (VEX_W_0F3846_P_2) },

4496 { "(bad)", { XX } },	4843 },

4497 { "(bad)", { XX } },	4844

4498 { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },	4845 /* PREFIX_VEX_0F3847 */

4499 { "(bad)", { XX } },	4846 {

4500 },	4847 { Bad_Opcode },

4501	4848 { Bad_Opcode },

4502 /* PREFIX_VEX_3835 */	4849 { "vpsllv%LW", { XM, Vex, EXx } },

4503 {	4850 },

4504 { "(bad)", { XX } },	4851

4505 { "(bad)", { XX } },	4852 /* PREFIX_VEX_0F3858 */

4506 { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },	4853 {

4507 { "(bad)", { XX } },	4854 { Bad_Opcode },

4508 },	4855 { Bad_Opcode },

4509	4856 { VEX_W_TABLE (VEX_W_0F3858_P_2) },

4510 /* PREFIX_VEX_3837 */	4857 },

4511 {	4858

4512 { "(bad)", { XX } },	4859 /* PREFIX_VEX_0F3859 */

4513 { "(bad)", { XX } },	4860 {

4514 { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },	4861 { Bad_Opcode },

4515 { "(bad)", { XX } },	4862 { Bad_Opcode },

4516 },	4863 { VEX_W_TABLE (VEX_W_0F3859_P_2) },

4517	4864 },

4518 /* PREFIX_VEX_3838 */	4865

4519 {	4866 /* PREFIX_VEX_0F385A */

4520 { "(bad)", { XX } },	4867 {

4521 { "(bad)", { XX } },	4868 { Bad_Opcode },

4522 { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },	4869 { Bad_Opcode },

4523 { "(bad)", { XX } },	4870 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },

4524 },	4871 },

4525	4872

4526 /* PREFIX_VEX_3839 */	4873 /* PREFIX_VEX_0F3878 */

4527 {	4874 {

4528 { "(bad)", { XX } },	4875 { Bad_Opcode },

4529 { "(bad)", { XX } },	4876 { Bad_Opcode },

4530 { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },	4877 { VEX_W_TABLE (VEX_W_0F3878_P_2) },

4531 { "(bad)", { XX } },	4878 },

4532 },	4879

4533	4880 /* PREFIX_VEX_0F3879 */

4534 /* PREFIX_VEX_383A */	4881 {

4535 {	4882 { Bad_Opcode },

4536 { "(bad)", { XX } },	4883 { Bad_Opcode },

4537 { "(bad)", { XX } },	4884 { VEX_W_TABLE (VEX_W_0F3879_P_2) },

4538 { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },	4885 },

4539 { "(bad)", { XX } },	4886

4540 },	4887 /* PREFIX_VEX_0F388C */

4541	4888 {

4542 /* PREFIX_VEX_383B */	4889 { Bad_Opcode },

4543 {	4890 { Bad_Opcode },

4544 { "(bad)", { XX } },	4891 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },

4545 { "(bad)", { XX } },	4892 },

4546 { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },	4893

4547 { "(bad)", { XX } },	4894 /* PREFIX_VEX_0F388E */

4548 },	4895 {

4549	4896 { Bad_Opcode },

4550 /* PREFIX_VEX_383C */	4897 { Bad_Opcode },

4551 {	4898 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },

4552 { "(bad)", { XX } },	4899 },

4553 { "(bad)", { XX } },	4900

4554 { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },	4901 /* PREFIX_VEX_0F3890 */

4555 { "(bad)", { XX } },	4902 {

4556 },	4903 { Bad_Opcode },

4557	4904 { Bad_Opcode },

4558 /* PREFIX_VEX_383D */	4905 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },

4559 {	4906 },

4560 { "(bad)", { XX } },	4907

4561 { "(bad)", { XX } },	4908 /* PREFIX_VEX_0F3891 */

4562 { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },	4909 {

4563 { "(bad)", { XX } },	4910 { Bad_Opcode },

4564 },	4911 { Bad_Opcode },

4565	4912 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },

4566 /* PREFIX_VEX_383E */	4913 },

4567 {	4914

4568 { "(bad)", { XX } },	4915 /* PREFIX_VEX_0F3892 */

4569 { "(bad)", { XX } },	4916 {

4570 { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },	4917 { Bad_Opcode },

4571 { "(bad)", { XX } },	4918 { Bad_Opcode },

4572 },	4919 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },

4573	4920 },

4574 /* PREFIX_VEX_383F */	4921

4575 {	4922 /* PREFIX_VEX_0F3893 */

4576 { "(bad)", { XX } },	4923 {

4577 { "(bad)", { XX } },	4924 { Bad_Opcode },

4578 { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },	4925 { Bad_Opcode },

4579 { "(bad)", { XX } },	4926 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },

4580 },	4927 },

4581	4928

4582 /* PREFIX_VEX_3840 */	4929 /* PREFIX_VEX_0F3896 */

4583 {	4930 {

4584 { "(bad)", { XX } },	4931 { Bad_Opcode },

4585 { "(bad)", { XX } },	4932 { Bad_Opcode },

4586 { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },

4587 { "(bad)", { XX } },

4588 },

4589

4590 /* PREFIX_VEX_3841 */

4591 {

4592 { "(bad)", { XX } },

4593 { "(bad)", { XX } },

4594 { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },

4595 { "(bad)", { XX } },

4596 },

4597

4598 /* PREFIX_VEX_3896 */

4599 {

4600 { "(bad)", { XX } },

4601 { "(bad)", { XX } },

4602 { "vfmaddsub132p%XW", { XM, Vex, EXx } },	4933 { "vfmaddsub132p%XW", { XM, Vex, EXx } },

4603 { "(bad)",» { XX } },	4934 },

4604 },	4935

4605	4936 /* PREFIX_VEX_0F3897 */

4606 /* PREFIX_VEX_3897 */	4937 {

4607 {	4938 { Bad_Opcode },

4608 { "(bad)",» { XX } },	4939 { Bad_Opcode },

4609 { "(bad)",» { XX } },

4610 { "vfmsubadd132p%XW", { XM, Vex, EXx } },	4940 { "vfmsubadd132p%XW", { XM, Vex, EXx } },

4611 { "(bad)",» { XX } },	4941 },

4612 },	4942

4613	4943 /* PREFIX_VEX_0F3898 */

4614 /* PREFIX_VEX_3898 */	4944 {

4615 {	4945 { Bad_Opcode },

4616 { "(bad)",» { XX } },	4946 { Bad_Opcode },

4617 { "(bad)",» { XX } },

4618 { "vfmadd132p%XW", { XM, Vex, EXx } },	4947 { "vfmadd132p%XW", { XM, Vex, EXx } },

4619 { "(bad)",» { XX } },	4948 },

4620 },	4949

4621	4950 /* PREFIX_VEX_0F3899 */

4622 /* PREFIX_VEX_3899 */	4951 {

4623 {	4952 { Bad_Opcode },

4624 { "(bad)",» { XX } },	4953 { Bad_Opcode },

4625 { "(bad)",» { XX } },	4954 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },

4626 { "vfmadd132s%XW", { XM, Vex, EXVexWdq } },	4955 },

4627 { "(bad)",» { XX } },	4956

4628 },	4957 /* PREFIX_VEX_0F389A */

4629	4958 {

4630 /* PREFIX_VEX_389A */	4959 { Bad_Opcode },

4631 {	4960 { Bad_Opcode },

4632 { "(bad)",» { XX } },

4633 { "(bad)",» { XX } },

4634 { "vfmsub132p%XW", { XM, Vex, EXx } },	4961 { "vfmsub132p%XW", { XM, Vex, EXx } },

4635 { "(bad)",» { XX } },	4962 },

4636 },	4963

4637	4964 /* PREFIX_VEX_0F389B */

4638 /* PREFIX_VEX_389B */	4965 {

4639 {	4966 { Bad_Opcode },

4640 { "(bad)",» { XX } },	4967 { Bad_Opcode },

4641 { "(bad)",» { XX } },	4968 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },

4642 { "vfmsub132s%XW", { XM, Vex, EXVexWdq } },	4969 },

4643 { "(bad)",» { XX } },	4970

4644 },	4971 /* PREFIX_VEX_0F389C */

4645	4972 {

4646 /* PREFIX_VEX_389C */	4973 { Bad_Opcode },

4647 {	4974 { Bad_Opcode },

4648 { "(bad)",» { XX } },

4649 { "(bad)",» { XX } },

4650 { "vfnmadd132p%XW", { XM, Vex, EXx } },	4975 { "vfnmadd132p%XW", { XM, Vex, EXx } },

4651 { "(bad)",» { XX } },	4976 },

4652 },	4977

4653	4978 /* PREFIX_VEX_0F389D */

4654 /* PREFIX_VEX_389D */	4979 {

4655 {	4980 { Bad_Opcode },

4656 { "(bad)",» { XX } },	4981 { Bad_Opcode },

4657 { "(bad)",» { XX } },	4982 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },

4658 { "vfnmadd132s%XW", { XM, Vex, EXVexWdq } },	4983 },

4659 { "(bad)",» { XX } },	4984

4660 },	4985 /* PREFIX_VEX_0F389E */

4661	4986 {

4662 /* PREFIX_VEX_389E */	4987 { Bad_Opcode },

4663 {	4988 { Bad_Opcode },

4664 { "(bad)",» { XX } },

4665 { "(bad)",» { XX } },

4666 { "vfnmsub132p%XW", { XM, Vex, EXx } },	4989 { "vfnmsub132p%XW", { XM, Vex, EXx } },

4667 { "(bad)",» { XX } },	4990 },

4668 },	4991

4669	4992 /* PREFIX_VEX_0F389F */

4670 /* PREFIX_VEX_389F */	4993 {

4671 {	4994 { Bad_Opcode },

4672 { "(bad)",» { XX } },	4995 { Bad_Opcode },

4673 { "(bad)",» { XX } },	4996 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },

4674 { "vfnmsub132s%XW", { XM, Vex, EXVexWdq } },	4997 },

4675 { "(bad)",» { XX } },	4998

4676 },	4999 /* PREFIX_VEX_0F38A6 */

4677	5000 {

4678 /* PREFIX_VEX_38A6 */	5001 { Bad_Opcode },

4679 {	5002 { Bad_Opcode },

4680 { "(bad)",» { XX } },

4681 { "(bad)",» { XX } },

4682 { "vfmaddsub213p%XW", { XM, Vex, EXx } },	5003 { "vfmaddsub213p%XW", { XM, Vex, EXx } },

4683 { "(bad)",» { XX } },	5004 { Bad_Opcode },

4684 },	5005 },

4685	5006

4686 /* PREFIX_VEX_38A7 */	5007 /* PREFIX_VEX_0F38A7 */

4687 {	5008 {

4688 { "(bad)",» { XX } },	5009 { Bad_Opcode },

4689 { "(bad)",» { XX } },	5010 { Bad_Opcode },

4690 { "vfmsubadd213p%XW", { XM, Vex, EXx } },	5011 { "vfmsubadd213p%XW", { XM, Vex, EXx } },

4691 { "(bad)",» { XX } },	5012 },

4692 },	5013

4693	5014 /* PREFIX_VEX_0F38A8 */

4694 /* PREFIX_VEX_38A8 */	5015 {

4695 {	5016 { Bad_Opcode },

4696 { "(bad)",» { XX } },	5017 { Bad_Opcode },

4697 { "(bad)",» { XX } },

4698 { "vfmadd213p%XW", { XM, Vex, EXx } },	5018 { "vfmadd213p%XW", { XM, Vex, EXx } },

4699 { "(bad)",» { XX } },	5019 },

4700 },	5020

4701	5021 /* PREFIX_VEX_0F38A9 */

4702 /* PREFIX_VEX_38A9 */	5022 {

4703 {	5023 { Bad_Opcode },

4704 { "(bad)",» { XX } },	5024 { Bad_Opcode },

4705 { "(bad)",» { XX } },	5025 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },

4706 { "vfmadd213s%XW", { XM, Vex, EXVexWdq } },	5026 },

4707 { "(bad)",» { XX } },	5027

4708 },	5028 /* PREFIX_VEX_0F38AA */

4709	5029 {

4710 /* PREFIX_VEX_38AA */	5030 { Bad_Opcode },

4711 {	5031 { Bad_Opcode },

4712 { "(bad)",» { XX } },

4713 { "(bad)",» { XX } },

4714 { "vfmsub213p%XW", { XM, Vex, EXx } },	5032 { "vfmsub213p%XW", { XM, Vex, EXx } },

4715 { "(bad)",» { XX } },	5033 },

4716 },	5034

4717	5035 /* PREFIX_VEX_0F38AB */

4718 /* PREFIX_VEX_38AB */	5036 {

4719 {	5037 { Bad_Opcode },

4720 { "(bad)",» { XX } },	5038 { Bad_Opcode },

4721 { "(bad)",» { XX } },	5039 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },

4722 { "vfmsub213s%XW", { XM, Vex, EXVexWdq } },	5040 },

4723 { "(bad)",» { XX } },	5041

4724 },	5042 /* PREFIX_VEX_0F38AC */

4725	5043 {

4726 /* PREFIX_VEX_38AC */	5044 { Bad_Opcode },

4727 {	5045 { Bad_Opcode },

4728 { "(bad)",» { XX } },

4729 { "(bad)",» { XX } },

4730 { "vfnmadd213p%XW", { XM, Vex, EXx } },	5046 { "vfnmadd213p%XW", { XM, Vex, EXx } },

4731 { "(bad)",» { XX } },	5047 },

4732 },	5048

4733	5049 /* PREFIX_VEX_0F38AD */

4734 /* PREFIX_VEX_38AD */	5050 {

4735 {	5051 { Bad_Opcode },

4736 { "(bad)",» { XX } },	5052 { Bad_Opcode },

4737 { "(bad)",» { XX } },	5053 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },

4738 { "vfnmadd213s%XW", { XM, Vex, EXVexWdq } },	5054 },

4739 { "(bad)",» { XX } },	5055

4740 },	5056 /* PREFIX_VEX_0F38AE */

4741	5057 {

4742 /* PREFIX_VEX_38AE */	5058 { Bad_Opcode },

4743 {	5059 { Bad_Opcode },

4744 { "(bad)",» { XX } },

4745 { "(bad)",» { XX } },

4746 { "vfnmsub213p%XW", { XM, Vex, EXx } },	5060 { "vfnmsub213p%XW", { XM, Vex, EXx } },

4747 { "(bad)",» { XX } },	5061 },

4748 },	5062

4749	5063 /* PREFIX_VEX_0F38AF */

4750 /* PREFIX_VEX_38AF */	5064 {

4751 {	5065 { Bad_Opcode },

4752 { "(bad)",» { XX } },	5066 { Bad_Opcode },

4753 { "(bad)",» { XX } },	5067 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },

4754 { "vfnmsub213s%XW", { XM, Vex, EXVexWdq } },	5068 },

4755 { "(bad)",» { XX } },	5069

4756 },	5070 /* PREFIX_VEX_0F38B6 */

4757	5071 {

4758 /* PREFIX_VEX_38B6 */	5072 { Bad_Opcode },

4759 {	5073 { Bad_Opcode },

4760 { "(bad)",» { XX } },

4761 { "(bad)",» { XX } },

4762 { "vfmaddsub231p%XW", { XM, Vex, EXx } },	5074 { "vfmaddsub231p%XW", { XM, Vex, EXx } },

4763 { "(bad)",» { XX } },	5075 },

4764 },	5076

4765	5077 /* PREFIX_VEX_0F38B7 */

4766 /* PREFIX_VEX_38B7 */	5078 {

4767 {	5079 { Bad_Opcode },

4768 { "(bad)",» { XX } },	5080 { Bad_Opcode },

4769 { "(bad)",» { XX } },

4770 { "vfmsubadd231p%XW", { XM, Vex, EXx } },	5081 { "vfmsubadd231p%XW", { XM, Vex, EXx } },

4771 { "(bad)",» { XX } },	5082 },

4772 },	5083

4773	5084 /* PREFIX_VEX_0F38B8 */

4774 /* PREFIX_VEX_38B8 */	5085 {

4775 {	5086 { Bad_Opcode },

4776 { "(bad)",» { XX } },	5087 { Bad_Opcode },

4777 { "(bad)",» { XX } },

4778 { "vfmadd231p%XW", { XM, Vex, EXx } },	5088 { "vfmadd231p%XW", { XM, Vex, EXx } },

4779 { "(bad)",» { XX } },	5089 },

4780 },	5090

4781	5091 /* PREFIX_VEX_0F38B9 */

4782 /* PREFIX_VEX_38B9 */	5092 {

4783 {	5093 { Bad_Opcode },

4784 { "(bad)",» { XX } },	5094 { Bad_Opcode },

4785 { "(bad)",» { XX } },	5095 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },

4786 { "vfmadd231s%XW", { XM, Vex, EXVexWdq } },	5096 },

4787 { "(bad)",» { XX } },	5097

4788 },	5098 /* PREFIX_VEX_0F38BA */

4789	5099 {

4790 /* PREFIX_VEX_38BA */	5100 { Bad_Opcode },

4791 {	5101 { Bad_Opcode },

4792 { "(bad)",» { XX } },

4793 { "(bad)",» { XX } },

4794 { "vfmsub231p%XW", { XM, Vex, EXx } },	5102 { "vfmsub231p%XW", { XM, Vex, EXx } },

4795 { "(bad)",» { XX } },	5103 },

4796 },	5104

4797	5105 /* PREFIX_VEX_0F38BB */

4798 /* PREFIX_VEX_38BB */	5106 {

4799 {	5107 { Bad_Opcode },

4800 { "(bad)",» { XX } },	5108 { Bad_Opcode },

4801 { "(bad)",» { XX } },	5109 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },

4802 { "vfmsub231s%XW", { XM, Vex, EXVexWdq } },	5110 },

4803 { "(bad)",» { XX } },	5111

4804 },	5112 /* PREFIX_VEX_0F38BC */

4805	5113 {

4806 /* PREFIX_VEX_38BC */	5114 { Bad_Opcode },

4807 {	5115 { Bad_Opcode },

4808 { "(bad)",» { XX } },

4809 { "(bad)",» { XX } },

4810 { "vfnmadd231p%XW", { XM, Vex, EXx } },	5116 { "vfnmadd231p%XW", { XM, Vex, EXx } },

4811 { "(bad)",» { XX } },	5117 },

4812 },	5118

4813	5119 /* PREFIX_VEX_0F38BD */

4814 /* PREFIX_VEX_38BD */	5120 {

4815 {	5121 { Bad_Opcode },

4816 { "(bad)",» { XX } },	5122 { Bad_Opcode },

4817 { "(bad)",» { XX } },	5123 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },

4818 { "vfnmadd231s%XW", { XM, Vex, EXVexWdq } },	5124 },

4819 { "(bad)",» { XX } },	5125

4820 },	5126 /* PREFIX_VEX_0F38BE */

4821	5127 {

4822 /* PREFIX_VEX_38BE */	5128 { Bad_Opcode },

4823 {	5129 { Bad_Opcode },

4824 { "(bad)",» { XX } },

4825 { "(bad)",» { XX } },

4826 { "vfnmsub231p%XW", { XM, Vex, EXx } },	5130 { "vfnmsub231p%XW", { XM, Vex, EXx } },

4827 { "(bad)", { XX } },	5131 },

4828 },	5132

4829	5133 /* PREFIX_VEX_0F38BF */

4830 /* PREFIX_VEX_38BF */	5134 {

4831 {	5135 { Bad_Opcode },

4832 { "(bad)", { XX } },	5136 { Bad_Opcode },

4833 { "(bad)", { XX } },	5137 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },

4834 { "vfnmsub231s%XW", { XM, Vex, EXVexWdq } },	5138 },

4835 { "(bad)", { XX } },	5139

4836 },	5140 /* PREFIX_VEX_0F38DB */

4837	5141 {

4838 /* PREFIX_VEX_38DB */	5142 { Bad_Opcode },

4839 {	5143 { Bad_Opcode },

4840 { "(bad)", { XX } },	5144 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },

4841 { "(bad)", { XX } },	5145 },

4842 { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },	5146

4843 { "(bad)", { XX } },	5147 /* PREFIX_VEX_0F38DC */

4844 },	5148 {

4845	5149 { Bad_Opcode },

4846 /* PREFIX_VEX_38DC */	5150 { Bad_Opcode },

4847 {	5151 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },

4848 { "(bad)", { XX } },	5152 },

4849 { "(bad)", { XX } },	5153

4850 { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },	5154 /* PREFIX_VEX_0F38DD */

4851 { "(bad)", { XX } },	5155 {

4852 },	5156 { Bad_Opcode },

4853	5157 { Bad_Opcode },

4854 /* PREFIX_VEX_38DD */	5158 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },

4855 {	5159 },

4856 { "(bad)", { XX } },	5160

4857 { "(bad)", { XX } },	5161 /* PREFIX_VEX_0F38DE */

4858 { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },	5162 {

4859 { "(bad)", { XX } },	5163 { Bad_Opcode },

4860 },	5164 { Bad_Opcode },

4861	5165 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },

4862 /* PREFIX_VEX_38DE */	5166 },

4863 {	5167

4864 { "(bad)", { XX } },	5168 /* PREFIX_VEX_0F38DF */

4865 { "(bad)", { XX } },	5169 {

4866 { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },	5170 { Bad_Opcode },

4867 { "(bad)", { XX } },	5171 { Bad_Opcode },

4868 },	5172 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },

4869	5173 },

4870 /* PREFIX_VEX_38DF */	5174

4871 {	5175 /* PREFIX_VEX_0F38F2 */

4872 { "(bad)", { XX } },	5176 {

4873 { "(bad)", { XX } },	5177 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },

4874 { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },	5178 },

4875 { "(bad)", { XX } },	5179

4876 },	5180 /* PREFIX_VEX_0F38F3_REG_1 */

4877	5181 {

4878 /* PREFIX_VEX_3A04 */	5182 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },

4879 {	5183 },

4880 { "(bad)", { XX } },	5184

4881 { "(bad)", { XX } },	5185 /* PREFIX_VEX_0F38F3_REG_2 */

4882 { "vpermilps", { XM, EXx, Ib } },	5186 {

4883 { "(bad)", { XX } },	5187 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },

4884 },	5188 },

4885	5189

4886 /* PREFIX_VEX_3A05 */	5190 /* PREFIX_VEX_0F38F3_REG_3 */

4887 {	5191 {

4888 { "(bad)", { XX } },	5192 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },

4889 { "(bad)", { XX } },	5193 },

4890 { "vpermilpd", { XM, EXx, Ib } },	5194

4891 { "(bad)", { XX } },	5195 /* PREFIX_VEX_0F38F5 */

4892 },	5196 {

4893	5197 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },

4894 /* PREFIX_VEX_3A06 */	5198 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },

4895 {	5199 { Bad_Opcode },

4896 { "(bad)", { XX } },	5200 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },

4897 { "(bad)", { XX } },	5201 },

4898 { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },	5202

4899 { "(bad)", { XX } },	5203 /* PREFIX_VEX_0F38F6 */

4900 },	5204 {

4901	5205 { Bad_Opcode },

4902 /* PREFIX_VEX_3A08 */	5206 { Bad_Opcode },

4903 {	5207 { Bad_Opcode },

4904 { "(bad)", { XX } },	5208 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },

4905 { "(bad)", { XX } },	5209 },

4906 { "vroundps", { XM, EXx, Ib } },	5210

4907 { "(bad)", { XX } },	5211 /* PREFIX_VEX_0F38F7 */

4908 },	5212 {

4909	5213 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },

4910 /* PREFIX_VEX_3A09 */	5214 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },

4911 {	5215 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },

4912 { "(bad)", { XX } },	5216 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },

4913 { "(bad)", { XX } },	5217 },

4914 { "vroundpd", { XM, EXx, Ib } },	5218

4915 { "(bad)", { XX } },	5219 /* PREFIX_VEX_0F3A00 */

4916 },	5220 {

4917	5221 { Bad_Opcode },

4918 /* PREFIX_VEX_3A0A */	5222 { Bad_Opcode },

4919 {	5223 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },

4920 { "(bad)", { XX } },	5224 },

4921 { "(bad)", { XX } },	5225

4922 { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },	5226 /* PREFIX_VEX_0F3A01 */

4923 { "(bad)", { XX } },	5227 {

4924 },	5228 { Bad_Opcode },

4925	5229 { Bad_Opcode },

4926 /* PREFIX_VEX_3A0B */	5230 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },

4927 {	5231 },

4928 { "(bad)", { XX } },	5232

4929 { "(bad)", { XX } },	5233 /* PREFIX_VEX_0F3A02 */

4930 { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },	5234 {

4931 { "(bad)", { XX } },	5235 { Bad_Opcode },

4932 },	5236 { Bad_Opcode },

4933	5237 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },

4934 /* PREFIX_VEX_3A0C */	5238 },

4935 {	5239

4936 { "(bad)", { XX } },	5240 /* PREFIX_VEX_0F3A04 */

4937 { "(bad)", { XX } },	5241 {

4938 { "vblendps", { XM, Vex, EXx, Ib } },	5242 { Bad_Opcode },

4939 { "(bad)", { XX } },	5243 { Bad_Opcode },

4940 },	5244 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },

4941	5245 },

4942 /* PREFIX_VEX_3A0D */	5246

4943 {	5247 /* PREFIX_VEX_0F3A05 */

4944 { "(bad)", { XX } },	5248 {

4945 { "(bad)", { XX } },	5249 { Bad_Opcode },

4946 { "vblendpd", { XM, Vex, EXx, Ib } },	5250 { Bad_Opcode },

4947 { "(bad)", { XX } },	5251 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },

4948 },	5252 },

4949	5253

4950 /* PREFIX_VEX_3A0E */	5254 /* PREFIX_VEX_0F3A06 */

4951 {	5255 {

4952 { "(bad)", { XX } },	5256 { Bad_Opcode },

4953 { "(bad)", { XX } },	5257 { Bad_Opcode },

4954 { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },	5258 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },

4955 { "(bad)", { XX } },	5259 },

4956 },	5260

4957	5261 /* PREFIX_VEX_0F3A08 */

4958 /* PREFIX_VEX_3A0F */	5262 {

4959 {	5263 { Bad_Opcode },

4960 { "(bad)", { XX } },	5264 { Bad_Opcode },

4961 { "(bad)", { XX } },	5265 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },

4962 { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },	5266 },

4963 { "(bad)", { XX } },	5267

4964 },	5268 /* PREFIX_VEX_0F3A09 */

4965	5269 {

4966 /* PREFIX_VEX_3A14 */	5270 { Bad_Opcode },

4967 {	5271 { Bad_Opcode },

4968 { "(bad)", { XX } },	5272 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },

4969 { "(bad)", { XX } },	5273 },

4970 { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },	5274

4971 { "(bad)", { XX } },	5275 /* PREFIX_VEX_0F3A0A */

4972 },	5276 {

4973	5277 { Bad_Opcode },

4974 /* PREFIX_VEX_3A15 */	5278 { Bad_Opcode },

4975 {	5279 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },

4976 { "(bad)", { XX } },	5280 },

4977 { "(bad)", { XX } },	5281

4978 { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },	5282 /* PREFIX_VEX_0F3A0B */

4979 { "(bad)", { XX } },	5283 {

4980 },	5284 { Bad_Opcode },

4981	5285 { Bad_Opcode },

4982 /* PREFIX_VEX_3A16 */	5286 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },

4983 {	5287 },

4984 { "(bad)", { XX } },	5288

4985 { "(bad)", { XX } },	5289 /* PREFIX_VEX_0F3A0C */

4986 { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },	5290 {

4987 { "(bad)", { XX } },	5291 { Bad_Opcode },

4988 },	5292 { Bad_Opcode },

4989	5293 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },

4990 /* PREFIX_VEX_3A17 */	5294 },

4991 {	5295

4992 { "(bad)", { XX } },	5296 /* PREFIX_VEX_0F3A0D */

4993 { "(bad)", { XX } },	5297 {

4994 { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },	5298 { Bad_Opcode },

4995 { "(bad)", { XX } },	5299 { Bad_Opcode },

4996 },	5300 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },

4997	5301 },

4998 /* PREFIX_VEX_3A18 */	5302

4999 {	5303 /* PREFIX_VEX_0F3A0E */

5000 { "(bad)", { XX } },	5304 {

5001 { "(bad)", { XX } },	5305 { Bad_Opcode },

5002 { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },	5306 { Bad_Opcode },

5003 { "(bad)", { XX } },	5307 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },

5004 },	5308 },

5005	5309

5006 /* PREFIX_VEX_3A19 */	5310 /* PREFIX_VEX_0F3A0F */

5007 {	5311 {

5008 { "(bad)", { XX } },	5312 { Bad_Opcode },

5009 { "(bad)", { XX } },	5313 { Bad_Opcode },

5010 { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },	5314 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },

5011 { "(bad)", { XX } },	5315 },

5012 },	5316

5013	5317 /* PREFIX_VEX_0F3A14 */

5014 /* PREFIX_VEX_3A20 */	5318 {

5015 {	5319 { Bad_Opcode },

5016 { "(bad)", { XX } },	5320 { Bad_Opcode },

5017 { "(bad)", { XX } },	5321 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },

5018 { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },	5322 },

5019 { "(bad)", { XX } },	5323

5020 },	5324 /* PREFIX_VEX_0F3A15 */

5021	5325 {

5022 /* PREFIX_VEX_3A21 */	5326 { Bad_Opcode },

5023 {	5327 { Bad_Opcode },

5024 { "(bad)", { XX } },	5328 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },

5025 { "(bad)", { XX } },	5329 },

5026 { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },	5330

5027 { "(bad)", { XX } },	5331 /* PREFIX_VEX_0F3A16 */

5028 },	5332 {

5029	5333 { Bad_Opcode },

5030 /* PREFIX_VEX_3A22 */	5334 { Bad_Opcode },

5031 {	5335 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },

5032 { "(bad)", { XX } },	5336 },

5033 { "(bad)", { XX } },	5337

5034 { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },	5338 /* PREFIX_VEX_0F3A17 */

5035 { "(bad)", { XX } },	5339 {

5036 },	5340 { Bad_Opcode },

5037	5341 { Bad_Opcode },

5038 /* PREFIX_VEX_3A40 */	5342 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },

5039 {	5343 },

5040 { "(bad)", { XX } },	5344

5041 { "(bad)", { XX } },	5345 /* PREFIX_VEX_0F3A18 */

5042 { "vdpps", { XM, Vex, EXx, Ib } },	5346 {

5043 { "(bad)", { XX } },	5347 { Bad_Opcode },

5044 },	5348 { Bad_Opcode },

5045	5349 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },

5046 /* PREFIX_VEX_3A41 */	5350 },

5047 {	5351

5048 { "(bad)", { XX } },	5352 /* PREFIX_VEX_0F3A19 */

5049 { "(bad)", { XX } },	5353 {

5050 { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },	5354 { Bad_Opcode },

5051 { "(bad)", { XX } },	5355 { Bad_Opcode },

5052 },	5356 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },

5053	5357 },

5054 /* PREFIX_VEX_3A42 */	5358

5055 {	5359 /* PREFIX_VEX_0F3A1D */

5056 { "(bad)", { XX } },	5360 {

5057 { "(bad)", { XX } },	5361 { Bad_Opcode },

5058 { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },	5362 { Bad_Opcode },

5059 { "(bad)", { XX } },	5363 { "vcvtps2ph", { EXxmmq, XM, Ib } },

5060 },	5364 },

5061	5365

5062 /* PREFIX_VEX_3A44 */	5366 /* PREFIX_VEX_0F3A20 */

5063 {	5367 {

5064 { "(bad)", { XX } },	5368 { Bad_Opcode },

5065 { "(bad)", { XX } },	5369 { Bad_Opcode },

5066 { VEX_LEN_TABLE (VEX_LEN_3A44_P_2) },	5370 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },

5067 { "(bad)", { XX } },	5371 },

5068 },	5372

5069	5373 /* PREFIX_VEX_0F3A21 */

5070 /* PREFIX_VEX_3A4A */	5374 {

5071 {	5375 { Bad_Opcode },

5072 { "(bad)", { XX } },	5376 { Bad_Opcode },

5073 { "(bad)", { XX } },	5377 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },

5074 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },	5378 },

5075 { "(bad)", { XX } },	5379

5076 },	5380 /* PREFIX_VEX_0F3A22 */

5077	5381 {

5078 /* PREFIX_VEX_3A4B */	5382 { Bad_Opcode },

5079 {	5383 { Bad_Opcode },

5080 { "(bad)", { XX } },	5384 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },

5081 { "(bad)", { XX } },	5385 },

5082 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },	5386

5083 { "(bad)", { XX } },	5387 /* PREFIX_VEX_0F3A38 */

5084 },	5388 {

5085	5389 { Bad_Opcode },

5086 /* PREFIX_VEX_3A4C */	5390 { Bad_Opcode },

5087 {	5391 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },

5088 { "(bad)", { XX } },	5392 },

5089 { "(bad)", { XX } },	5393

5090 { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },	5394 /* PREFIX_VEX_0F3A39 */

5091 { "(bad)", { XX } },	5395 {

5092 },	5396 { Bad_Opcode },

5093	5397 { Bad_Opcode },

5094 /* PREFIX_VEX_3A5C */	5398 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },

5095 {	5399 },

5096 { "(bad)", { XX } },	5400

5097 { "(bad)", { XX } },	5401 /* PREFIX_VEX_0F3A40 */

5098 { "vfmaddsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },	5402 {

5099 { "(bad)", { XX } },	5403 { Bad_Opcode },

5100 },	5404 { Bad_Opcode },

5101	5405 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },

5102 /* PREFIX_VEX_3A5D */	5406 },

5103 {	5407

5104 { "(bad)", { XX } },	5408 /* PREFIX_VEX_0F3A41 */

5105 { "(bad)", { XX } },	5409 {

5106 { "vfmaddsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },	5410 { Bad_Opcode },

5107 { "(bad)", { XX } },	5411 { Bad_Opcode },

5108 },	5412 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },

5109	5413 },

5110 /* PREFIX_VEX_3A5E */	5414

5111 {	5415 /* PREFIX_VEX_0F3A42 */

5112 { "(bad)", { XX } },	5416 {

5113 { "(bad)", { XX } },	5417 { Bad_Opcode },

5114 { "vfmsubaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },	5418 { Bad_Opcode },

5115 { "(bad)", { XX } },	5419 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },

5116 },	5420 },

5117	5421

5118 /* PREFIX_VEX_3A5F */	5422 /* PREFIX_VEX_0F3A44 */

5119 {	5423 {

5120 { "(bad)", { XX } },	5424 { Bad_Opcode },

5121 { "(bad)", { XX } },	5425 { Bad_Opcode },

5122 { "vfmsubaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },	5426 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },

5123 { "(bad)", { XX } },	5427 },

5124 },	5428

5125	5429 /* PREFIX_VEX_0F3A46 */

5126 /* PREFIX_VEX_3A60 */	5430 {

5127 {	5431 { Bad_Opcode },

5128 { "(bad)", { XX } },	5432 { Bad_Opcode },

5129 { "(bad)", { XX } },	5433 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },

5130 { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },	5434 },

5131 { "(bad)", { XX } },	5435

5132 },	5436 /* PREFIX_VEX_0F3A48 */

5133	5437 {

5134 /* PREFIX_VEX_3A61 */	5438 { Bad_Opcode },

5135 {	5439 { Bad_Opcode },

5136 { "(bad)", { XX } },	5440 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },

5137 { "(bad)", { XX } },	5441 },

5138 { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },	5442

5139 { "(bad)", { XX } },	5443 /* PREFIX_VEX_0F3A49 */

5140 },	5444 {

5141	5445 { Bad_Opcode },

5142 /* PREFIX_VEX_3A62 */	5446 { Bad_Opcode },

5143 {	5447 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },

5144 { "(bad)", { XX } },	5448 },

5145 { "(bad)", { XX } },	5449

5146 { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },	5450 /* PREFIX_VEX_0F3A4A */

5147 { "(bad)", { XX } },	5451 {

5148 },	5452 { Bad_Opcode },

5149	5453 { Bad_Opcode },

5150 /* PREFIX_VEX_3A63 */	5454 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },

5151 {	5455 },

5152 { "(bad)", { XX } },	5456

5153 { "(bad)", { XX } },	5457 /* PREFIX_VEX_0F3A4B */

5154 { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },	5458 {

5155 { "(bad)", { XX } },	5459 { Bad_Opcode },

5156 },	5460 { Bad_Opcode },

5157	5461 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },

5158 /* PREFIX_VEX_3A68 */	5462 },

5159 {	5463

5160 { "(bad)", { XX } },	5464 /* PREFIX_VEX_0F3A4C */

5161 { "(bad)", { XX } },	5465 {

5162 { "vfmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },	5466 { Bad_Opcode },

5163 { "(bad)", { XX } },	5467 { Bad_Opcode },

5164 },	5468 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },

5165	5469 },

5166 /* PREFIX_VEX_3A69 */	5470

5167 {	5471 /* PREFIX_VEX_0F3A5C */

5168 { "(bad)", { XX } },	5472 {

5169 { "(bad)", { XX } },	5473 { Bad_Opcode },

5170 { "vfmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },	5474 { Bad_Opcode },

5171 { "(bad)", { XX } },	5475 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

5172 },	5476 },

5173	5477

5174 /* PREFIX_VEX_3A6A */	5478 /* PREFIX_VEX_0F3A5D */

5175 {	5479 {

5176 { "(bad)", { XX } },	5480 { Bad_Opcode },

5177 { "(bad)", { XX } },	5481 { Bad_Opcode },

5178 { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },	5482 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

5179 { "(bad)", { XX } },	5483 },

5180 },	5484

5181	5485 /* PREFIX_VEX_0F3A5E */

5182 /* PREFIX_VEX_3A6B */	5486 {

5183 {	5487 { Bad_Opcode },

5184 { "(bad)", { XX } },	5488 { Bad_Opcode },

5185 { "(bad)", { XX } },	5489 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

5186 { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },	5490 },

5187 { "(bad)", { XX } },	5491

5188 },	5492 /* PREFIX_VEX_0F3A5F */

5189	5493 {

5190 /* PREFIX_VEX_3A6C */	5494 { Bad_Opcode },

5191 {	5495 { Bad_Opcode },

5192 { "(bad)", { XX } },	5496 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

5193 { "(bad)", { XX } },	5497 },

5194 { "vfmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },	5498

5195 { "(bad)", { XX } },	5499 /* PREFIX_VEX_0F3A60 */

5196 },	5500 {

5197	5501 { Bad_Opcode },

5198 /* PREFIX_VEX_3A6D */	5502 { Bad_Opcode },

5199 {	5503 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },

5200 { "(bad)", { XX } },	5504 { Bad_Opcode },

5201 { "(bad)", { XX } },	5505 },

5202 { "vfmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },	5506

5203 { "(bad)", { XX } },	5507 /* PREFIX_VEX_0F3A61 */

5204 },	5508 {

5205	5509 { Bad_Opcode },

5206 /* PREFIX_VEX_3A6E */	5510 { Bad_Opcode },

5207 {	5511 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },

5208 { "(bad)", { XX } },	5512 },

5209 { "(bad)", { XX } },	5513

5210 { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },	5514 /* PREFIX_VEX_0F3A62 */

5211 { "(bad)", { XX } },	5515 {

5212 },	5516 { Bad_Opcode },

5213	5517 { Bad_Opcode },

5214 /* PREFIX_VEX_3A6F */	5518 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },

5215 {	5519 },

5216 { "(bad)", { XX } },	5520

5217 { "(bad)", { XX } },	5521 /* PREFIX_VEX_0F3A63 */

5218 { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },	5522 {

5219 { "(bad)", { XX } },	5523 { Bad_Opcode },

5220 },	5524 { Bad_Opcode },

5221	5525 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },

5222 /* PREFIX_VEX_3A78 */	5526 },

5223 {	5527

5224 { "(bad)", { XX } },	5528 /* PREFIX_VEX_0F3A68 */

5225 { "(bad)", { XX } },	5529 {

5226 { "vfnmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },	5530 { Bad_Opcode },

5227 { "(bad)", { XX } },	5531 { Bad_Opcode },

5228 },	5532 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

5229	5533 },

5230 /* PREFIX_VEX_3A79 */	5534

5231 {	5535 /* PREFIX_VEX_0F3A69 */

5232 { "(bad)", { XX } },	5536 {

5233 { "(bad)", { XX } },	5537 { Bad_Opcode },

5234 { "vfnmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },	5538 { Bad_Opcode },

5235 { "(bad)", { XX } },	5539 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

5236 },	5540 },

5237	5541

5238 /* PREFIX_VEX_3A7A */	5542 /* PREFIX_VEX_0F3A6A */

5239 {	5543 {

5240 { "(bad)", { XX } },	5544 { Bad_Opcode },

5241 { "(bad)", { XX } },	5545 { Bad_Opcode },

5242 { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },	5546 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },

5243 { "(bad)", { XX } },	5547 },

5244 },	5548

5245	5549 /* PREFIX_VEX_0F3A6B */

5246 /* PREFIX_VEX_3A7B */	5550 {

5247 {	5551 { Bad_Opcode },

5248 { "(bad)", { XX } },	5552 { Bad_Opcode },

5249 { "(bad)", { XX } },	5553 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },

5250 { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },	5554 },

5251 { "(bad)", { XX } },	5555

5252 },	5556 /* PREFIX_VEX_0F3A6C */

5253	5557 {

5254 /* PREFIX_VEX_3A7C */	5558 { Bad_Opcode },

5255 {	5559 { Bad_Opcode },

5256 { "(bad)", { XX } },	5560 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

5257 { "(bad)", { XX } },	5561 },

5258 { "vfnmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },	5562

5259 { "(bad)", { XX } },	5563 /* PREFIX_VEX_0F3A6D */

5260 },	5564 {

5261	5565 { Bad_Opcode },

5262 /* PREFIX_VEX_3A7D */	5566 { Bad_Opcode },

5263 {	5567 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

5264 { "(bad)", { XX } },	5568 },

5265 { "(bad)", { XX } },	5569

5266 { "vfnmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },	5570 /* PREFIX_VEX_0F3A6E */

5267 { "(bad)", { XX } },	5571 {

5268 },	5572 { Bad_Opcode },

5269	5573 { Bad_Opcode },

5270 /* PREFIX_VEX_3A7E */	5574 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },

5271 {	5575 },

5272 { "(bad)", { XX } },	5576

5273 { "(bad)", { XX } },	5577 /* PREFIX_VEX_0F3A6F */

5274 { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },	5578 {

5275 { "(bad)", { XX } },	5579 { Bad_Opcode },

5276 },	5580 { Bad_Opcode },

5277	5581 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },

5278 /* PREFIX_VEX_3A7F */	5582 },

5279 {	5583

5280 { "(bad)", { XX } },	5584 /* PREFIX_VEX_0F3A78 */

5281 { "(bad)", { XX } },	5585 {

5282 { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },	5586 { Bad_Opcode },

5283 { "(bad)", { XX } },	5587 { Bad_Opcode },

5284 },	5588 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

5285	5589 },

5286 /* PREFIX_VEX_3ADF */	5590

5287 {	5591 /* PREFIX_VEX_0F3A79 */

5288 { "(bad)", { XX } },	5592 {

5289 { "(bad)", { XX } },	5593 { Bad_Opcode },

5290 { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },	5594 { Bad_Opcode },

5291 { "(bad)", { XX } },	5595 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

	5596 },

	5597

	5598 /* PREFIX_VEX_0F3A7A */

	5599 {

	5600 { Bad_Opcode },

	5601 { Bad_Opcode },

	5602 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },

	5603 },

	5604

	5605 /* PREFIX_VEX_0F3A7B */

	5606 {

	5607 { Bad_Opcode },

	5608 { Bad_Opcode },

	5609 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },

	5610 },

	5611

	5612 /* PREFIX_VEX_0F3A7C */

	5613 {

	5614 { Bad_Opcode },

	5615 { Bad_Opcode },

	5616 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

	5617 { Bad_Opcode },

	5618 },

	5619

	5620 /* PREFIX_VEX_0F3A7D */

	5621 {

	5622 { Bad_Opcode },

	5623 { Bad_Opcode },

	5624 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

	5625 },

	5626

	5627 /* PREFIX_VEX_0F3A7E */

	5628 {

	5629 { Bad_Opcode },

	5630 { Bad_Opcode },

	5631 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },

	5632 },

	5633

	5634 /* PREFIX_VEX_0F3A7F */

	5635 {

	5636 { Bad_Opcode },

	5637 { Bad_Opcode },

	5638 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },

	5639 },

	5640

	5641 /* PREFIX_VEX_0F3ADF */

	5642 {

	5643 { Bad_Opcode },

	5644 { Bad_Opcode },

	5645 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },

	5646 },

	5647

	5648 /* PREFIX_VEX_0F3AF0 */

	5649 {

	5650 { Bad_Opcode },

	5651 { Bad_Opcode },

	5652 { Bad_Opcode },

	5653 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },

5292 },	5654 },

5293 };	5655 };

5294	5656

5295 static const struct dis386 x86_64_table[][2] = {	5657 static const struct dis386 x86_64_table[][2] = {

5296 /* X86_64_06 */	5658 /* X86_64_06 */

5297 {	5659 {

5298 { "push{T\|}", { es } },	5660 { "pushP", { es } },

5299 { "(bad)", { XX } },

5300 },	5661 },

5301	5662

5302 /* X86_64_07 */	5663 /* X86_64_07 */

5303 {	5664 {

5304 { "pop{T\|}", { es } },	5665 { "popP", { es } },

5305 { "(bad)", { XX } },

5306 },	5666 },

5307	5667

5308 /* X86_64_0D */	5668 /* X86_64_0D */

5309 {	5669 {

5310 { "push{T\|}", { cs } },	5670 { "pushP", { cs } },

5311 { "(bad)", { XX } },

5312 },	5671 },

5313	5672

5314 /* X86_64_16 */	5673 /* X86_64_16 */

5315 {	5674 {

5316 { "push{T\|}", { ss } },	5675 { "pushP", { ss } },

5317 { "(bad)", { XX } },

5318 },	5676 },

5319	5677

5320 /* X86_64_17 */	5678 /* X86_64_17 */

5321 {	5679 {

5322 { "pop{T\|}", { ss } },	5680 { "popP", { ss } },

5323 { "(bad)", { XX } },

5324 },	5681 },

5325	5682

5326 /* X86_64_1E */	5683 /* X86_64_1E */

5327 {	5684 {

5328 { "push{T\|}", { ds } },	5685 { "pushP", { ds } },

5329 { "(bad)", { XX } },

5330 },	5686 },

5331	5687

5332 /* X86_64_1F */	5688 /* X86_64_1F */

5333 {	5689 {

5334 { "pop{T\|}", { ds } },	5690 { "popP", { ds } },

5335 { "(bad)", { XX } },

5336 },	5691 },

5337	5692

5338 /* X86_64_27 */	5693 /* X86_64_27 */

5339 {	5694 {

5340 { "daa", { XX } },	5695 { "daa", { XX } },

5341 { "(bad)", { XX } },

5342 },	5696 },

5343	5697

5344 /* X86_64_2F */	5698 /* X86_64_2F */

5345 {	5699 {

5346 { "das", { XX } },	5700 { "das", { XX } },

5347 { "(bad)", { XX } },

5348 },	5701 },

5349	5702

5350 /* X86_64_37 */	5703 /* X86_64_37 */

5351 {	5704 {

5352 { "aaa", { XX } },	5705 { "aaa", { XX } },

5353 { "(bad)", { XX } },

5354 },	5706 },

5355	5707

5356 /* X86_64_3F */	5708 /* X86_64_3F */

5357 {	5709 {

5358 { "aas", { XX } },	5710 { "aas", { XX } },

5359 { "(bad)", { XX } },

5360 },	5711 },

5361	5712

5362 /* X86_64_60 */	5713 /* X86_64_60 */

5363 {	5714 {

5364 { "pusha{P\|}", { XX } },	5715 { "pushaP", { XX } },

5365 { "(bad)", { XX } },

5366 },	5716 },

5367	5717

5368 /* X86_64_61 */	5718 /* X86_64_61 */

5369 {	5719 {

5370 { "popa{P\|}", { XX } },	5720 { "popaP", { XX } },

5371 { "(bad)", { XX } },

5372 },	5721 },

5373	5722

5374 /* X86_64_62 */	5723 /* X86_64_62 */

5375 {	5724 {

5376 { MOD_TABLE (MOD_62_32BIT) },	5725 { MOD_TABLE (MOD_62_32BIT) },

5377 { "(bad)", { XX } },

5378 },	5726 },

5379	5727

5380 /* X86_64_63 */	5728 /* X86_64_63 */

5381 {	5729 {

5382 { "arpl", { Ew, Gw } },	5730 { "arpl", { Ew, Gw } },

5383 { "movs{lq\|xd}", { Gv, Ed } },	5731 { "movs{lq\|xd}", { Gv, Ed } },

5384 },	5732 },

5385	5733

5386 /* X86_64_6D */	5734 /* X86_64_6D */

5387 {	5735 {

5388 { "ins{R\|}", { Yzr, indirDX } },	5736 { "ins{R\|}", { Yzr, indirDX } },

5389 { "ins{G\|}", { Yzr, indirDX } },	5737 { "ins{G\|}", { Yzr, indirDX } },

5390 },	5738 },

5391	5739

5392 /* X86_64_6F */	5740 /* X86_64_6F */

5393 {	5741 {

5394 { "outs{R\|}", { indirDXr, Xz } },	5742 { "outs{R\|}", { indirDXr, Xz } },

5395 { "outs{G\|}", { indirDXr, Xz } },	5743 { "outs{G\|}", { indirDXr, Xz } },

5396 },	5744 },

5397	5745

5398 /* X86_64_9A */	5746 /* X86_64_9A */

5399 {	5747 {

5400 { "Jcall{T\|}", { Ap } },	5748 { "Jcall{T\|}", { Ap } },

5401 { "(bad)", { XX } },

5402 },	5749 },

5403	5750

5404 /* X86_64_C4 */	5751 /* X86_64_C4 */

5405 {	5752 {

5406 { MOD_TABLE (MOD_C4_32BIT) },	5753 { MOD_TABLE (MOD_C4_32BIT) },

5407 { VEX_C4_TABLE (VEX_0F) },	5754 { VEX_C4_TABLE (VEX_0F) },

5408 },	5755 },

5409	5756

5410 /* X86_64_C5 */	5757 /* X86_64_C5 */

5411 {	5758 {

5412 { MOD_TABLE (MOD_C5_32BIT) },	5759 { MOD_TABLE (MOD_C5_32BIT) },

5413 { VEX_C5_TABLE (VEX_0F) },	5760 { VEX_C5_TABLE (VEX_0F) },

5414 },	5761 },

5415	5762

5416 /* X86_64_CE */	5763 /* X86_64_CE */

5417 {	5764 {

5418 { "into", { XX } },	5765 { "into", { XX } },

5419 { "(bad)", { XX } },

5420 },	5766 },

5421	5767

5422 /* X86_64_D4 */	5768 /* X86_64_D4 */

5423 {	5769 {

5424 { "aam", { sIb } },	5770 { "aam", { Ib } },

5425 { "(bad)", { XX } },

5426 },	5771 },

5427	5772

5428 /* X86_64_D5 */	5773 /* X86_64_D5 */

5429 {	5774 {

5430 { "aad", { sIb } },	5775 { "aad", { Ib } },

5431 { "(bad)", { XX } },

5432 },	5776 },

5433	5777

5434 /* X86_64_EA */	5778 /* X86_64_EA */

5435 {	5779 {

5436 { "Jjmp{T\|}", { Ap } },	5780 { "Jjmp{T\|}", { Ap } },

5437 { "(bad)", { XX } },

5438 },	5781 },

5439	5782

5440 /* X86_64_0F01_REG_0 */	5783 /* X86_64_0F01_REG_0 */

5441 {	5784 {

5442 { "sgdt{Q\|IQ}", { M } },	5785 { "sgdt{Q\|IQ}", { M } },

5443 { "sgdt", { M } },	5786 { "sgdt", { M } },

5444 },	5787 },

5445	5788

5446 /* X86_64_0F01_REG_1 */	5789 /* X86_64_0F01_REG_1 */

5447 {	5790 {

(...skipping 25 matching lines...) Expand all Loading...
5473 { "phaddsw", { MX, EM } },	5816 { "phaddsw", { MX, EM } },

5474 { "pmaddubsw", { MX, EM } },	5817 { "pmaddubsw", { MX, EM } },

5475 { "phsubw", { MX, EM } },	5818 { "phsubw", { MX, EM } },

5476 { "phsubd", { MX, EM } },	5819 { "phsubd", { MX, EM } },

5477 { "phsubsw", { MX, EM } },	5820 { "phsubsw", { MX, EM } },

5478 /* 08 */	5821 /* 08 */

5479 { "psignb", { MX, EM } },	5822 { "psignb", { MX, EM } },

5480 { "psignw", { MX, EM } },	5823 { "psignw", { MX, EM } },

5481 { "psignd", { MX, EM } },	5824 { "psignd", { MX, EM } },

5482 { "pmulhrsw", { MX, EM } },	5825 { "pmulhrsw", { MX, EM } },

5483 { "(bad)",» » { XX } },	5826 { Bad_Opcode },

5484 { "(bad)",» » { XX } },	5827 { Bad_Opcode },

5485 { "(bad)",» » { XX } },	5828 { Bad_Opcode },

5486 { "(bad)",» » { XX } },	5829 { Bad_Opcode },

5487 /* 10 */	5830 /* 10 */

5488 { PREFIX_TABLE (PREFIX_0F3810) },	5831 { PREFIX_TABLE (PREFIX_0F3810) },

5489 { "(bad)",» » { XX } },	5832 { Bad_Opcode },

5490 { "(bad)",» » { XX } },	5833 { Bad_Opcode },

5491 { "(bad)",» » { XX } },	5834 { Bad_Opcode },

5492 { PREFIX_TABLE (PREFIX_0F3814) },	5835 { PREFIX_TABLE (PREFIX_0F3814) },

5493 { PREFIX_TABLE (PREFIX_0F3815) },	5836 { PREFIX_TABLE (PREFIX_0F3815) },

5494 { "(bad)",» » { XX } },	5837 { Bad_Opcode },

5495 { PREFIX_TABLE (PREFIX_0F3817) },	5838 { PREFIX_TABLE (PREFIX_0F3817) },

5496 /* 18 */	5839 /* 18 */

5497 { "(bad)",» » { XX } },	5840 { Bad_Opcode },

5498 { "(bad)",» » { XX } },	5841 { Bad_Opcode },

5499 { "(bad)",» » { XX } },	5842 { Bad_Opcode },

5500 { "(bad)",» » { XX } },	5843 { Bad_Opcode },

5501 { "pabsb", { MX, EM } },	5844 { "pabsb", { MX, EM } },

5502 { "pabsw", { MX, EM } },	5845 { "pabsw", { MX, EM } },

5503 { "pabsd", { MX, EM } },	5846 { "pabsd", { MX, EM } },

5504 { "(bad)",» » { XX } },	5847 { Bad_Opcode },

5505 /* 20 */	5848 /* 20 */

5506 { PREFIX_TABLE (PREFIX_0F3820) },	5849 { PREFIX_TABLE (PREFIX_0F3820) },

5507 { PREFIX_TABLE (PREFIX_0F3821) },	5850 { PREFIX_TABLE (PREFIX_0F3821) },

5508 { PREFIX_TABLE (PREFIX_0F3822) },	5851 { PREFIX_TABLE (PREFIX_0F3822) },

5509 { PREFIX_TABLE (PREFIX_0F3823) },	5852 { PREFIX_TABLE (PREFIX_0F3823) },

5510 { PREFIX_TABLE (PREFIX_0F3824) },	5853 { PREFIX_TABLE (PREFIX_0F3824) },

5511 { PREFIX_TABLE (PREFIX_0F3825) },	5854 { PREFIX_TABLE (PREFIX_0F3825) },

5512 { "(bad)",» » { XX } },	5855 { Bad_Opcode },

5513 { "(bad)",» » { XX } },	5856 { Bad_Opcode },

5514 /* 28 */	5857 /* 28 */

5515 { PREFIX_TABLE (PREFIX_0F3828) },	5858 { PREFIX_TABLE (PREFIX_0F3828) },

5516 { PREFIX_TABLE (PREFIX_0F3829) },	5859 { PREFIX_TABLE (PREFIX_0F3829) },

5517 { PREFIX_TABLE (PREFIX_0F382A) },	5860 { PREFIX_TABLE (PREFIX_0F382A) },

5518 { PREFIX_TABLE (PREFIX_0F382B) },	5861 { PREFIX_TABLE (PREFIX_0F382B) },

5519 { "(bad)",» » { XX } },	5862 { Bad_Opcode },

5520 { "(bad)",» » { XX } },	5863 { Bad_Opcode },

5521 { "(bad)",» » { XX } },	5864 { Bad_Opcode },

5522 { "(bad)",» » { XX } },	5865 { Bad_Opcode },

5523 /* 30 */	5866 /* 30 */

5524 { PREFIX_TABLE (PREFIX_0F3830) },	5867 { PREFIX_TABLE (PREFIX_0F3830) },

5525 { PREFIX_TABLE (PREFIX_0F3831) },	5868 { PREFIX_TABLE (PREFIX_0F3831) },

5526 { PREFIX_TABLE (PREFIX_0F3832) },	5869 { PREFIX_TABLE (PREFIX_0F3832) },

5527 { PREFIX_TABLE (PREFIX_0F3833) },	5870 { PREFIX_TABLE (PREFIX_0F3833) },

5528 { PREFIX_TABLE (PREFIX_0F3834) },	5871 { PREFIX_TABLE (PREFIX_0F3834) },

5529 { PREFIX_TABLE (PREFIX_0F3835) },	5872 { PREFIX_TABLE (PREFIX_0F3835) },

5530 { "(bad)",» » { XX } },	5873 { Bad_Opcode },

5531 { PREFIX_TABLE (PREFIX_0F3837) },	5874 { PREFIX_TABLE (PREFIX_0F3837) },

5532 /* 38 */	5875 /* 38 */

5533 { PREFIX_TABLE (PREFIX_0F3838) },	5876 { PREFIX_TABLE (PREFIX_0F3838) },

5534 { PREFIX_TABLE (PREFIX_0F3839) },	5877 { PREFIX_TABLE (PREFIX_0F3839) },

5535 { PREFIX_TABLE (PREFIX_0F383A) },	5878 { PREFIX_TABLE (PREFIX_0F383A) },

5536 { PREFIX_TABLE (PREFIX_0F383B) },	5879 { PREFIX_TABLE (PREFIX_0F383B) },

5537 { PREFIX_TABLE (PREFIX_0F383C) },	5880 { PREFIX_TABLE (PREFIX_0F383C) },

5538 { PREFIX_TABLE (PREFIX_0F383D) },	5881 { PREFIX_TABLE (PREFIX_0F383D) },

5539 { PREFIX_TABLE (PREFIX_0F383E) },	5882 { PREFIX_TABLE (PREFIX_0F383E) },

5540 { PREFIX_TABLE (PREFIX_0F383F) },	5883 { PREFIX_TABLE (PREFIX_0F383F) },

5541 /* 40 */	5884 /* 40 */

5542 { PREFIX_TABLE (PREFIX_0F3840) },	5885 { PREFIX_TABLE (PREFIX_0F3840) },

5543 { PREFIX_TABLE (PREFIX_0F3841) },	5886 { PREFIX_TABLE (PREFIX_0F3841) },

5544 { "(bad)",» » { XX } },	5887 { Bad_Opcode },

5545 { "(bad)",» » { XX } },	5888 { Bad_Opcode },

5546 { "(bad)",» » { XX } },	5889 { Bad_Opcode },

5547 { "(bad)",» » { XX } },	5890 { Bad_Opcode },

5548 { "(bad)",» » { XX } },	5891 { Bad_Opcode },

5549 { "(bad)",» » { XX } },	5892 { Bad_Opcode },

5550 /* 48 */	5893 /* 48 */

5551 { "(bad)",» » { XX } },	5894 { Bad_Opcode },

5552 { "(bad)",» » { XX } },	5895 { Bad_Opcode },

5553 { "(bad)",» » { XX } },	5896 { Bad_Opcode },

5554 { "(bad)",» » { XX } },	5897 { Bad_Opcode },

5555 { "(bad)",» » { XX } },	5898 { Bad_Opcode },

5556 { "(bad)",» » { XX } },	5899 { Bad_Opcode },

5557 { "(bad)",» » { XX } },	5900 { Bad_Opcode },

5558 { "(bad)",» » { XX } },	5901 { Bad_Opcode },

5559 /* 50 */	5902 /* 50 */

5560 { "(bad)",» » { XX } },	5903 { Bad_Opcode },

5561 { "(bad)",» » { XX } },	5904 { Bad_Opcode },

5562 { "(bad)",» » { XX } },	5905 { Bad_Opcode },

5563 { "(bad)",» » { XX } },	5906 { Bad_Opcode },

5564 { "(bad)",» » { XX } },	5907 { Bad_Opcode },

5565 { "(bad)",» » { XX } },	5908 { Bad_Opcode },

5566 { "(bad)",» » { XX } },	5909 { Bad_Opcode },

5567 { "(bad)",» » { XX } },	5910 { Bad_Opcode },

5568 /* 58 */	5911 /* 58 */

5569 { "(bad)",» » { XX } },	5912 { Bad_Opcode },

5570 { "(bad)",» » { XX } },	5913 { Bad_Opcode },

5571 { "(bad)",» » { XX } },	5914 { Bad_Opcode },

5572 { "(bad)",» » { XX } },	5915 { Bad_Opcode },

5573 { "(bad)",» » { XX } },	5916 { Bad_Opcode },

5574 { "(bad)",» » { XX } },	5917 { Bad_Opcode },

5575 { "(bad)",» » { XX } },	5918 { Bad_Opcode },

5576 { "(bad)",» » { XX } },	5919 { Bad_Opcode },

5577 /* 60 */	5920 /* 60 */

5578 { "(bad)",» » { XX } },	5921 { Bad_Opcode },

5579 { "(bad)",» » { XX } },	5922 { Bad_Opcode },

5580 { "(bad)",» » { XX } },	5923 { Bad_Opcode },

5581 { "(bad)",» » { XX } },	5924 { Bad_Opcode },

5582 { "(bad)",» » { XX } },	5925 { Bad_Opcode },

5583 { "(bad)",» » { XX } },	5926 { Bad_Opcode },

5584 { "(bad)",» » { XX } },	5927 { Bad_Opcode },

5585 { "(bad)",» » { XX } },	5928 { Bad_Opcode },

5586 /* 68 */	5929 /* 68 */

5587 { "(bad)",» » { XX } },	5930 { Bad_Opcode },

5588 { "(bad)",» » { XX } },	5931 { Bad_Opcode },

5589 { "(bad)",» » { XX } },	5932 { Bad_Opcode },

5590 { "(bad)",» » { XX } },	5933 { Bad_Opcode },

5591 { "(bad)",» » { XX } },	5934 { Bad_Opcode },

5592 { "(bad)",» » { XX } },	5935 { Bad_Opcode },

5593 { "(bad)",» » { XX } },	5936 { Bad_Opcode },

5594 { "(bad)",» » { XX } },	5937 { Bad_Opcode },

5595 /* 70 */	5938 /* 70 */

5596 { "(bad)",» » { XX } },	5939 { Bad_Opcode },

5597 { "(bad)",» » { XX } },	5940 { Bad_Opcode },

5598 { "(bad)",» » { XX } },	5941 { Bad_Opcode },

5599 { "(bad)",» » { XX } },	5942 { Bad_Opcode },

5600 { "(bad)",» » { XX } },	5943 { Bad_Opcode },

5601 { "(bad)",» » { XX } },	5944 { Bad_Opcode },

5602 { "(bad)",» » { XX } },	5945 { Bad_Opcode },

5603 { "(bad)",» » { XX } },	5946 { Bad_Opcode },

5604 /* 78 */	5947 /* 78 */

5605 { "(bad)",» » { XX } },	5948 { Bad_Opcode },

5606 { "(bad)",» » { XX } },	5949 { Bad_Opcode },

5607 { "(bad)",» » { XX } },	5950 { Bad_Opcode },

5608 { "(bad)",» » { XX } },	5951 { Bad_Opcode },

5609 { "(bad)",» » { XX } },	5952 { Bad_Opcode },

5610 { "(bad)",» » { XX } },	5953 { Bad_Opcode },

5611 { "(bad)",» » { XX } },	5954 { Bad_Opcode },

5612 { "(bad)",» » { XX } },	5955 { Bad_Opcode },

5613 /* 80 */	5956 /* 80 */

5614 { PREFIX_TABLE (PREFIX_0F3880) },	5957 { PREFIX_TABLE (PREFIX_0F3880) },

5615 { PREFIX_TABLE (PREFIX_0F3881) },	5958 { PREFIX_TABLE (PREFIX_0F3881) },

5616 { "(bad)",» » { XX } },	5959 { PREFIX_TABLE (PREFIX_0F3882) },

5617 { "(bad)",» » { XX } },	5960 { Bad_Opcode },

5618 { "(bad)",» » { XX } },	5961 { Bad_Opcode },

5619 { "(bad)",» » { XX } },	5962 { Bad_Opcode },

5620 { "(bad)",» » { XX } },	5963 { Bad_Opcode },

5621 { "(bad)",» » { XX } },	5964 { Bad_Opcode },

5622 /* 88 */	5965 /* 88 */

5623 { "(bad)",» » { XX } },	5966 { Bad_Opcode },

5624 { "(bad)",» » { XX } },	5967 { Bad_Opcode },

5625 { "(bad)",» » { XX } },	5968 { Bad_Opcode },

5626 { "(bad)",» » { XX } },	5969 { Bad_Opcode },

5627 { "(bad)",» » { XX } },	5970 { Bad_Opcode },

5628 { "(bad)",» » { XX } },	5971 { Bad_Opcode },

5629 { "(bad)",» » { XX } },	5972 { Bad_Opcode },

5630 { "(bad)",» » { XX } },	5973 { Bad_Opcode },

5631 /* 90 */	5974 /* 90 */

5632 { "(bad)",» » { XX } },	5975 { Bad_Opcode },

5633 { "(bad)",» » { XX } },	5976 { Bad_Opcode },

5634 { "(bad)",» » { XX } },	5977 { Bad_Opcode },

5635 { "(bad)",» » { XX } },	5978 { Bad_Opcode },

5636 { "(bad)",» » { XX } },	5979 { Bad_Opcode },

5637 { "(bad)",» » { XX } },	5980 { Bad_Opcode },

5638 { "(bad)",» » { XX } },	5981 { Bad_Opcode },

5639 { "(bad)",» » { XX } },	5982 { Bad_Opcode },

5640 /* 98 */	5983 /* 98 */

5641 { "(bad)",» » { XX } },	5984 { Bad_Opcode },

5642 { "(bad)",» » { XX } },	5985 { Bad_Opcode },

5643 { "(bad)",» » { XX } },	5986 { Bad_Opcode },

5644 { "(bad)",» » { XX } },	5987 { Bad_Opcode },

5645 { "(bad)",» » { XX } },	5988 { Bad_Opcode },

5646 { "(bad)",» » { XX } },	5989 { Bad_Opcode },

5647 { "(bad)",» » { XX } },	5990 { Bad_Opcode },

5648 { "(bad)",» » { XX } },	5991 { Bad_Opcode },

5649 /* a0 */	5992 /* a0 */

5650 { "(bad)",» » { XX } },	5993 { Bad_Opcode },

5651 { "(bad)",» » { XX } },	5994 { Bad_Opcode },

5652 { "(bad)",» » { XX } },	5995 { Bad_Opcode },

5653 { "(bad)",» » { XX } },	5996 { Bad_Opcode },

5654 { "(bad)",» » { XX } },	5997 { Bad_Opcode },

5655 { "(bad)",» » { XX } },	5998 { Bad_Opcode },

5656 { "(bad)",» » { XX } },	5999 { Bad_Opcode },

5657 { "(bad)",» » { XX } },	6000 { Bad_Opcode },

5658 /* a8 */	6001 /* a8 */

5659 { "(bad)",» » { XX } },	6002 { Bad_Opcode },

5660 { "(bad)",» » { XX } },	6003 { Bad_Opcode },

5661 { "(bad)",» » { XX } },	6004 { Bad_Opcode },

5662 { "(bad)",» » { XX } },	6005 { Bad_Opcode },

5663 { "(bad)",» » { XX } },	6006 { Bad_Opcode },

5664 { "(bad)",» » { XX } },	6007 { Bad_Opcode },

5665 { "(bad)",» » { XX } },	6008 { Bad_Opcode },

5666 { "(bad)",» » { XX } },	6009 { Bad_Opcode },

5667 /* b0 */	6010 /* b0 */

5668 { "(bad)",» » { XX } },	6011 { Bad_Opcode },

5669 { "(bad)",» » { XX } },	6012 { Bad_Opcode },

5670 { "(bad)",» » { XX } },	6013 { Bad_Opcode },

5671 { "(bad)",» » { XX } },	6014 { Bad_Opcode },

5672 { "(bad)",» » { XX } },	6015 { Bad_Opcode },

5673 { "(bad)",» » { XX } },	6016 { Bad_Opcode },

5674 { "(bad)",» » { XX } },	6017 { Bad_Opcode },

5675 { "(bad)",» » { XX } },	6018 { Bad_Opcode },

5676 /* b8 */	6019 /* b8 */

5677 { "(bad)",» » { XX } },	6020 { Bad_Opcode },

5678 { "(bad)",» » { XX } },	6021 { Bad_Opcode },

5679 { "(bad)",» » { XX } },	6022 { Bad_Opcode },

5680 { "(bad)",» » { XX } },	6023 { Bad_Opcode },

5681 { "(bad)",» » { XX } },	6024 { Bad_Opcode },

5682 { "(bad)",» » { XX } },	6025 { Bad_Opcode },

5683 { "(bad)",» » { XX } },	6026 { Bad_Opcode },

5684 { "(bad)",» » { XX } },	6027 { Bad_Opcode },

5685 /* c0 */	6028 /* c0 */

5686 { "(bad)",» » { XX } },	6029 { Bad_Opcode },

5687 { "(bad)",» » { XX } },	6030 { Bad_Opcode },

5688 { "(bad)",» » { XX } },	6031 { Bad_Opcode },

5689 { "(bad)",» » { XX } },	6032 { Bad_Opcode },

5690 { "(bad)",» » { XX } },	6033 { Bad_Opcode },

5691 { "(bad)",» » { XX } },	6034 { Bad_Opcode },

5692 { "(bad)",» » { XX } },	6035 { Bad_Opcode },

5693 { "(bad)",» » { XX } },	6036 { Bad_Opcode },

5694 /* c8 */	6037 /* c8 */

5695 { "(bad)",» » { XX } },	6038 { Bad_Opcode },

5696 { "(bad)",» » { XX } },	6039 { Bad_Opcode },

5697 { "(bad)",» » { XX } },	6040 { Bad_Opcode },

5698 { "(bad)",» » { XX } },	6041 { Bad_Opcode },

5699 { "(bad)",» » { XX } },	6042 { Bad_Opcode },

5700 { "(bad)",» » { XX } },	6043 { Bad_Opcode },

5701 { "(bad)",» » { XX } },	6044 { Bad_Opcode },

5702 { "(bad)",» » { XX } },	6045 { Bad_Opcode },

5703 /* d0 */	6046 /* d0 */

5704 { "(bad)",» » { XX } },	6047 { Bad_Opcode },

5705 { "(bad)",» » { XX } },	6048 { Bad_Opcode },

5706 { "(bad)",» » { XX } },	6049 { Bad_Opcode },

5707 { "(bad)",» » { XX } },	6050 { Bad_Opcode },

5708 { "(bad)",» » { XX } },	6051 { Bad_Opcode },

5709 { "(bad)",» » { XX } },	6052 { Bad_Opcode },

5710 { "(bad)",» » { XX } },	6053 { Bad_Opcode },

5711 { "(bad)",» » { XX } },	6054 { Bad_Opcode },

5712 /* d8 */	6055 /* d8 */

5713 { "(bad)",» » { XX } },	6056 { Bad_Opcode },

5714 { "(bad)",» » { XX } },	6057 { Bad_Opcode },

5715 { "(bad)",» » { XX } },	6058 { Bad_Opcode },

5716 { PREFIX_TABLE (PREFIX_0F38DB) },	6059 { PREFIX_TABLE (PREFIX_0F38DB) },

5717 { PREFIX_TABLE (PREFIX_0F38DC) },	6060 { PREFIX_TABLE (PREFIX_0F38DC) },

5718 { PREFIX_TABLE (PREFIX_0F38DD) },	6061 { PREFIX_TABLE (PREFIX_0F38DD) },

5719 { PREFIX_TABLE (PREFIX_0F38DE) },	6062 { PREFIX_TABLE (PREFIX_0F38DE) },

5720 { PREFIX_TABLE (PREFIX_0F38DF) },	6063 { PREFIX_TABLE (PREFIX_0F38DF) },

5721 /* e0 */	6064 /* e0 */

5722 { "(bad)",» » { XX } },	6065 { Bad_Opcode },

5723 { "(bad)",» » { XX } },	6066 { Bad_Opcode },

5724 { "(bad)",» » { XX } },	6067 { Bad_Opcode },

5725 { "(bad)",» » { XX } },	6068 { Bad_Opcode },

5726 { "(bad)",» » { XX } },	6069 { Bad_Opcode },

5727 { "(bad)",» » { XX } },	6070 { Bad_Opcode },

5728 { "(bad)",» » { XX } },	6071 { Bad_Opcode },

5729 { "(bad)",» » { XX } },	6072 { Bad_Opcode },

5730 /* e8 */	6073 /* e8 */

5731 { "(bad)",» » { XX } },	6074 { Bad_Opcode },

5732 { "(bad)",» » { XX } },	6075 { Bad_Opcode },

5733 { "(bad)",» » { XX } },	6076 { Bad_Opcode },

5734 { "(bad)",» » { XX } },	6077 { Bad_Opcode },

5735 { "(bad)",» » { XX } },	6078 { Bad_Opcode },

5736 { "(bad)",» » { XX } },	6079 { Bad_Opcode },

5737 { "(bad)",» » { XX } },	6080 { Bad_Opcode },

5738 { "(bad)",» » { XX } },	6081 { Bad_Opcode },

5739 /* f0 */	6082 /* f0 */

5740 { PREFIX_TABLE (PREFIX_0F38F0) },	6083 { PREFIX_TABLE (PREFIX_0F38F0) },

5741 { PREFIX_TABLE (PREFIX_0F38F1) },	6084 { PREFIX_TABLE (PREFIX_0F38F1) },

5742 { "(bad)",» » { XX } },	6085 { Bad_Opcode },

5743 { "(bad)",» » { XX } },	6086 { Bad_Opcode },

5744 { "(bad)",» » { XX } },	6087 { Bad_Opcode },

5745 { "(bad)",» » { XX } },	6088 { Bad_Opcode },

5746 { "(bad)",» » { XX } },	6089 { PREFIX_TABLE (PREFIX_0F38F6) },

5747 { "(bad)",» » { XX } },	6090 { Bad_Opcode },

5748 /* f8 */	6091 /* f8 */

5749 { "(bad)",» » { XX } },	6092 { Bad_Opcode },

5750 { "(bad)",» » { XX } },	6093 { Bad_Opcode },

5751 { "(bad)",» » { XX } },	6094 { Bad_Opcode },

5752 { "(bad)",» » { XX } },	6095 { Bad_Opcode },

5753 { "(bad)",» » { XX } },	6096 { Bad_Opcode },

5754 { "(bad)",» » { XX } },	6097 { Bad_Opcode },

5755 { "(bad)",» » { XX } },	6098 { Bad_Opcode },

5756 { "(bad)",» » { XX } },	6099 { Bad_Opcode },

5757 },	6100 },

5758 /* THREE_BYTE_0F3A */	6101 /* THREE_BYTE_0F3A */

5759 {	6102 {

5760 /* 00 */	6103 /* 00 */

5761 { "(bad)",» » { XX } },	6104 { Bad_Opcode },

5762 { "(bad)",» » { XX } },	6105 { Bad_Opcode },

5763 { "(bad)",» » { XX } },	6106 { Bad_Opcode },

5764 { "(bad)",» » { XX } },	6107 { Bad_Opcode },

5765 { "(bad)",» » { XX } },	6108 { Bad_Opcode },

5766 { "(bad)",» » { XX } },	6109 { Bad_Opcode },

5767 { "(bad)",» » { XX } },	6110 { Bad_Opcode },

5768 { "(bad)",» » { XX } },	6111 { Bad_Opcode },

5769 /* 08 */	6112 /* 08 */

5770 { PREFIX_TABLE (PREFIX_0F3A08) },	6113 { PREFIX_TABLE (PREFIX_0F3A08) },

5771 { PREFIX_TABLE (PREFIX_0F3A09) },	6114 { PREFIX_TABLE (PREFIX_0F3A09) },

5772 { PREFIX_TABLE (PREFIX_0F3A0A) },	6115 { PREFIX_TABLE (PREFIX_0F3A0A) },

5773 { PREFIX_TABLE (PREFIX_0F3A0B) },	6116 { PREFIX_TABLE (PREFIX_0F3A0B) },

5774 { PREFIX_TABLE (PREFIX_0F3A0C) },	6117 { PREFIX_TABLE (PREFIX_0F3A0C) },

5775 { PREFIX_TABLE (PREFIX_0F3A0D) },	6118 { PREFIX_TABLE (PREFIX_0F3A0D) },

5776 { PREFIX_TABLE (PREFIX_0F3A0E) },	6119 { PREFIX_TABLE (PREFIX_0F3A0E) },

5777 { "palignr", { MX, EM, Ib } },	6120 { "palignr", { MX, EM, Ib } },

5778 /* 10 */	6121 /* 10 */

5779 { "(bad)",» » { XX } },	6122 { Bad_Opcode },

5780 { "(bad)",» » { XX } },	6123 { Bad_Opcode },

5781 { "(bad)",» » { XX } },	6124 { Bad_Opcode },

5782 { "(bad)",» » { XX } },	6125 { Bad_Opcode },

5783 { PREFIX_TABLE (PREFIX_0F3A14) },	6126 { PREFIX_TABLE (PREFIX_0F3A14) },

5784 { PREFIX_TABLE (PREFIX_0F3A15) },	6127 { PREFIX_TABLE (PREFIX_0F3A15) },

5785 { PREFIX_TABLE (PREFIX_0F3A16) },	6128 { PREFIX_TABLE (PREFIX_0F3A16) },

5786 { PREFIX_TABLE (PREFIX_0F3A17) },	6129 { PREFIX_TABLE (PREFIX_0F3A17) },

5787 /* 18 */	6130 /* 18 */

5788 { "(bad)",» » { XX } },	6131 { Bad_Opcode },

5789 { "(bad)",» » { XX } },	6132 { Bad_Opcode },

5790 { "(bad)",» » { XX } },	6133 { Bad_Opcode },

5791 { "(bad)",» » { XX } },	6134 { Bad_Opcode },

5792 { "(bad)",» » { XX } },	6135 { Bad_Opcode },

5793 { "(bad)",» » { XX } },	6136 { Bad_Opcode },

5794 { "(bad)",» » { XX } },	6137 { Bad_Opcode },

5795 { "(bad)",» » { XX } },	6138 { Bad_Opcode },

5796 /* 20 */	6139 /* 20 */

5797 { PREFIX_TABLE (PREFIX_0F3A20) },	6140 { PREFIX_TABLE (PREFIX_0F3A20) },

5798 { PREFIX_TABLE (PREFIX_0F3A21) },	6141 { PREFIX_TABLE (PREFIX_0F3A21) },

5799 { PREFIX_TABLE (PREFIX_0F3A22) },	6142 { PREFIX_TABLE (PREFIX_0F3A22) },

5800 { "(bad)",» » { XX } },	6143 { Bad_Opcode },

5801 { "(bad)",» » { XX } },	6144 { Bad_Opcode },

5802 { "(bad)",» » { XX } },	6145 { Bad_Opcode },

5803 { "(bad)",» » { XX } },	6146 { Bad_Opcode },

5804 { "(bad)",» » { XX } },	6147 { Bad_Opcode },

5805 /* 28 */	6148 /* 28 */

5806 { "(bad)",» » { XX } },	6149 { Bad_Opcode },

5807 { "(bad)",» » { XX } },	6150 { Bad_Opcode },

5808 { "(bad)",» » { XX } },	6151 { Bad_Opcode },

5809 { "(bad)",» » { XX } },	6152 { Bad_Opcode },

5810 { "(bad)",» » { XX } },	6153 { Bad_Opcode },

5811 { "(bad)",» » { XX } },	6154 { Bad_Opcode },

5812 { "(bad)",» » { XX } },	6155 { Bad_Opcode },

5813 { "(bad)",» » { XX } },	6156 { Bad_Opcode },

5814 /* 30 */	6157 /* 30 */

5815 { "(bad)",» » { XX } },	6158 { Bad_Opcode },

5816 { "(bad)",» » { XX } },	6159 { Bad_Opcode },

5817 { "(bad)",» » { XX } },	6160 { Bad_Opcode },

5818 { "(bad)",» » { XX } },	6161 { Bad_Opcode },

5819 { "(bad)",» » { XX } },	6162 { Bad_Opcode },

5820 { "(bad)",» » { XX } },	6163 { Bad_Opcode },

5821 { "(bad)",» » { XX } },	6164 { Bad_Opcode },

5822 { "(bad)",» » { XX } },	6165 { Bad_Opcode },

5823 /* 38 */	6166 /* 38 */

5824 { "(bad)",» » { XX } },	6167 { Bad_Opcode },

5825 { "(bad)",» » { XX } },	6168 { Bad_Opcode },

5826 { "(bad)",» » { XX } },	6169 { Bad_Opcode },

5827 { "(bad)",» » { XX } },	6170 { Bad_Opcode },

5828 { "(bad)",» » { XX } },	6171 { Bad_Opcode },

5829 { "(bad)",» » { XX } },	6172 { Bad_Opcode },

5830 { "(bad)",» » { XX } },	6173 { Bad_Opcode },

5831 { "(bad)",» » { XX } },	6174 { Bad_Opcode },

5832 /* 40 */	6175 /* 40 */

5833 { PREFIX_TABLE (PREFIX_0F3A40) },	6176 { PREFIX_TABLE (PREFIX_0F3A40) },

5834 { PREFIX_TABLE (PREFIX_0F3A41) },	6177 { PREFIX_TABLE (PREFIX_0F3A41) },

5835 { PREFIX_TABLE (PREFIX_0F3A42) },	6178 { PREFIX_TABLE (PREFIX_0F3A42) },

5836 { "(bad)",» » { XX } },	6179 { Bad_Opcode },

5837 { PREFIX_TABLE (PREFIX_0F3A44) },	6180 { PREFIX_TABLE (PREFIX_0F3A44) },

5838 { "(bad)",» » { XX } },	6181 { Bad_Opcode },

5839 { "(bad)",» » { XX } },	6182 { Bad_Opcode },

5840 { "(bad)",» » { XX } },	6183 { Bad_Opcode },

5841 /* 48 */	6184 /* 48 */

5842 { "(bad)",» » { XX } },	6185 { Bad_Opcode },

5843 { "(bad)",» » { XX } },	6186 { Bad_Opcode },

5844 { "(bad)",» » { XX } },	6187 { Bad_Opcode },

5845 { "(bad)",» » { XX } },	6188 { Bad_Opcode },

5846 { "(bad)",» » { XX } },	6189 { Bad_Opcode },

5847 { "(bad)",» » { XX } },	6190 { Bad_Opcode },

5848 { "(bad)",» » { XX } },	6191 { Bad_Opcode },

5849 { "(bad)",» » { XX } },	6192 { Bad_Opcode },

5850 /* 50 */	6193 /* 50 */

5851 { "(bad)",» » { XX } },	6194 { Bad_Opcode },

5852 { "(bad)",» » { XX } },	6195 { Bad_Opcode },

5853 { "(bad)",» » { XX } },	6196 { Bad_Opcode },

5854 { "(bad)",» » { XX } },	6197 { Bad_Opcode },

5855 { "(bad)",» » { XX } },	6198 { Bad_Opcode },

5856 { "(bad)",» » { XX } },	6199 { Bad_Opcode },

5857 { "(bad)",» » { XX } },	6200 { Bad_Opcode },

5858 { "(bad)",» » { XX } },	6201 { Bad_Opcode },

5859 /* 58 */	6202 /* 58 */

5860 { "(bad)",» » { XX } },	6203 { Bad_Opcode },

5861 { "(bad)",» » { XX } },	6204 { Bad_Opcode },

5862 { "(bad)",» » { XX } },	6205 { Bad_Opcode },

5863 { "(bad)",» » { XX } },	6206 { Bad_Opcode },

5864 { "(bad)",» » { XX } },	6207 { Bad_Opcode },

5865 { "(bad)",» » { XX } },	6208 { Bad_Opcode },

5866 { "(bad)",» » { XX } },	6209 { Bad_Opcode },

5867 { "(bad)",» » { XX } },	6210 { Bad_Opcode },

5868 /* 60 */	6211 /* 60 */

5869 { PREFIX_TABLE (PREFIX_0F3A60) },	6212 { PREFIX_TABLE (PREFIX_0F3A60) },

5870 { PREFIX_TABLE (PREFIX_0F3A61) },	6213 { PREFIX_TABLE (PREFIX_0F3A61) },

5871 { PREFIX_TABLE (PREFIX_0F3A62) },	6214 { PREFIX_TABLE (PREFIX_0F3A62) },

5872 { PREFIX_TABLE (PREFIX_0F3A63) },	6215 { PREFIX_TABLE (PREFIX_0F3A63) },

5873 { "(bad)",» » { XX } },	6216 { Bad_Opcode },

5874 { "(bad)",» » { XX } },	6217 { Bad_Opcode },

5875 { "(bad)",» » { XX } },	6218 { Bad_Opcode },

5876 { "(bad)",» » { XX } },	6219 { Bad_Opcode },

5877 /* 68 */	6220 /* 68 */

5878 { "(bad)",» » { XX } },	6221 { Bad_Opcode },

5879 { "(bad)",» » { XX } },	6222 { Bad_Opcode },

5880 { "(bad)",» » { XX } },	6223 { Bad_Opcode },

5881 { "(bad)",» » { XX } },	6224 { Bad_Opcode },

5882 { "(bad)",» » { XX } },	6225 { Bad_Opcode },

5883 { "(bad)",» » { XX } },	6226 { Bad_Opcode },

5884 { "(bad)",» » { XX } },	6227 { Bad_Opcode },

5885 { "(bad)",» » { XX } },	6228 { Bad_Opcode },

5886 /* 70 */	6229 /* 70 */

5887 { "(bad)",» » { XX } },	6230 { Bad_Opcode },

5888 { "(bad)",» » { XX } },	6231 { Bad_Opcode },

5889 { "(bad)",» » { XX } },	6232 { Bad_Opcode },

5890 { "(bad)",» » { XX } },	6233 { Bad_Opcode },

5891 { "(bad)",» » { XX } },	6234 { Bad_Opcode },

5892 { "(bad)",» » { XX } },	6235 { Bad_Opcode },

5893 { "(bad)",» » { XX } },	6236 { Bad_Opcode },

5894 { "(bad)",» » { XX } },	6237 { Bad_Opcode },

5895 /* 78 */	6238 /* 78 */

5896 { "(bad)",» » { XX } },	6239 { Bad_Opcode },

5897 { "(bad)",» » { XX } },	6240 { Bad_Opcode },

5898 { "(bad)",» » { XX } },	6241 { Bad_Opcode },

5899 { "(bad)",» » { XX } },	6242 { Bad_Opcode },

5900 { "(bad)",» » { XX } },	6243 { Bad_Opcode },

5901 { "(bad)",» » { XX } },	6244 { Bad_Opcode },

5902 { "(bad)",» » { XX } },	6245 { Bad_Opcode },

5903 { "(bad)",» » { XX } },	6246 { Bad_Opcode },

5904 /* 80 */	6247 /* 80 */

5905 { "(bad)",» » { XX } },	6248 { Bad_Opcode },

5906 { "(bad)",» » { XX } },	6249 { Bad_Opcode },

5907 { "(bad)",» » { XX } },	6250 { Bad_Opcode },

5908 { "(bad)",» » { XX } },	6251 { Bad_Opcode },

5909 { "(bad)",» » { XX } },	6252 { Bad_Opcode },

5910 { "(bad)",» » { XX } },	6253 { Bad_Opcode },

5911 { "(bad)",» » { XX } },	6254 { Bad_Opcode },

5912 { "(bad)",» » { XX } },	6255 { Bad_Opcode },

5913 /* 88 */	6256 /* 88 */

5914 { "(bad)",» » { XX } },	6257 { Bad_Opcode },

5915 { "(bad)",» » { XX } },	6258 { Bad_Opcode },

5916 { "(bad)",» » { XX } },	6259 { Bad_Opcode },

5917 { "(bad)",» » { XX } },	6260 { Bad_Opcode },

5918 { "(bad)",» » { XX } },	6261 { Bad_Opcode },

5919 { "(bad)",» » { XX } },	6262 { Bad_Opcode },

5920 { "(bad)",» » { XX } },	6263 { Bad_Opcode },

5921 { "(bad)",» » { XX } },	6264 { Bad_Opcode },

5922 /* 90 */	6265 /* 90 */

5923 { "(bad)",» » { XX } },	6266 { Bad_Opcode },

5924 { "(bad)",» » { XX } },	6267 { Bad_Opcode },

5925 { "(bad)",» » { XX } },	6268 { Bad_Opcode },

5926 { "(bad)",» » { XX } },	6269 { Bad_Opcode },

5927 { "(bad)",» » { XX } },	6270 { Bad_Opcode },

5928 { "(bad)",» » { XX } },	6271 { Bad_Opcode },

5929 { "(bad)",» » { XX } },	6272 { Bad_Opcode },

5930 { "(bad)",» » { XX } },	6273 { Bad_Opcode },

5931 /* 98 */	6274 /* 98 */

5932 { "(bad)",» » { XX } },	6275 { Bad_Opcode },

5933 { "(bad)",» » { XX } },	6276 { Bad_Opcode },

5934 { "(bad)",» » { XX } },	6277 { Bad_Opcode },

5935 { "(bad)",» » { XX } },	6278 { Bad_Opcode },

5936 { "(bad)",» » { XX } },	6279 { Bad_Opcode },

5937 { "(bad)",» » { XX } },	6280 { Bad_Opcode },

5938 { "(bad)",» » { XX } },	6281 { Bad_Opcode },

5939 { "(bad)",» » { XX } },	6282 { Bad_Opcode },

5940 /* a0 */	6283 /* a0 */

5941 { "(bad)",» » { XX } },	6284 { Bad_Opcode },

5942 { "(bad)",» » { XX } },	6285 { Bad_Opcode },

5943 { "(bad)",» » { XX } },	6286 { Bad_Opcode },

5944 { "(bad)",» » { XX } },	6287 { Bad_Opcode },

5945 { "(bad)",» » { XX } },	6288 { Bad_Opcode },

5946 { "(bad)",» » { XX } },	6289 { Bad_Opcode },

5947 { "(bad)",» » { XX } },	6290 { Bad_Opcode },

5948 { "(bad)",» » { XX } },	6291 { Bad_Opcode },

5949 /* a8 */	6292 /* a8 */

5950 { "(bad)",» » { XX } },	6293 { Bad_Opcode },

5951 { "(bad)",» » { XX } },	6294 { Bad_Opcode },

5952 { "(bad)",» » { XX } },	6295 { Bad_Opcode },

5953 { "(bad)",» » { XX } },	6296 { Bad_Opcode },

5954 { "(bad)",» » { XX } },	6297 { Bad_Opcode },

5955 { "(bad)",» » { XX } },	6298 { Bad_Opcode },

5956 { "(bad)",» » { XX } },	6299 { Bad_Opcode },

5957 { "(bad)",» » { XX } },	6300 { Bad_Opcode },

5958 /* b0 */	6301 /* b0 */

5959 { "(bad)",» » { XX } },	6302 { Bad_Opcode },

5960 { "(bad)",» » { XX } },	6303 { Bad_Opcode },

5961 { "(bad)",» » { XX } },	6304 { Bad_Opcode },

5962 { "(bad)",» » { XX } },	6305 { Bad_Opcode },

5963 { "(bad)",» » { XX } },	6306 { Bad_Opcode },

5964 { "(bad)",» » { XX } },	6307 { Bad_Opcode },

5965 { "(bad)",» » { XX } },	6308 { Bad_Opcode },

5966 { "(bad)",» » { XX } },	6309 { Bad_Opcode },

5967 /* b8 */	6310 /* b8 */

5968 { "(bad)",» » { XX } },	6311 { Bad_Opcode },

5969 { "(bad)",» » { XX } },	6312 { Bad_Opcode },

5970 { "(bad)",» » { XX } },	6313 { Bad_Opcode },

5971 { "(bad)",» » { XX } },	6314 { Bad_Opcode },

5972 { "(bad)",» » { XX } },	6315 { Bad_Opcode },

5973 { "(bad)",» » { XX } },	6316 { Bad_Opcode },

5974 { "(bad)",» » { XX } },	6317 { Bad_Opcode },

5975 { "(bad)",» » { XX } },	6318 { Bad_Opcode },

5976 /* c0 */	6319 /* c0 */

5977 { "(bad)",» » { XX } },	6320 { Bad_Opcode },

5978 { "(bad)",» » { XX } },	6321 { Bad_Opcode },

5979 { "(bad)",» » { XX } },	6322 { Bad_Opcode },

5980 { "(bad)",» » { XX } },	6323 { Bad_Opcode },

5981 { "(bad)",» » { XX } },	6324 { Bad_Opcode },

5982 { "(bad)",» » { XX } },	6325 { Bad_Opcode },

5983 { "(bad)",» » { XX } },	6326 { Bad_Opcode },

5984 { "(bad)",» » { XX } },	6327 { Bad_Opcode },

5985 /* c8 */	6328 /* c8 */

5986 { "(bad)",» » { XX } },	6329 { Bad_Opcode },

5987 { "(bad)",» » { XX } },	6330 { Bad_Opcode },

5988 { "(bad)",» » { XX } },	6331 { Bad_Opcode },

5989 { "(bad)",» » { XX } },	6332 { Bad_Opcode },

5990 { "(bad)",» » { XX } },	6333 { Bad_Opcode },

5991 { "(bad)",» » { XX } },	6334 { Bad_Opcode },

5992 { "(bad)",» » { XX } },	6335 { Bad_Opcode },

5993 { "(bad)",» » { XX } },	6336 { Bad_Opcode },

5994 /* d0 */	6337 /* d0 */

5995 { "(bad)",» » { XX } },	6338 { Bad_Opcode },

5996 { "(bad)",» » { XX } },	6339 { Bad_Opcode },

5997 { "(bad)",» » { XX } },	6340 { Bad_Opcode },

5998 { "(bad)",» » { XX } },	6341 { Bad_Opcode },

5999 { "(bad)",» » { XX } },	6342 { Bad_Opcode },

6000 { "(bad)",» » { XX } },	6343 { Bad_Opcode },

6001 { "(bad)",» » { XX } },	6344 { Bad_Opcode },

6002 { "(bad)",» » { XX } },	6345 { Bad_Opcode },

6003 /* d8 */	6346 /* d8 */

6004 { "(bad)",» » { XX } },	6347 { Bad_Opcode },

6005 { "(bad)",» » { XX } },	6348 { Bad_Opcode },

6006 { "(bad)",» » { XX } },	6349 { Bad_Opcode },

6007 { "(bad)",» » { XX } },	6350 { Bad_Opcode },

6008 { "(bad)",» » { XX } },	6351 { Bad_Opcode },

6009 { "(bad)",» » { XX } },	6352 { Bad_Opcode },

6010 { "(bad)",» » { XX } },	6353 { Bad_Opcode },

6011 { PREFIX_TABLE (PREFIX_0F3ADF) },	6354 { PREFIX_TABLE (PREFIX_0F3ADF) },

6012 /* e0 */	6355 /* e0 */

6013 { "(bad)",» » { XX } },	6356 { Bad_Opcode },

6014 { "(bad)",» » { XX } },	6357 { Bad_Opcode },

6015 { "(bad)",» » { XX } },	6358 { Bad_Opcode },

6016 { "(bad)",» » { XX } },	6359 { Bad_Opcode },

6017 { "(bad)",» » { XX } },	6360 { Bad_Opcode },

6018 { "(bad)",» » { XX } },	6361 { Bad_Opcode },

6019 { "(bad)",» » { XX } },	6362 { Bad_Opcode },

6020 { "(bad)",» » { XX } },	6363 { Bad_Opcode },

6021 /* e8 */	6364 /* e8 */

6022 { "(bad)",» » { XX } },	6365 { Bad_Opcode },

6023 { "(bad)",» » { XX } },	6366 { Bad_Opcode },

6024 { "(bad)",» » { XX } },	6367 { Bad_Opcode },

6025 { "(bad)",» » { XX } },	6368 { Bad_Opcode },

6026 { "(bad)",» » { XX } },	6369 { Bad_Opcode },

6027 { "(bad)",» » { XX } },	6370 { Bad_Opcode },

6028 { "(bad)",» » { XX } },	6371 { Bad_Opcode },

6029 { "(bad)",» » { XX } },	6372 { Bad_Opcode },

6030 /* f0 */	6373 /* f0 */

6031 { "(bad)",» » { XX } },	6374 { Bad_Opcode },

6032 { "(bad)",» » { XX } },	6375 { Bad_Opcode },

6033 { "(bad)",» » { XX } },	6376 { Bad_Opcode },

6034 { "(bad)",» » { XX } },	6377 { Bad_Opcode },

6035 { "(bad)",» » { XX } },	6378 { Bad_Opcode },

6036 { "(bad)",» » { XX } },	6379 { Bad_Opcode },

6037 { "(bad)",» » { XX } },	6380 { Bad_Opcode },

6038 { "(bad)",» » { XX } },	6381 { Bad_Opcode },

6039 /* f8 */	6382 /* f8 */

6040 { "(bad)",» » { XX } },	6383 { Bad_Opcode },

6041 { "(bad)",» » { XX } },	6384 { Bad_Opcode },

6042 { "(bad)",» » { XX } },	6385 { Bad_Opcode },

6043 { "(bad)",» » { XX } },	6386 { Bad_Opcode },

6044 { "(bad)",» » { XX } },	6387 { Bad_Opcode },

6045 { "(bad)",» » { XX } },	6388 { Bad_Opcode },

6046 { "(bad)",» » { XX } },	6389 { Bad_Opcode },

6047 { "(bad)",» » { XX } },	6390 { Bad_Opcode },

6048 },	6391 },

6049	6392

6050 /* THREE_BYTE_0F7A */	6393 /* THREE_BYTE_0F7A */

6051 {	6394 {

6052 /* 00 */	6395 /* 00 */

6053 { "(bad)",» » { XX } },	6396 { Bad_Opcode },

6054 { "(bad)",» » { XX } },	6397 { Bad_Opcode },

6055 { "(bad)",» » { XX } },	6398 { Bad_Opcode },

6056 { "(bad)",» » { XX } },	6399 { Bad_Opcode },

6057 { "(bad)",» » { XX } },	6400 { Bad_Opcode },

6058 { "(bad)",» » { XX } },	6401 { Bad_Opcode },

6059 { "(bad)",» » { XX } },	6402 { Bad_Opcode },

6060 { "(bad)",» » { XX } },	6403 { Bad_Opcode },

6061 /* 08 */	6404 /* 08 */

6062 { "(bad)",» » { XX } },	6405 { Bad_Opcode },

6063 { "(bad)",» » { XX } },	6406 { Bad_Opcode },

6064 { "(bad)",» » { XX } },	6407 { Bad_Opcode },

6065 { "(bad)",» » { XX } },	6408 { Bad_Opcode },

6066 { "(bad)",» » { XX } },	6409 { Bad_Opcode },

6067 { "(bad)",» » { XX } },	6410 { Bad_Opcode },

6068 { "(bad)",» » { XX } },	6411 { Bad_Opcode },

6069 { "(bad)",» » { XX } },	6412 { Bad_Opcode },

6070 /* 10 */	6413 /* 10 */

6071 { "(bad)",» » { XX } },	6414 { Bad_Opcode },

6072 { "(bad)",» » { XX } },	6415 { Bad_Opcode },

6073 { "(bad)",» » { XX } },	6416 { Bad_Opcode },

6074 { "(bad)",» » { XX } },	6417 { Bad_Opcode },

6075 { "(bad)",» » { XX } },	6418 { Bad_Opcode },

6076 { "(bad)",» » { XX } },	6419 { Bad_Opcode },

6077 { "(bad)",» » { XX } },	6420 { Bad_Opcode },

6078 { "(bad)",» » { XX } },	6421 { Bad_Opcode },

6079 /* 18 */	6422 /* 18 */

6080 { "(bad)",» » { XX } },	6423 { Bad_Opcode },

6081 { "(bad)",» » { XX } },	6424 { Bad_Opcode },

6082 { "(bad)",» » { XX } },	6425 { Bad_Opcode },

6083 { "(bad)",» » { XX } },	6426 { Bad_Opcode },

6084 { "(bad)",» » { XX } },	6427 { Bad_Opcode },

6085 { "(bad)",» » { XX } },	6428 { Bad_Opcode },

6086 { "(bad)",» » { XX } },	6429 { Bad_Opcode },

6087 { "(bad)",» » { XX } },	6430 { Bad_Opcode },

6088 /* 20 */	6431 /* 20 */

6089 { "ptest", { XX } },	6432 { "ptest", { XX } },

6090 { "(bad)",» » { XX } },	6433 { Bad_Opcode },

6091 { "(bad)",» » { XX } },	6434 { Bad_Opcode },

6092 { "(bad)",» » { XX } },	6435 { Bad_Opcode },

6093 { "(bad)",» » { XX } },	6436 { Bad_Opcode },

6094 { "(bad)",» » { XX } },	6437 { Bad_Opcode },

6095 { "(bad)",» » { XX } },	6438 { Bad_Opcode },

6096 { "(bad)",» » { XX } },	6439 { Bad_Opcode },

6097 /* 28 */	6440 /* 28 */

6098 { "(bad)",» » { XX } },	6441 { Bad_Opcode },

6099 { "(bad)",» » { XX } },	6442 { Bad_Opcode },

6100 { "(bad)",» » { XX } },	6443 { Bad_Opcode },

6101 { "(bad)",» » { XX } },	6444 { Bad_Opcode },

6102 { "(bad)",» » { XX } },	6445 { Bad_Opcode },

6103 { "(bad)",» » { XX } },	6446 { Bad_Opcode },

6104 { "(bad)",» » { XX } },	6447 { Bad_Opcode },

6105 { "(bad)",» » { XX } },	6448 { Bad_Opcode },

6106 /* 30 */	6449 /* 30 */

6107 { "(bad)",» » { XX } },	6450 { Bad_Opcode },

6108 { "(bad)",» » { XX } },	6451 { Bad_Opcode },

6109 { "(bad)",» » { XX } },	6452 { Bad_Opcode },

6110 { "(bad)",» » { XX } },	6453 { Bad_Opcode },

6111 { "(bad)",» » { XX } },	6454 { Bad_Opcode },

6112 { "(bad)",» » { XX } },	6455 { Bad_Opcode },

6113 { "(bad)",» » { XX } },	6456 { Bad_Opcode },

6114 { "(bad)",» » { XX } },	6457 { Bad_Opcode },

6115 /* 38 */	6458 /* 38 */

6116 { "(bad)",» » { XX } },	6459 { Bad_Opcode },

6117 { "(bad)",» » { XX } },	6460 { Bad_Opcode },

6118 { "(bad)",» » { XX } },	6461 { Bad_Opcode },

6119 { "(bad)",» » { XX } },	6462 { Bad_Opcode },

6120 { "(bad)",» » { XX } },	6463 { Bad_Opcode },

6121 { "(bad)",» » { XX } },	6464 { Bad_Opcode },

6122 { "(bad)",» » { XX } },	6465 { Bad_Opcode },

6123 { "(bad)",» » { XX } },	6466 { Bad_Opcode },

6124 /* 40 */	6467 /* 40 */

6125 { "(bad)",» » { XX } },	6468 { Bad_Opcode },

6126 { "phaddbw", { XM, EXq } },	6469 { "phaddbw", { XM, EXq } },

6127 { "phaddbd", { XM, EXq } },	6470 { "phaddbd", { XM, EXq } },

6128 { "phaddbq", { XM, EXq } },	6471 { "phaddbq", { XM, EXq } },

6129 { "(bad)",» » { XX } },	6472 { Bad_Opcode },

6130 { "(bad)",» » { XX } },	6473 { Bad_Opcode },

6131 { "phaddwd", { XM, EXq } },	6474 { "phaddwd", { XM, EXq } },

6132 { "phaddwq", { XM, EXq } },	6475 { "phaddwq", { XM, EXq } },

6133 /* 48 */	6476 /* 48 */

6134 { "(bad)",» » { XX } },	6477 { Bad_Opcode },

6135 { "(bad)",» » { XX } },	6478 { Bad_Opcode },

6136 { "(bad)",» » { XX } },	6479 { Bad_Opcode },

6137 { "phadddq", { XM, EXq } },	6480 { "phadddq", { XM, EXq } },

6138 { "(bad)",» » { XX } },	6481 { Bad_Opcode },

6139 { "(bad)",» » { XX } },	6482 { Bad_Opcode },

6140 { "(bad)",» » { XX } },	6483 { Bad_Opcode },

6141 { "(bad)",» » { XX } },	6484 { Bad_Opcode },

6142 /* 50 */	6485 /* 50 */

6143 { "(bad)",» » { XX } },	6486 { Bad_Opcode },

6144 { "phaddubw", { XM, EXq } },	6487 { "phaddubw", { XM, EXq } },

6145 { "phaddubd", { XM, EXq } },	6488 { "phaddubd", { XM, EXq } },

6146 { "phaddubq", { XM, EXq } },	6489 { "phaddubq", { XM, EXq } },

6147 { "(bad)",» » { XX } },	6490 { Bad_Opcode },

6148 { "(bad)",» » { XX } },	6491 { Bad_Opcode },

6149 { "phadduwd", { XM, EXq } },	6492 { "phadduwd", { XM, EXq } },

6150 { "phadduwq", { XM, EXq } },	6493 { "phadduwq", { XM, EXq } },

6151 /* 58 */	6494 /* 58 */

6152 { "(bad)",» » { XX } },	6495 { Bad_Opcode },

6153 { "(bad)",» » { XX } },	6496 { Bad_Opcode },

6154 { "(bad)",» » { XX } },	6497 { Bad_Opcode },

6155 { "phaddudq", { XM, EXq } },	6498 { "phaddudq", { XM, EXq } },

6156 { "(bad)",» » { XX } },	6499 { Bad_Opcode },

6157 { "(bad)",» » { XX } },	6500 { Bad_Opcode },

6158 { "(bad)",» » { XX } },	6501 { Bad_Opcode },

6159 { "(bad)",» » { XX } },	6502 { Bad_Opcode },

6160 /* 60 */	6503 /* 60 */

6161 { "(bad)",» » { XX } },	6504 { Bad_Opcode },

6162 { "phsubbw", { XM, EXq } },	6505 { "phsubbw", { XM, EXq } },

6163 { "phsubbd", { XM, EXq } },	6506 { "phsubbd", { XM, EXq } },

6164 { "phsubbq", { XM, EXq } },	6507 { "phsubbq", { XM, EXq } },

6165 { "(bad)",» » { XX } },	6508 { Bad_Opcode },

6166 { "(bad)",» » { XX } },	6509 { Bad_Opcode },

6167 { "(bad)",» » { XX } },	6510 { Bad_Opcode },

6168 { "(bad)",» » { XX } },	6511 { Bad_Opcode },

6169 /* 68 */	6512 /* 68 */

6170 { "(bad)",» » { XX } },	6513 { Bad_Opcode },

6171 { "(bad)",» » { XX } },	6514 { Bad_Opcode },

6172 { "(bad)",» » { XX } },	6515 { Bad_Opcode },

6173 { "(bad)",» » { XX } },	6516 { Bad_Opcode },

6174 { "(bad)",» » { XX } },	6517 { Bad_Opcode },

6175 { "(bad)",» » { XX } },	6518 { Bad_Opcode },

6176 { "(bad)",» » { XX } },	6519 { Bad_Opcode },

6177 { "(bad)",» » { XX } },	6520 { Bad_Opcode },

6178 /* 70 */	6521 /* 70 */

6179 { "(bad)",» » { XX } },	6522 { Bad_Opcode },

6180 { "(bad)",» » { XX } },	6523 { Bad_Opcode },

6181 { "(bad)",» » { XX } },	6524 { Bad_Opcode },

6182 { "(bad)",» » { XX } },	6525 { Bad_Opcode },

6183 { "(bad)",» » { XX } },	6526 { Bad_Opcode },

6184 { "(bad)",» » { XX } },	6527 { Bad_Opcode },

6185 { "(bad)",» » { XX } },	6528 { Bad_Opcode },

6186 { "(bad)",» » { XX } },	6529 { Bad_Opcode },

6187 /* 78 */	6530 /* 78 */

6188 { "(bad)",» » { XX } },	6531 { Bad_Opcode },

6189 { "(bad)",» » { XX } },	6532 { Bad_Opcode },

6190 { "(bad)",» » { XX } },	6533 { Bad_Opcode },

6191 { "(bad)",» » { XX } },	6534 { Bad_Opcode },

6192 { "(bad)",» » { XX } },	6535 { Bad_Opcode },

6193 { "(bad)",» » { XX } },	6536 { Bad_Opcode },

6194 { "(bad)",» » { XX } },	6537 { Bad_Opcode },

6195 { "(bad)",» » { XX } },	6538 { Bad_Opcode },

6196 /* 80 */	6539 /* 80 */

6197 { "(bad)",» » { XX } },	6540 { Bad_Opcode },

6198 { "(bad)",» » { XX } },	6541 { Bad_Opcode },

6199 { "(bad)",» » { XX } },	6542 { Bad_Opcode },

6200 { "(bad)",» » { XX } },	6543 { Bad_Opcode },

6201 { "(bad)",» » { XX } },	6544 { Bad_Opcode },

6202 { "(bad)",» » { XX } },	6545 { Bad_Opcode },

6203 { "(bad)",» » { XX } },	6546 { Bad_Opcode },

6204 { "(bad)",» » { XX } },	6547 { Bad_Opcode },

6205 /* 88 */	6548 /* 88 */

6206 { "(bad)",» » { XX } },	6549 { Bad_Opcode },

6207 { "(bad)",» » { XX } },	6550 { Bad_Opcode },

6208 { "(bad)",» » { XX } },	6551 { Bad_Opcode },

6209 { "(bad)",» » { XX } },	6552 { Bad_Opcode },

6210 { "(bad)",» » { XX } },	6553 { Bad_Opcode },

6211 { "(bad)",» » { XX } },	6554 { Bad_Opcode },

6212 { "(bad)",» » { XX } },	6555 { Bad_Opcode },

6213 { "(bad)",» » { XX } },	6556 { Bad_Opcode },

6214 /* 90 */	6557 /* 90 */

6215 { "(bad)",» » { XX } },	6558 { Bad_Opcode },

6216 { "(bad)",» » { XX } },	6559 { Bad_Opcode },

6217 { "(bad)",» » { XX } },	6560 { Bad_Opcode },

6218 { "(bad)",» » { XX } },	6561 { Bad_Opcode },

6219 { "(bad)",» » { XX } },	6562 { Bad_Opcode },

6220 { "(bad)",» » { XX } },	6563 { Bad_Opcode },

6221 { "(bad)",» » { XX } },	6564 { Bad_Opcode },

6222 { "(bad)",» » { XX } },	6565 { Bad_Opcode },

6223 /* 98 */	6566 /* 98 */

6224 { "(bad)",» » { XX } },	6567 { Bad_Opcode },

6225 { "(bad)",» » { XX } },	6568 { Bad_Opcode },

6226 { "(bad)",» » { XX } },	6569 { Bad_Opcode },

6227 { "(bad)",» » { XX } },	6570 { Bad_Opcode },

6228 { "(bad)",» » { XX } },	6571 { Bad_Opcode },

6229 { "(bad)",» » { XX } },	6572 { Bad_Opcode },

6230 { "(bad)",» » { XX } },	6573 { Bad_Opcode },

6231 { "(bad)",» » { XX } },	6574 { Bad_Opcode },

6232 /* a0 */	6575 /* a0 */

6233 { "(bad)",» » { XX } },	6576 { Bad_Opcode },

6234 { "(bad)",» » { XX } },	6577 { Bad_Opcode },

6235 { "(bad)",» » { XX } },	6578 { Bad_Opcode },

6236 { "(bad)",» » { XX } },	6579 { Bad_Opcode },

6237 { "(bad)",» » { XX } },	6580 { Bad_Opcode },

6238 { "(bad)",» » { XX } },	6581 { Bad_Opcode },

6239 { "(bad)",» » { XX } },	6582 { Bad_Opcode },

6240 { "(bad)",» » { XX } },	6583 { Bad_Opcode },

6241 /* a8 */	6584 /* a8 */

6242 { "(bad)",» » { XX } },	6585 { Bad_Opcode },

6243 { "(bad)",» » { XX } },	6586 { Bad_Opcode },

6244 { "(bad)",» » { XX } },	6587 { Bad_Opcode },

6245 { "(bad)",» » { XX } },	6588 { Bad_Opcode },

6246 { "(bad)",» » { XX } },	6589 { Bad_Opcode },

6247 { "(bad)",» » { XX } },	6590 { Bad_Opcode },

6248 { "(bad)",» » { XX } },	6591 { Bad_Opcode },

6249 { "(bad)",» » { XX } },	6592 { Bad_Opcode },

6250 /* b0 */	6593 /* b0 */

6251 { "(bad)",» » { XX } },	6594 { Bad_Opcode },

6252 { "(bad)",» » { XX } },	6595 { Bad_Opcode },

6253 { "(bad)",» » { XX } },	6596 { Bad_Opcode },

6254 { "(bad)",» » { XX } },	6597 { Bad_Opcode },

6255 { "(bad)",» » { XX } },	6598 { Bad_Opcode },

6256 { "(bad)",» » { XX } },	6599 { Bad_Opcode },

6257 { "(bad)",» » { XX } },	6600 { Bad_Opcode },

6258 { "(bad)",» » { XX } },	6601 { Bad_Opcode },

6259 /* b8 */	6602 /* b8 */

6260 { "(bad)",» » { XX } },	6603 { Bad_Opcode },

6261 { "(bad)",» » { XX } },	6604 { Bad_Opcode },

6262 { "(bad)",» » { XX } },	6605 { Bad_Opcode },

6263 { "(bad)",» » { XX } },	6606 { Bad_Opcode },

6264 { "(bad)",» » { XX } },	6607 { Bad_Opcode },

6265 { "(bad)",» » { XX } },	6608 { Bad_Opcode },

6266 { "(bad)",» » { XX } },	6609 { Bad_Opcode },

6267 { "(bad)",» » { XX } },	6610 { Bad_Opcode },

6268 /* c0 */	6611 /* c0 */

6269 { "(bad)",» » { XX } },	6612 { Bad_Opcode },

6270 { "(bad)",» » { XX } },	6613 { Bad_Opcode },

6271 { "(bad)",» » { XX } },	6614 { Bad_Opcode },

6272 { "(bad)",» » { XX } },	6615 { Bad_Opcode },

6273 { "(bad)",» » { XX } },	6616 { Bad_Opcode },

6274 { "(bad)",» » { XX } },	6617 { Bad_Opcode },

6275 { "(bad)",» » { XX } },	6618 { Bad_Opcode },

6276 { "(bad)",» » { XX } },	6619 { Bad_Opcode },

6277 /* c8 */	6620 /* c8 */

6278 { "(bad)",» » { XX } },	6621 { Bad_Opcode },

6279 { "(bad)",» » { XX } },	6622 { Bad_Opcode },

6280 { "(bad)",» » { XX } },	6623 { Bad_Opcode },

6281 { "(bad)",» » { XX } },	6624 { Bad_Opcode },

6282 { "(bad)",» » { XX } },	6625 { Bad_Opcode },

6283 { "(bad)",» » { XX } },	6626 { Bad_Opcode },

6284 { "(bad)",» » { XX } },	6627 { Bad_Opcode },

6285 { "(bad)",» » { XX } },	6628 { Bad_Opcode },

6286 /* d0 */	6629 /* d0 */

6287 { "(bad)",» » { XX } },	6630 { Bad_Opcode },

6288 { "(bad)",» » { XX } },	6631 { Bad_Opcode },

6289 { "(bad)",» » { XX } },	6632 { Bad_Opcode },

6290 { "(bad)",» » { XX } },	6633 { Bad_Opcode },

6291 { "(bad)",» » { XX } },	6634 { Bad_Opcode },

6292 { "(bad)",» » { XX } },	6635 { Bad_Opcode },

6293 { "(bad)",» » { XX } },	6636 { Bad_Opcode },

6294 { "(bad)",» » { XX } },	6637 { Bad_Opcode },

6295 /* d8 */	6638 /* d8 */

6296 { "(bad)",» » { XX } },	6639 { Bad_Opcode },

6297 { "(bad)",» » { XX } },	6640 { Bad_Opcode },

6298 { "(bad)",» » { XX } },	6641 { Bad_Opcode },

6299 { "(bad)",» » { XX } },	6642 { Bad_Opcode },

6300 { "(bad)",» » { XX } },	6643 { Bad_Opcode },

6301 { "(bad)",» » { XX } },	6644 { Bad_Opcode },

6302 { "(bad)",» » { XX } },	6645 { Bad_Opcode },

6303 { "(bad)",» » { XX } },	6646 { Bad_Opcode },

6304 /* e0 */	6647 /* e0 */

6305 { "(bad)",» » { XX } },	6648 { Bad_Opcode },

6306 { "(bad)",» » { XX } },	6649 { Bad_Opcode },

6307 { "(bad)",» » { XX } },	6650 { Bad_Opcode },

6308 { "(bad)",» » { XX } },	6651 { Bad_Opcode },

6309 { "(bad)",» » { XX } },	6652 { Bad_Opcode },

6310 { "(bad)",» » { XX } },	6653 { Bad_Opcode },

6311 { "(bad)",» » { XX } },	6654 { Bad_Opcode },

6312 { "(bad)",» » { XX } },	6655 { Bad_Opcode },

6313 /* e8 */	6656 /* e8 */

6314 { "(bad)",» » { XX } },	6657 { Bad_Opcode },

6315 { "(bad)",» » { XX } },	6658 { Bad_Opcode },

6316 { "(bad)",» » { XX } },	6659 { Bad_Opcode },

6317 { "(bad)",» » { XX } },	6660 { Bad_Opcode },

6318 { "(bad)",» » { XX } },	6661 { Bad_Opcode },

6319 { "(bad)",» » { XX } },	6662 { Bad_Opcode },

6320 { "(bad)",» » { XX } },	6663 { Bad_Opcode },

6321 { "(bad)",» » { XX } },	6664 { Bad_Opcode },

6322 /* f0 */	6665 /* f0 */

6323 { "(bad)",» » { XX } },	6666 { Bad_Opcode },

6324 { "(bad)",» » { XX } },	6667 { Bad_Opcode },

6325 { "(bad)",» » { XX } },	6668 { Bad_Opcode },

6326 { "(bad)",» » { XX } },	6669 { Bad_Opcode },

6327 { "(bad)",» » { XX } },	6670 { Bad_Opcode },

6328 { "(bad)",» » { XX } },	6671 { Bad_Opcode },

6329 { "(bad)",» » { XX } },	6672 { Bad_Opcode },

6330 { "(bad)",» » { XX } },	6673 { Bad_Opcode },

6331 /* f8 */	6674 /* f8 */

6332 { "(bad)",» » { XX } },	6675 { Bad_Opcode },

6333 { "(bad)",» » { XX } },	6676 { Bad_Opcode },

6334 { "(bad)",» » { XX } },	6677 { Bad_Opcode },

6335 { "(bad)",» » { XX } },	6678 { Bad_Opcode },

6336 { "(bad)",» » { XX } },	6679 { Bad_Opcode },

6337 { "(bad)",» » { XX } },	6680 { Bad_Opcode },

6338 { "(bad)",» » { XX } },	6681 { Bad_Opcode },

6339 { "(bad)",» » { XX } },	6682 { Bad_Opcode },

6340 },	6683 },

6341 };	6684 };

6342	6685

	6686 static const struct dis386 xop_table[][256] = {

	6687 /* XOP_08 */

	6688 {

	6689 /* 00 */

	6690 { Bad_Opcode },

	6691 { Bad_Opcode },

	6692 { Bad_Opcode },

	6693 { Bad_Opcode },

	6694 { Bad_Opcode },

	6695 { Bad_Opcode },

	6696 { Bad_Opcode },

	6697 { Bad_Opcode },

	6698 /* 08 */

	6699 { Bad_Opcode },

	6700 { Bad_Opcode },

	6701 { Bad_Opcode },

	6702 { Bad_Opcode },

	6703 { Bad_Opcode },

	6704 { Bad_Opcode },

	6705 { Bad_Opcode },

	6706 { Bad_Opcode },

	6707 /* 10 */

	6708 { Bad_Opcode },

	6709 { Bad_Opcode },

	6710 { Bad_Opcode },

	6711 { Bad_Opcode },

	6712 { Bad_Opcode },

	6713 { Bad_Opcode },

	6714 { Bad_Opcode },

	6715 { Bad_Opcode },

	6716 /* 18 */

	6717 { Bad_Opcode },

	6718 { Bad_Opcode },

	6719 { Bad_Opcode },

	6720 { Bad_Opcode },

	6721 { Bad_Opcode },

	6722 { Bad_Opcode },

	6723 { Bad_Opcode },

	6724 { Bad_Opcode },

	6725 /* 20 */

	6726 { Bad_Opcode },

	6727 { Bad_Opcode },

	6728 { Bad_Opcode },

	6729 { Bad_Opcode },

	6730 { Bad_Opcode },

	6731 { Bad_Opcode },

	6732 { Bad_Opcode },

	6733 { Bad_Opcode },

	6734 /* 28 */

	6735 { Bad_Opcode },

	6736 { Bad_Opcode },

	6737 { Bad_Opcode },

	6738 { Bad_Opcode },

	6739 { Bad_Opcode },

	6740 { Bad_Opcode },

	6741 { Bad_Opcode },

	6742 { Bad_Opcode },

	6743 /* 30 */

	6744 { Bad_Opcode },

	6745 { Bad_Opcode },

	6746 { Bad_Opcode },

	6747 { Bad_Opcode },

	6748 { Bad_Opcode },

	6749 { Bad_Opcode },

	6750 { Bad_Opcode },

	6751 { Bad_Opcode },

	6752 /* 38 */

	6753 { Bad_Opcode },

	6754 { Bad_Opcode },

	6755 { Bad_Opcode },

	6756 { Bad_Opcode },

	6757 { Bad_Opcode },

	6758 { Bad_Opcode },

	6759 { Bad_Opcode },

	6760 { Bad_Opcode },

	6761 /* 40 */

	6762 { Bad_Opcode },

	6763 { Bad_Opcode },

	6764 { Bad_Opcode },

	6765 { Bad_Opcode },

	6766 { Bad_Opcode },

	6767 { Bad_Opcode },

	6768 { Bad_Opcode },

	6769 { Bad_Opcode },

	6770 /* 48 */

	6771 { Bad_Opcode },

	6772 { Bad_Opcode },

	6773 { Bad_Opcode },

	6774 { Bad_Opcode },

	6775 { Bad_Opcode },

	6776 { Bad_Opcode },

	6777 { Bad_Opcode },

	6778 { Bad_Opcode },

	6779 /* 50 */

	6780 { Bad_Opcode },

	6781 { Bad_Opcode },

	6782 { Bad_Opcode },

	6783 { Bad_Opcode },

	6784 { Bad_Opcode },

	6785 { Bad_Opcode },

	6786 { Bad_Opcode },

	6787 { Bad_Opcode },

	6788 /* 58 */

	6789 { Bad_Opcode },

	6790 { Bad_Opcode },

	6791 { Bad_Opcode },

	6792 { Bad_Opcode },

	6793 { Bad_Opcode },

	6794 { Bad_Opcode },

	6795 { Bad_Opcode },

	6796 { Bad_Opcode },

	6797 /* 60 */

	6798 { Bad_Opcode },

	6799 { Bad_Opcode },

	6800 { Bad_Opcode },

	6801 { Bad_Opcode },

	6802 { Bad_Opcode },

	6803 { Bad_Opcode },

	6804 { Bad_Opcode },

	6805 { Bad_Opcode },

	6806 /* 68 */

	6807 { Bad_Opcode },

	6808 { Bad_Opcode },

	6809 { Bad_Opcode },

	6810 { Bad_Opcode },

	6811 { Bad_Opcode },

	6812 { Bad_Opcode },

	6813 { Bad_Opcode },

	6814 { Bad_Opcode },

	6815 /* 70 */

	6816 { Bad_Opcode },

	6817 { Bad_Opcode },

	6818 { Bad_Opcode },

	6819 { Bad_Opcode },

	6820 { Bad_Opcode },

	6821 { Bad_Opcode },

	6822 { Bad_Opcode },

	6823 { Bad_Opcode },

	6824 /* 78 */

	6825 { Bad_Opcode },

	6826 { Bad_Opcode },

	6827 { Bad_Opcode },

	6828 { Bad_Opcode },

	6829 { Bad_Opcode },

	6830 { Bad_Opcode },

	6831 { Bad_Opcode },

	6832 { Bad_Opcode },

	6833 /* 80 */

	6834 { Bad_Opcode },

	6835 { Bad_Opcode },

	6836 { Bad_Opcode },

	6837 { Bad_Opcode },

	6838 { Bad_Opcode },

	6839 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

	6840 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

	6841 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

	6842 /* 88 */

	6843 { Bad_Opcode },

	6844 { Bad_Opcode },

	6845 { Bad_Opcode },

	6846 { Bad_Opcode },

	6847 { Bad_Opcode },

	6848 { Bad_Opcode },

	6849 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

	6850 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

	6851 /* 90 */

	6852 { Bad_Opcode },

	6853 { Bad_Opcode },

	6854 { Bad_Opcode },

	6855 { Bad_Opcode },

	6856 { Bad_Opcode },

	6857 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

	6858 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

	6859 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

	6860 /* 98 */

	6861 { Bad_Opcode },

	6862 { Bad_Opcode },

	6863 { Bad_Opcode },

	6864 { Bad_Opcode },

	6865 { Bad_Opcode },

	6866 { Bad_Opcode },

	6867 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

	6868 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

	6869 /* a0 */

	6870 { Bad_Opcode },

	6871 { Bad_Opcode },

	6872 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

	6873 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

	6874 { Bad_Opcode },

	6875 { Bad_Opcode },

	6876 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

	6877 { Bad_Opcode },

	6878 /* a8 */

	6879 { Bad_Opcode },

	6880 { Bad_Opcode },

	6881 { Bad_Opcode },

	6882 { Bad_Opcode },

	6883 { Bad_Opcode },

	6884 { Bad_Opcode },

	6885 { Bad_Opcode },

	6886 { Bad_Opcode },

	6887 /* b0 */

	6888 { Bad_Opcode },

	6889 { Bad_Opcode },

	6890 { Bad_Opcode },

	6891 { Bad_Opcode },

	6892 { Bad_Opcode },

	6893 { Bad_Opcode },

	6894 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },

	6895 { Bad_Opcode },

	6896 /* b8 */

	6897 { Bad_Opcode },

	6898 { Bad_Opcode },

	6899 { Bad_Opcode },

	6900 { Bad_Opcode },

	6901 { Bad_Opcode },

	6902 { Bad_Opcode },

	6903 { Bad_Opcode },

	6904 { Bad_Opcode },

	6905 /* c0 */

	6906 { "vprotb", { XM, Vex_2src_1, Ib } },

	6907 { "vprotw", { XM, Vex_2src_1, Ib } },

	6908 { "vprotd", { XM, Vex_2src_1, Ib } },

	6909 { "vprotq", { XM, Vex_2src_1, Ib } },

	6910 { Bad_Opcode },

	6911 { Bad_Opcode },

	6912 { Bad_Opcode },

	6913 { Bad_Opcode },

	6914 /* c8 */

	6915 { Bad_Opcode },

	6916 { Bad_Opcode },

	6917 { Bad_Opcode },

	6918 { Bad_Opcode },

	6919 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },

	6920 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },

	6921 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },

	6922 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },

	6923 /* d0 */

	6924 { Bad_Opcode },

	6925 { Bad_Opcode },

	6926 { Bad_Opcode },

	6927 { Bad_Opcode },

	6928 { Bad_Opcode },

	6929 { Bad_Opcode },

	6930 { Bad_Opcode },

	6931 { Bad_Opcode },

	6932 /* d8 */

	6933 { Bad_Opcode },

	6934 { Bad_Opcode },

	6935 { Bad_Opcode },

	6936 { Bad_Opcode },

	6937 { Bad_Opcode },

	6938 { Bad_Opcode },

	6939 { Bad_Opcode },

	6940 { Bad_Opcode },

	6941 /* e0 */

	6942 { Bad_Opcode },

	6943 { Bad_Opcode },

	6944 { Bad_Opcode },

	6945 { Bad_Opcode },

	6946 { Bad_Opcode },

	6947 { Bad_Opcode },

	6948 { Bad_Opcode },

	6949 { Bad_Opcode },

	6950 /* e8 */

	6951 { Bad_Opcode },

	6952 { Bad_Opcode },

	6953 { Bad_Opcode },

	6954 { Bad_Opcode },

	6955 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },

	6956 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },

	6957 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },

	6958 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },

	6959 /* f0 */

	6960 { Bad_Opcode },

	6961 { Bad_Opcode },

	6962 { Bad_Opcode },

	6963 { Bad_Opcode },

	6964 { Bad_Opcode },

	6965 { Bad_Opcode },

	6966 { Bad_Opcode },

	6967 { Bad_Opcode },

	6968 /* f8 */

	6969 { Bad_Opcode },

	6970 { Bad_Opcode },

	6971 { Bad_Opcode },

	6972 { Bad_Opcode },

	6973 { Bad_Opcode },

	6974 { Bad_Opcode },

	6975 { Bad_Opcode },

	6976 { Bad_Opcode },

	6977 },

	6978 /* XOP_09 */

	6979 {

	6980 /* 00 */

	6981 { Bad_Opcode },

	6982 { REG_TABLE (REG_XOP_TBM_01) },

	6983 { REG_TABLE (REG_XOP_TBM_02) },

	6984 { Bad_Opcode },

	6985 { Bad_Opcode },

	6986 { Bad_Opcode },

	6987 { Bad_Opcode },

	6988 { Bad_Opcode },

	6989 /* 08 */

	6990 { Bad_Opcode },

	6991 { Bad_Opcode },

	6992 { Bad_Opcode },

	6993 { Bad_Opcode },

	6994 { Bad_Opcode },

	6995 { Bad_Opcode },

	6996 { Bad_Opcode },

	6997 { Bad_Opcode },

	6998 /* 10 */

	6999 { Bad_Opcode },

	7000 { Bad_Opcode },

	7001 { REG_TABLE (REG_XOP_LWPCB) },

	7002 { Bad_Opcode },

	7003 { Bad_Opcode },

	7004 { Bad_Opcode },

	7005 { Bad_Opcode },

	7006 { Bad_Opcode },

	7007 /* 18 */

	7008 { Bad_Opcode },

	7009 { Bad_Opcode },

	7010 { Bad_Opcode },

	7011 { Bad_Opcode },

	7012 { Bad_Opcode },

	7013 { Bad_Opcode },

	7014 { Bad_Opcode },

	7015 { Bad_Opcode },

	7016 /* 20 */

	7017 { Bad_Opcode },

	7018 { Bad_Opcode },

	7019 { Bad_Opcode },

	7020 { Bad_Opcode },

	7021 { Bad_Opcode },

	7022 { Bad_Opcode },

	7023 { Bad_Opcode },

	7024 { Bad_Opcode },

	7025 /* 28 */

	7026 { Bad_Opcode },

	7027 { Bad_Opcode },

	7028 { Bad_Opcode },

	7029 { Bad_Opcode },

	7030 { Bad_Opcode },

	7031 { Bad_Opcode },

	7032 { Bad_Opcode },

	7033 { Bad_Opcode },

	7034 /* 30 */

	7035 { Bad_Opcode },

	7036 { Bad_Opcode },

	7037 { Bad_Opcode },

	7038 { Bad_Opcode },

	7039 { Bad_Opcode },

	7040 { Bad_Opcode },

	7041 { Bad_Opcode },

	7042 { Bad_Opcode },

	7043 /* 38 */

	7044 { Bad_Opcode },

	7045 { Bad_Opcode },

	7046 { Bad_Opcode },

	7047 { Bad_Opcode },

	7048 { Bad_Opcode },

	7049 { Bad_Opcode },

	7050 { Bad_Opcode },

	7051 { Bad_Opcode },

	7052 /* 40 */

	7053 { Bad_Opcode },

	7054 { Bad_Opcode },

	7055 { Bad_Opcode },

	7056 { Bad_Opcode },

	7057 { Bad_Opcode },

	7058 { Bad_Opcode },

	7059 { Bad_Opcode },

	7060 { Bad_Opcode },

	7061 /* 48 */

	7062 { Bad_Opcode },

	7063 { Bad_Opcode },

	7064 { Bad_Opcode },

	7065 { Bad_Opcode },

	7066 { Bad_Opcode },

	7067 { Bad_Opcode },

	7068 { Bad_Opcode },

	7069 { Bad_Opcode },

	7070 /* 50 */

	7071 { Bad_Opcode },

	7072 { Bad_Opcode },

	7073 { Bad_Opcode },

	7074 { Bad_Opcode },

	7075 { Bad_Opcode },

	7076 { Bad_Opcode },

	7077 { Bad_Opcode },

	7078 { Bad_Opcode },

	7079 /* 58 */

	7080 { Bad_Opcode },

	7081 { Bad_Opcode },

	7082 { Bad_Opcode },

	7083 { Bad_Opcode },

	7084 { Bad_Opcode },

	7085 { Bad_Opcode },

	7086 { Bad_Opcode },

	7087 { Bad_Opcode },

	7088 /* 60 */

	7089 { Bad_Opcode },

	7090 { Bad_Opcode },

	7091 { Bad_Opcode },

	7092 { Bad_Opcode },

	7093 { Bad_Opcode },

	7094 { Bad_Opcode },

	7095 { Bad_Opcode },

	7096 { Bad_Opcode },

	7097 /* 68 */

	7098 { Bad_Opcode },

	7099 { Bad_Opcode },

	7100 { Bad_Opcode },

	7101 { Bad_Opcode },

	7102 { Bad_Opcode },

	7103 { Bad_Opcode },

	7104 { Bad_Opcode },

	7105 { Bad_Opcode },

	7106 /* 70 */

	7107 { Bad_Opcode },

	7108 { Bad_Opcode },

	7109 { Bad_Opcode },

	7110 { Bad_Opcode },

	7111 { Bad_Opcode },

	7112 { Bad_Opcode },

	7113 { Bad_Opcode },

	7114 { Bad_Opcode },

	7115 /* 78 */

	7116 { Bad_Opcode },

	7117 { Bad_Opcode },

	7118 { Bad_Opcode },

	7119 { Bad_Opcode },

	7120 { Bad_Opcode },

	7121 { Bad_Opcode },

	7122 { Bad_Opcode },

	7123 { Bad_Opcode },

	7124 /* 80 */

	7125 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },

	7126 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },

	7127 { "vfrczss", { XM, EXd } },

	7128 { "vfrczsd", { XM, EXq } },

	7129 { Bad_Opcode },

	7130 { Bad_Opcode },

	7131 { Bad_Opcode },

	7132 { Bad_Opcode },

	7133 /* 88 */

	7134 { Bad_Opcode },

	7135 { Bad_Opcode },

	7136 { Bad_Opcode },

	7137 { Bad_Opcode },

	7138 { Bad_Opcode },

	7139 { Bad_Opcode },

	7140 { Bad_Opcode },

	7141 { Bad_Opcode },

	7142 /* 90 */

	7143 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } },

	7144 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } },

	7145 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } },

	7146 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } },

	7147 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } },

	7148 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } },

	7149 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } },

	7150 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } },

	7151 /* 98 */

	7152 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } },

	7153 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } },

	7154 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } },

	7155 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } },

	7156 { Bad_Opcode },

	7157 { Bad_Opcode },

	7158 { Bad_Opcode },

	7159 { Bad_Opcode },

	7160 /* a0 */

	7161 { Bad_Opcode },

	7162 { Bad_Opcode },

	7163 { Bad_Opcode },

	7164 { Bad_Opcode },

	7165 { Bad_Opcode },

	7166 { Bad_Opcode },

	7167 { Bad_Opcode },

	7168 { Bad_Opcode },

	7169 /* a8 */

	7170 { Bad_Opcode },

	7171 { Bad_Opcode },

	7172 { Bad_Opcode },

	7173 { Bad_Opcode },

	7174 { Bad_Opcode },

	7175 { Bad_Opcode },

	7176 { Bad_Opcode },

	7177 { Bad_Opcode },

	7178 /* b0 */

	7179 { Bad_Opcode },

	7180 { Bad_Opcode },

	7181 { Bad_Opcode },

	7182 { Bad_Opcode },

	7183 { Bad_Opcode },

	7184 { Bad_Opcode },

	7185 { Bad_Opcode },

	7186 { Bad_Opcode },

	7187 /* b8 */

	7188 { Bad_Opcode },

	7189 { Bad_Opcode },

	7190 { Bad_Opcode },

	7191 { Bad_Opcode },

	7192 { Bad_Opcode },

	7193 { Bad_Opcode },

	7194 { Bad_Opcode },

	7195 { Bad_Opcode },

	7196 /* c0 */

	7197 { Bad_Opcode },

	7198 { "vphaddbw", { XM, EXxmm } },

	7199 { "vphaddbd", { XM, EXxmm } },

	7200 { "vphaddbq", { XM, EXxmm } },

	7201 { Bad_Opcode },

	7202 { Bad_Opcode },

	7203 { "vphaddwd", { XM, EXxmm } },

	7204 { "vphaddwq", { XM, EXxmm } },

	7205 /* c8 */

	7206 { Bad_Opcode },

	7207 { Bad_Opcode },

	7208 { Bad_Opcode },

	7209 { "vphadddq", { XM, EXxmm } },

	7210 { Bad_Opcode },

	7211 { Bad_Opcode },

	7212 { Bad_Opcode },

	7213 { Bad_Opcode },

	7214 /* d0 */

	7215 { Bad_Opcode },

	7216 { "vphaddubw", { XM, EXxmm } },

	7217 { "vphaddubd", { XM, EXxmm } },

	7218 { "vphaddubq", { XM, EXxmm } },

	7219 { Bad_Opcode },

	7220 { Bad_Opcode },

	7221 { "vphadduwd", { XM, EXxmm } },

	7222 { "vphadduwq", { XM, EXxmm } },

	7223 /* d8 */

	7224 { Bad_Opcode },

	7225 { Bad_Opcode },

	7226 { Bad_Opcode },

	7227 { "vphaddudq", { XM, EXxmm } },

	7228 { Bad_Opcode },

	7229 { Bad_Opcode },

	7230 { Bad_Opcode },

	7231 { Bad_Opcode },

	7232 /* e0 */

	7233 { Bad_Opcode },

	7234 { "vphsubbw", { XM, EXxmm } },

	7235 { "vphsubwd", { XM, EXxmm } },

	7236 { "vphsubdq", { XM, EXxmm } },

	7237 { Bad_Opcode },

	7238 { Bad_Opcode },

	7239 { Bad_Opcode },

	7240 { Bad_Opcode },

	7241 /* e8 */

	7242 { Bad_Opcode },

	7243 { Bad_Opcode },

	7244 { Bad_Opcode },

	7245 { Bad_Opcode },

	7246 { Bad_Opcode },

	7247 { Bad_Opcode },

	7248 { Bad_Opcode },

	7249 { Bad_Opcode },

	7250 /* f0 */

	7251 { Bad_Opcode },

	7252 { Bad_Opcode },

	7253 { Bad_Opcode },

	7254 { Bad_Opcode },

	7255 { Bad_Opcode },

	7256 { Bad_Opcode },

	7257 { Bad_Opcode },

	7258 { Bad_Opcode },

	7259 /* f8 */

	7260 { Bad_Opcode },

	7261 { Bad_Opcode },

	7262 { Bad_Opcode },

	7263 { Bad_Opcode },

	7264 { Bad_Opcode },

	7265 { Bad_Opcode },

	7266 { Bad_Opcode },

	7267 { Bad_Opcode },

	7268 },

	7269 /* XOP_0A */

	7270 {

	7271 /* 00 */

	7272 { Bad_Opcode },

	7273 { Bad_Opcode },

	7274 { Bad_Opcode },

	7275 { Bad_Opcode },

	7276 { Bad_Opcode },

	7277 { Bad_Opcode },

	7278 { Bad_Opcode },

	7279 { Bad_Opcode },

	7280 /* 08 */

	7281 { Bad_Opcode },

	7282 { Bad_Opcode },

	7283 { Bad_Opcode },

	7284 { Bad_Opcode },

	7285 { Bad_Opcode },

	7286 { Bad_Opcode },

	7287 { Bad_Opcode },

	7288 { Bad_Opcode },

	7289 /* 10 */

	7290 { "bextr", { Gv, Ev, Iq } },

	7291 { Bad_Opcode },

	7292 { REG_TABLE (REG_XOP_LWP) },

	7293 { Bad_Opcode },

	7294 { Bad_Opcode },

	7295 { Bad_Opcode },

	7296 { Bad_Opcode },

	7297 { Bad_Opcode },

	7298 /* 18 */

	7299 { Bad_Opcode },

	7300 { Bad_Opcode },

	7301 { Bad_Opcode },

	7302 { Bad_Opcode },

	7303 { Bad_Opcode },

	7304 { Bad_Opcode },

	7305 { Bad_Opcode },

	7306 { Bad_Opcode },

	7307 /* 20 */

	7308 { Bad_Opcode },

	7309 { Bad_Opcode },

	7310 { Bad_Opcode },

	7311 { Bad_Opcode },

	7312 { Bad_Opcode },

	7313 { Bad_Opcode },

	7314 { Bad_Opcode },

	7315 { Bad_Opcode },

	7316 /* 28 */

	7317 { Bad_Opcode },

	7318 { Bad_Opcode },

	7319 { Bad_Opcode },

	7320 { Bad_Opcode },

	7321 { Bad_Opcode },

	7322 { Bad_Opcode },

	7323 { Bad_Opcode },

	7324 { Bad_Opcode },

	7325 /* 30 */

	7326 { Bad_Opcode },

	7327 { Bad_Opcode },

	7328 { Bad_Opcode },

	7329 { Bad_Opcode },

	7330 { Bad_Opcode },

	7331 { Bad_Opcode },

	7332 { Bad_Opcode },

	7333 { Bad_Opcode },

	7334 /* 38 */

	7335 { Bad_Opcode },

	7336 { Bad_Opcode },

	7337 { Bad_Opcode },

	7338 { Bad_Opcode },

	7339 { Bad_Opcode },

	7340 { Bad_Opcode },

	7341 { Bad_Opcode },

	7342 { Bad_Opcode },

	7343 /* 40 */

	7344 { Bad_Opcode },

	7345 { Bad_Opcode },

	7346 { Bad_Opcode },

	7347 { Bad_Opcode },

	7348 { Bad_Opcode },

	7349 { Bad_Opcode },

	7350 { Bad_Opcode },

	7351 { Bad_Opcode },

	7352 /* 48 */

	7353 { Bad_Opcode },

	7354 { Bad_Opcode },

	7355 { Bad_Opcode },

	7356 { Bad_Opcode },

	7357 { Bad_Opcode },

	7358 { Bad_Opcode },

	7359 { Bad_Opcode },

	7360 { Bad_Opcode },

	7361 /* 50 */

	7362 { Bad_Opcode },

	7363 { Bad_Opcode },

	7364 { Bad_Opcode },

	7365 { Bad_Opcode },

	7366 { Bad_Opcode },

	7367 { Bad_Opcode },

	7368 { Bad_Opcode },

	7369 { Bad_Opcode },

	7370 /* 58 */

	7371 { Bad_Opcode },

	7372 { Bad_Opcode },

	7373 { Bad_Opcode },

	7374 { Bad_Opcode },

	7375 { Bad_Opcode },

	7376 { Bad_Opcode },

	7377 { Bad_Opcode },

	7378 { Bad_Opcode },

	7379 /* 60 */

	7380 { Bad_Opcode },

	7381 { Bad_Opcode },

	7382 { Bad_Opcode },

	7383 { Bad_Opcode },

	7384 { Bad_Opcode },

	7385 { Bad_Opcode },

	7386 { Bad_Opcode },

	7387 { Bad_Opcode },

	7388 /* 68 */

	7389 { Bad_Opcode },

	7390 { Bad_Opcode },

	7391 { Bad_Opcode },

	7392 { Bad_Opcode },

	7393 { Bad_Opcode },

	7394 { Bad_Opcode },

	7395 { Bad_Opcode },

	7396 { Bad_Opcode },

	7397 /* 70 */

	7398 { Bad_Opcode },

	7399 { Bad_Opcode },

	7400 { Bad_Opcode },

	7401 { Bad_Opcode },

	7402 { Bad_Opcode },

	7403 { Bad_Opcode },

	7404 { Bad_Opcode },

	7405 { Bad_Opcode },

	7406 /* 78 */

	7407 { Bad_Opcode },

	7408 { Bad_Opcode },

	7409 { Bad_Opcode },

	7410 { Bad_Opcode },

	7411 { Bad_Opcode },

	7412 { Bad_Opcode },

	7413 { Bad_Opcode },

	7414 { Bad_Opcode },

	7415 /* 80 */

	7416 { Bad_Opcode },

	7417 { Bad_Opcode },

	7418 { Bad_Opcode },

	7419 { Bad_Opcode },

	7420 { Bad_Opcode },

	7421 { Bad_Opcode },

	7422 { Bad_Opcode },

	7423 { Bad_Opcode },

	7424 /* 88 */

	7425 { Bad_Opcode },

	7426 { Bad_Opcode },

	7427 { Bad_Opcode },

	7428 { Bad_Opcode },

	7429 { Bad_Opcode },

	7430 { Bad_Opcode },

	7431 { Bad_Opcode },

	7432 { Bad_Opcode },

	7433 /* 90 */

	7434 { Bad_Opcode },

	7435 { Bad_Opcode },

	7436 { Bad_Opcode },

	7437 { Bad_Opcode },

	7438 { Bad_Opcode },

	7439 { Bad_Opcode },

	7440 { Bad_Opcode },

	7441 { Bad_Opcode },

	7442 /* 98 */

	7443 { Bad_Opcode },

	7444 { Bad_Opcode },

	7445 { Bad_Opcode },

	7446 { Bad_Opcode },

	7447 { Bad_Opcode },

	7448 { Bad_Opcode },

	7449 { Bad_Opcode },

	7450 { Bad_Opcode },

	7451 /* a0 */

	7452 { Bad_Opcode },

	7453 { Bad_Opcode },

	7454 { Bad_Opcode },

	7455 { Bad_Opcode },

	7456 { Bad_Opcode },

	7457 { Bad_Opcode },

	7458 { Bad_Opcode },

	7459 { Bad_Opcode },

	7460 /* a8 */

	7461 { Bad_Opcode },

	7462 { Bad_Opcode },

	7463 { Bad_Opcode },

	7464 { Bad_Opcode },

	7465 { Bad_Opcode },

	7466 { Bad_Opcode },

	7467 { Bad_Opcode },

	7468 { Bad_Opcode },

	7469 /* b0 */

	7470 { Bad_Opcode },

	7471 { Bad_Opcode },

	7472 { Bad_Opcode },

	7473 { Bad_Opcode },

	7474 { Bad_Opcode },

	7475 { Bad_Opcode },

	7476 { Bad_Opcode },

	7477 { Bad_Opcode },

	7478 /* b8 */

	7479 { Bad_Opcode },

	7480 { Bad_Opcode },

	7481 { Bad_Opcode },

	7482 { Bad_Opcode },

	7483 { Bad_Opcode },

	7484 { Bad_Opcode },

	7485 { Bad_Opcode },

	7486 { Bad_Opcode },

	7487 /* c0 */

	7488 { Bad_Opcode },

	7489 { Bad_Opcode },

	7490 { Bad_Opcode },

	7491 { Bad_Opcode },

	7492 { Bad_Opcode },

	7493 { Bad_Opcode },

	7494 { Bad_Opcode },

	7495 { Bad_Opcode },

	7496 /* c8 */

	7497 { Bad_Opcode },

	7498 { Bad_Opcode },

	7499 { Bad_Opcode },

	7500 { Bad_Opcode },

	7501 { Bad_Opcode },

	7502 { Bad_Opcode },

	7503 { Bad_Opcode },

	7504 { Bad_Opcode },

	7505 /* d0 */

	7506 { Bad_Opcode },

	7507 { Bad_Opcode },

	7508 { Bad_Opcode },

	7509 { Bad_Opcode },

	7510 { Bad_Opcode },

	7511 { Bad_Opcode },

	7512 { Bad_Opcode },

	7513 { Bad_Opcode },

	7514 /* d8 */

	7515 { Bad_Opcode },

	7516 { Bad_Opcode },

	7517 { Bad_Opcode },

	7518 { Bad_Opcode },

	7519 { Bad_Opcode },

	7520 { Bad_Opcode },

	7521 { Bad_Opcode },

	7522 { Bad_Opcode },

	7523 /* e0 */

	7524 { Bad_Opcode },

	7525 { Bad_Opcode },

	7526 { Bad_Opcode },

	7527 { Bad_Opcode },

	7528 { Bad_Opcode },

	7529 { Bad_Opcode },

	7530 { Bad_Opcode },

	7531 { Bad_Opcode },

	7532 /* e8 */

	7533 { Bad_Opcode },

	7534 { Bad_Opcode },

	7535 { Bad_Opcode },

	7536 { Bad_Opcode },

	7537 { Bad_Opcode },

	7538 { Bad_Opcode },

	7539 { Bad_Opcode },

	7540 { Bad_Opcode },

	7541 /* f0 */

	7542 { Bad_Opcode },

	7543 { Bad_Opcode },

	7544 { Bad_Opcode },

	7545 { Bad_Opcode },

	7546 { Bad_Opcode },

	7547 { Bad_Opcode },

	7548 { Bad_Opcode },

	7549 { Bad_Opcode },

	7550 /* f8 */

	7551 { Bad_Opcode },

	7552 { Bad_Opcode },

	7553 { Bad_Opcode },

	7554 { Bad_Opcode },

	7555 { Bad_Opcode },

	7556 { Bad_Opcode },

	7557 { Bad_Opcode },

	7558 { Bad_Opcode },

	7559 },

	7560 };

6343	7561

6344 static const struct dis386 vex_table[][256] = {	7562 static const struct dis386 vex_table[][256] = {

6345 /* VEX_0F */	7563 /* VEX_0F */

6346 {	7564 {

6347 /* 00 */	7565 /* 00 */

6348 { "(bad)",» » { XX } },	7566 { Bad_Opcode },

6349 { "(bad)",» » { XX } },	7567 { Bad_Opcode },

6350 { "(bad)",» » { XX } },	7568 { Bad_Opcode },

6351 { "(bad)",» » { XX } },	7569 { Bad_Opcode },

6352 { "(bad)",» » { XX } },	7570 { Bad_Opcode },

6353 { "(bad)",» » { XX } },	7571 { Bad_Opcode },

6354 { "(bad)",» » { XX } },	7572 { Bad_Opcode },

6355 { "(bad)",» » { XX } },	7573 { Bad_Opcode },

6356 /* 08 */	7574 /* 08 */

6357 { "(bad)",» » { XX } },	7575 { Bad_Opcode },

6358 { "(bad)",» » { XX } },	7576 { Bad_Opcode },

6359 { "(bad)",» » { XX } },	7577 { Bad_Opcode },

6360 { "(bad)",» » { XX } },	7578 { Bad_Opcode },

6361 { "(bad)",» » { XX } },	7579 { Bad_Opcode },

6362 { "(bad)",» » { XX } },	7580 { Bad_Opcode },

6363 { "(bad)",» » { XX } },	7581 { Bad_Opcode },

6364 { "(bad)",» » { XX } },	7582 { Bad_Opcode },

6365 /* 10 */	7583 /* 10 */

6366 { PREFIX_TABLE (PREFIX_VEX_10) },	7584 { PREFIX_TABLE (PREFIX_VEX_0F10) },

6367 { PREFIX_TABLE (PREFIX_VEX_11) },	7585 { PREFIX_TABLE (PREFIX_VEX_0F11) },

6368 { PREFIX_TABLE (PREFIX_VEX_12) },	7586 { PREFIX_TABLE (PREFIX_VEX_0F12) },

6369 { MOD_TABLE (MOD_VEX_13) },	7587 { MOD_TABLE (MOD_VEX_0F13) },

6370 { "vunpcklpX",» { XM, Vex, EXx } },	7588 { VEX_W_TABLE (VEX_W_0F14) },

6371 { "vunpckhpX",» { XM, Vex, EXx } },	7589 { VEX_W_TABLE (VEX_W_0F15) },

6372 { PREFIX_TABLE (PREFIX_VEX_16) },	7590 { PREFIX_TABLE (PREFIX_VEX_0F16) },

6373 { MOD_TABLE (MOD_VEX_17) },	7591 { MOD_TABLE (MOD_VEX_0F17) },

6374 /* 18 */	7592 /* 18 */

6375 { "(bad)",» » { XX } },	7593 { Bad_Opcode },

6376 { "(bad)",» » { XX } },	7594 { Bad_Opcode },

6377 { "(bad)",» » { XX } },	7595 { Bad_Opcode },

6378 { "(bad)",» » { XX } },	7596 { Bad_Opcode },

6379 { "(bad)",» » { XX } },	7597 { Bad_Opcode },

6380 { "(bad)",» » { XX } },	7598 { Bad_Opcode },

6381 { "(bad)",» » { XX } },	7599 { Bad_Opcode },

6382 { "(bad)",» » { XX } },	7600 { Bad_Opcode },

6383 /* 20 */	7601 /* 20 */

6384 { "(bad)",» » { XX } },	7602 { Bad_Opcode },

6385 { "(bad)",» » { XX } },	7603 { Bad_Opcode },

6386 { "(bad)",» » { XX } },	7604 { Bad_Opcode },

6387 { "(bad)",» » { XX } },	7605 { Bad_Opcode },

6388 { "(bad)",» » { XX } },	7606 { Bad_Opcode },

6389 { "(bad)",» » { XX } },	7607 { Bad_Opcode },

6390 { "(bad)",» » { XX } },	7608 { Bad_Opcode },

6391 { "(bad)",» » { XX } },	7609 { Bad_Opcode },

6392 /* 28 */	7610 /* 28 */

6393 { "vmovapX",» { XM, EXx } },	7611 { VEX_W_TABLE (VEX_W_0F28) },

6394 { "vmovapX",» { EXxS, XM } },	7612 { VEX_W_TABLE (VEX_W_0F29) },

6395 { PREFIX_TABLE (PREFIX_VEX_2A) },	7613 { PREFIX_TABLE (PREFIX_VEX_0F2A) },

6396 { MOD_TABLE (MOD_VEX_2B) },	7614 { MOD_TABLE (MOD_VEX_0F2B) },

6397 { PREFIX_TABLE (PREFIX_VEX_2C) },	7615 { PREFIX_TABLE (PREFIX_VEX_0F2C) },

6398 { PREFIX_TABLE (PREFIX_VEX_2D) },	7616 { PREFIX_TABLE (PREFIX_VEX_0F2D) },

6399 { PREFIX_TABLE (PREFIX_VEX_2E) },	7617 { PREFIX_TABLE (PREFIX_VEX_0F2E) },

6400 { PREFIX_TABLE (PREFIX_VEX_2F) },	7618 { PREFIX_TABLE (PREFIX_VEX_0F2F) },

6401 /* 30 */	7619 /* 30 */

6402 { "(bad)",» » { XX } },	7620 { Bad_Opcode },

6403 { "(bad)",» » { XX } },	7621 { Bad_Opcode },

6404 { "(bad)",» » { XX } },	7622 { Bad_Opcode },

6405 { "(bad)",» » { XX } },	7623 { Bad_Opcode },

6406 { "(bad)",» » { XX } },	7624 { Bad_Opcode },

6407 { "(bad)",» » { XX } },	7625 { Bad_Opcode },

6408 { "(bad)",» » { XX } },	7626 { Bad_Opcode },

6409 { "(bad)",» » { XX } },	7627 { Bad_Opcode },

6410 /* 38 */	7628 /* 38 */

6411 { "(bad)",» » { XX } },	7629 { Bad_Opcode },

6412 { "(bad)",» » { XX } },	7630 { Bad_Opcode },

6413 { "(bad)",» » { XX } },	7631 { Bad_Opcode },

6414 { "(bad)",» » { XX } },	7632 { Bad_Opcode },

6415 { "(bad)",» » { XX } },	7633 { Bad_Opcode },

6416 { "(bad)",» » { XX } },	7634 { Bad_Opcode },

6417 { "(bad)",» » { XX } },	7635 { Bad_Opcode },

6418 { "(bad)",» » { XX } },	7636 { Bad_Opcode },

6419 /* 40 */	7637 /* 40 */

6420 { "(bad)",» » { XX } },	7638 { Bad_Opcode },

6421 { "(bad)",» » { XX } },	7639 { Bad_Opcode },

6422 { "(bad)",» » { XX } },	7640 { Bad_Opcode },

6423 { "(bad)",» » { XX } },	7641 { Bad_Opcode },

6424 { "(bad)",» » { XX } },	7642 { Bad_Opcode },

6425 { "(bad)",» » { XX } },	7643 { Bad_Opcode },

6426 { "(bad)",» » { XX } },	7644 { Bad_Opcode },

6427 { "(bad)",» » { XX } },	7645 { Bad_Opcode },

6428 /* 48 */	7646 /* 48 */

6429 { "(bad)",» » { XX } },	7647 { Bad_Opcode },

6430 { "(bad)",» » { XX } },	7648 { Bad_Opcode },

6431 { "(bad)",» » { XX } },	7649 { Bad_Opcode },

6432 { "(bad)",» » { XX } },	7650 { Bad_Opcode },

6433 { "(bad)",» » { XX } },	7651 { Bad_Opcode },

6434 { "(bad)",» » { XX } },	7652 { Bad_Opcode },

6435 { "(bad)",» » { XX } },	7653 { Bad_Opcode },

6436 { "(bad)",» » { XX } },	7654 { Bad_Opcode },

6437 /* 50 */	7655 /* 50 */

6438 { MOD_TABLE (MOD_VEX_51) },	7656 { MOD_TABLE (MOD_VEX_0F50) },

6439 { PREFIX_TABLE (PREFIX_VEX_51) },	7657 { PREFIX_TABLE (PREFIX_VEX_0F51) },

6440 { PREFIX_TABLE (PREFIX_VEX_52) },	7658 { PREFIX_TABLE (PREFIX_VEX_0F52) },

6441 { PREFIX_TABLE (PREFIX_VEX_53) },	7659 { PREFIX_TABLE (PREFIX_VEX_0F53) },

6442 { "vandpX", { XM, Vex, EXx } },	7660 { "vandpX", { XM, Vex, EXx } },

6443 { "vandnpX", { XM, Vex, EXx } },	7661 { "vandnpX", { XM, Vex, EXx } },

6444 { "vorpX", { XM, Vex, EXx } },	7662 { "vorpX", { XM, Vex, EXx } },

6445 { "vxorpX", { XM, Vex, EXx } },	7663 { "vxorpX", { XM, Vex, EXx } },

6446 /* 58 */	7664 /* 58 */

6447 { PREFIX_TABLE (PREFIX_VEX_58) },	7665 { PREFIX_TABLE (PREFIX_VEX_0F58) },

6448 { PREFIX_TABLE (PREFIX_VEX_59) },	7666 { PREFIX_TABLE (PREFIX_VEX_0F59) },

6449 { PREFIX_TABLE (PREFIX_VEX_5A) },	7667 { PREFIX_TABLE (PREFIX_VEX_0F5A) },

6450 { PREFIX_TABLE (PREFIX_VEX_5B) },	7668 { PREFIX_TABLE (PREFIX_VEX_0F5B) },

6451 { PREFIX_TABLE (PREFIX_VEX_5C) },	7669 { PREFIX_TABLE (PREFIX_VEX_0F5C) },

6452 { PREFIX_TABLE (PREFIX_VEX_5D) },	7670 { PREFIX_TABLE (PREFIX_VEX_0F5D) },

6453 { PREFIX_TABLE (PREFIX_VEX_5E) },	7671 { PREFIX_TABLE (PREFIX_VEX_0F5E) },

6454 { PREFIX_TABLE (PREFIX_VEX_5F) },	7672 { PREFIX_TABLE (PREFIX_VEX_0F5F) },

6455 /* 60 */	7673 /* 60 */

6456 { PREFIX_TABLE (PREFIX_VEX_60) },	7674 { PREFIX_TABLE (PREFIX_VEX_0F60) },

6457 { PREFIX_TABLE (PREFIX_VEX_61) },	7675 { PREFIX_TABLE (PREFIX_VEX_0F61) },

6458 { PREFIX_TABLE (PREFIX_VEX_62) },	7676 { PREFIX_TABLE (PREFIX_VEX_0F62) },

6459 { PREFIX_TABLE (PREFIX_VEX_63) },	7677 { PREFIX_TABLE (PREFIX_VEX_0F63) },

6460 { PREFIX_TABLE (PREFIX_VEX_64) },	7678 { PREFIX_TABLE (PREFIX_VEX_0F64) },

6461 { PREFIX_TABLE (PREFIX_VEX_65) },	7679 { PREFIX_TABLE (PREFIX_VEX_0F65) },

6462 { PREFIX_TABLE (PREFIX_VEX_66) },	7680 { PREFIX_TABLE (PREFIX_VEX_0F66) },

6463 { PREFIX_TABLE (PREFIX_VEX_67) },	7681 { PREFIX_TABLE (PREFIX_VEX_0F67) },

6464 /* 68 */	7682 /* 68 */

6465 { PREFIX_TABLE (PREFIX_VEX_68) },	7683 { PREFIX_TABLE (PREFIX_VEX_0F68) },

6466 { PREFIX_TABLE (PREFIX_VEX_69) },	7684 { PREFIX_TABLE (PREFIX_VEX_0F69) },

6467 { PREFIX_TABLE (PREFIX_VEX_6A) },	7685 { PREFIX_TABLE (PREFIX_VEX_0F6A) },

6468 { PREFIX_TABLE (PREFIX_VEX_6B) },	7686 { PREFIX_TABLE (PREFIX_VEX_0F6B) },

6469 { PREFIX_TABLE (PREFIX_VEX_6C) },	7687 { PREFIX_TABLE (PREFIX_VEX_0F6C) },

6470 { PREFIX_TABLE (PREFIX_VEX_6D) },	7688 { PREFIX_TABLE (PREFIX_VEX_0F6D) },

6471 { PREFIX_TABLE (PREFIX_VEX_6E) },	7689 { PREFIX_TABLE (PREFIX_VEX_0F6E) },

6472 { PREFIX_TABLE (PREFIX_VEX_6F) },	7690 { PREFIX_TABLE (PREFIX_VEX_0F6F) },

6473 /* 70 */	7691 /* 70 */

6474 { PREFIX_TABLE (PREFIX_VEX_70) },	7692 { PREFIX_TABLE (PREFIX_VEX_0F70) },

6475 { REG_TABLE (REG_VEX_71) },	7693 { REG_TABLE (REG_VEX_0F71) },

6476 { REG_TABLE (REG_VEX_72) },	7694 { REG_TABLE (REG_VEX_0F72) },

6477 { REG_TABLE (REG_VEX_73) },	7695 { REG_TABLE (REG_VEX_0F73) },

6478 { PREFIX_TABLE (PREFIX_VEX_74) },	7696 { PREFIX_TABLE (PREFIX_VEX_0F74) },

6479 { PREFIX_TABLE (PREFIX_VEX_75) },	7697 { PREFIX_TABLE (PREFIX_VEX_0F75) },

6480 { PREFIX_TABLE (PREFIX_VEX_76) },	7698 { PREFIX_TABLE (PREFIX_VEX_0F76) },

6481 { PREFIX_TABLE (PREFIX_VEX_77) },	7699 { PREFIX_TABLE (PREFIX_VEX_0F77) },

6482 /* 78 */	7700 /* 78 */

6483 { "(bad)",» » { XX } },	7701 { Bad_Opcode },

6484 { "(bad)",» » { XX } },	7702 { Bad_Opcode },

6485 { "(bad)",» » { XX } },	7703 { Bad_Opcode },

6486 { "(bad)",» » { XX } },	7704 { Bad_Opcode },

6487 { PREFIX_TABLE (PREFIX_VEX_7C) },	7705 { PREFIX_TABLE (PREFIX_VEX_0F7C) },

6488 { PREFIX_TABLE (PREFIX_VEX_7D) },	7706 { PREFIX_TABLE (PREFIX_VEX_0F7D) },

6489 { PREFIX_TABLE (PREFIX_VEX_7E) },	7707 { PREFIX_TABLE (PREFIX_VEX_0F7E) },

6490 { PREFIX_TABLE (PREFIX_VEX_7F) },	7708 { PREFIX_TABLE (PREFIX_VEX_0F7F) },

6491 /* 80 */	7709 /* 80 */

6492 { "(bad)",» » { XX } },	7710 { Bad_Opcode },

6493 { "(bad)",» » { XX } },	7711 { Bad_Opcode },

6494 { "(bad)",» » { XX } },	7712 { Bad_Opcode },

6495 { "(bad)",» » { XX } },	7713 { Bad_Opcode },

6496 { "(bad)",» » { XX } },	7714 { Bad_Opcode },

6497 { "(bad)",» » { XX } },	7715 { Bad_Opcode },

6498 { "(bad)",» » { XX } },	7716 { Bad_Opcode },

6499 { "(bad)",» » { XX } },	7717 { Bad_Opcode },

6500 /* 88 */	7718 /* 88 */

6501 { "(bad)",» » { XX } },	7719 { Bad_Opcode },

6502 { "(bad)",» » { XX } },	7720 { Bad_Opcode },

6503 { "(bad)",» » { XX } },	7721 { Bad_Opcode },

6504 { "(bad)",» » { XX } },	7722 { Bad_Opcode },

6505 { "(bad)",» » { XX } },	7723 { Bad_Opcode },

6506 { "(bad)",» » { XX } },	7724 { Bad_Opcode },

6507 { "(bad)",» » { XX } },	7725 { Bad_Opcode },

6508 { "(bad)",» » { XX } },	7726 { Bad_Opcode },

6509 /* 90 */	7727 /* 90 */

6510 { "(bad)",» » { XX } },	7728 { Bad_Opcode },

6511 { "(bad)",» » { XX } },	7729 { Bad_Opcode },

6512 { "(bad)",» » { XX } },	7730 { Bad_Opcode },

6513 { "(bad)",» » { XX } },	7731 { Bad_Opcode },

6514 { "(bad)",» » { XX } },	7732 { Bad_Opcode },

6515 { "(bad)",» » { XX } },	7733 { Bad_Opcode },

6516 { "(bad)",» » { XX } },	7734 { Bad_Opcode },

6517 { "(bad)",» » { XX } },	7735 { Bad_Opcode },

6518 /* 98 */	7736 /* 98 */

6519 { "(bad)",» » { XX } },	7737 { Bad_Opcode },

6520 { "(bad)",» » { XX } },	7738 { Bad_Opcode },

6521 { "(bad)",» » { XX } },	7739 { Bad_Opcode },

6522 { "(bad)",» » { XX } },	7740 { Bad_Opcode },

6523 { "(bad)",» » { XX } },	7741 { Bad_Opcode },

6524 { "(bad)",» » { XX } },	7742 { Bad_Opcode },

6525 { "(bad)",» » { XX } },	7743 { Bad_Opcode },

6526 { "(bad)",» » { XX } },	7744 { Bad_Opcode },

6527 /* a0 */	7745 /* a0 */

6528 { "(bad)",» » { XX } },	7746 { Bad_Opcode },

6529 { "(bad)",» » { XX } },	7747 { Bad_Opcode },

6530 { "(bad)",» » { XX } },	7748 { Bad_Opcode },

6531 { "(bad)",» » { XX } },	7749 { Bad_Opcode },

6532 { "(bad)",» » { XX } },	7750 { Bad_Opcode },

6533 { "(bad)",» » { XX } },	7751 { Bad_Opcode },

6534 { "(bad)",» » { XX } },	7752 { Bad_Opcode },

6535 { "(bad)",» » { XX } },	7753 { Bad_Opcode },

6536 /* a8 */	7754 /* a8 */

6537 { "(bad)",» » { XX } },	7755 { Bad_Opcode },

6538 { "(bad)",» » { XX } },	7756 { Bad_Opcode },

6539 { "(bad)",» » { XX } },	7757 { Bad_Opcode },

6540 { "(bad)",» » { XX } },	7758 { Bad_Opcode },

6541 { "(bad)",» » { XX } },	7759 { Bad_Opcode },

6542 { "(bad)",» » { XX } },	7760 { Bad_Opcode },

6543 { REG_TABLE (REG_VEX_AE) },	7761 { REG_TABLE (REG_VEX_0FAE) },

6544 { "(bad)",» » { XX } },	7762 { Bad_Opcode },

6545 /* b0 */	7763 /* b0 */

6546 { "(bad)",» » { XX } },	7764 { Bad_Opcode },

6547 { "(bad)",» » { XX } },	7765 { Bad_Opcode },

6548 { "(bad)",» » { XX } },	7766 { Bad_Opcode },

6549 { "(bad)",» » { XX } },	7767 { Bad_Opcode },

6550 { "(bad)",» » { XX } },	7768 { Bad_Opcode },

6551 { "(bad)",» » { XX } },	7769 { Bad_Opcode },

6552 { "(bad)",» » { XX } },	7770 { Bad_Opcode },

6553 { "(bad)",» » { XX } },	7771 { Bad_Opcode },

6554 /* b8 */	7772 /* b8 */

6555 { "(bad)",» » { XX } },	7773 { Bad_Opcode },

6556 { "(bad)",» » { XX } },	7774 { Bad_Opcode },

6557 { "(bad)",» » { XX } },	7775 { Bad_Opcode },

6558 { "(bad)",» » { XX } },	7776 { Bad_Opcode },

6559 { "(bad)",» » { XX } },	7777 { Bad_Opcode },

6560 { "(bad)",» » { XX } },	7778 { Bad_Opcode },

6561 { "(bad)",» » { XX } },	7779 { Bad_Opcode },

6562 { "(bad)",» » { XX } },	7780 { Bad_Opcode },

6563 /* c0 */	7781 /* c0 */

6564 { "(bad)",» » { XX } },	7782 { Bad_Opcode },

6565 { "(bad)",» » { XX } },	7783 { Bad_Opcode },

6566 { PREFIX_TABLE (PREFIX_VEX_C2) },	7784 { PREFIX_TABLE (PREFIX_VEX_0FC2) },

6567 { "(bad)",» » { XX } },	7785 { Bad_Opcode },

6568 { PREFIX_TABLE (PREFIX_VEX_C4) },	7786 { PREFIX_TABLE (PREFIX_VEX_0FC4) },

6569 { PREFIX_TABLE (PREFIX_VEX_C5) },	7787 { PREFIX_TABLE (PREFIX_VEX_0FC5) },

6570 { "vshufpX", { XM, Vex, EXx, Ib } },	7788 { "vshufpX", { XM, Vex, EXx, Ib } },

6571 { "(bad)",» » { XX } },	7789 { Bad_Opcode },

6572 /* c8 */	7790 /* c8 */

6573 { "(bad)",» » { XX } },	7791 { Bad_Opcode },

6574 { "(bad)",» » { XX } },	7792 { Bad_Opcode },

6575 { "(bad)",» » { XX } },	7793 { Bad_Opcode },

6576 { "(bad)",» » { XX } },	7794 { Bad_Opcode },

6577 { "(bad)",» » { XX } },	7795 { Bad_Opcode },

6578 { "(bad)",» » { XX } },	7796 { Bad_Opcode },

6579 { "(bad)",» » { XX } },	7797 { Bad_Opcode },

6580 { "(bad)",» » { XX } },	7798 { Bad_Opcode },

6581 /* d0 */	7799 /* d0 */

6582 { PREFIX_TABLE (PREFIX_VEX_D0) },	7800 { PREFIX_TABLE (PREFIX_VEX_0FD0) },

6583 { PREFIX_TABLE (PREFIX_VEX_D1) },	7801 { PREFIX_TABLE (PREFIX_VEX_0FD1) },

6584 { PREFIX_TABLE (PREFIX_VEX_D2) },	7802 { PREFIX_TABLE (PREFIX_VEX_0FD2) },

6585 { PREFIX_TABLE (PREFIX_VEX_D3) },	7803 { PREFIX_TABLE (PREFIX_VEX_0FD3) },

6586 { PREFIX_TABLE (PREFIX_VEX_D4) },	7804 { PREFIX_TABLE (PREFIX_VEX_0FD4) },

6587 { PREFIX_TABLE (PREFIX_VEX_D5) },	7805 { PREFIX_TABLE (PREFIX_VEX_0FD5) },

6588 { PREFIX_TABLE (PREFIX_VEX_D6) },	7806 { PREFIX_TABLE (PREFIX_VEX_0FD6) },

6589 { PREFIX_TABLE (PREFIX_VEX_D7) },	7807 { PREFIX_TABLE (PREFIX_VEX_0FD7) },

6590 /* d8 */	7808 /* d8 */

6591 { PREFIX_TABLE (PREFIX_VEX_D8) },	7809 { PREFIX_TABLE (PREFIX_VEX_0FD8) },

6592 { PREFIX_TABLE (PREFIX_VEX_D9) },	7810 { PREFIX_TABLE (PREFIX_VEX_0FD9) },

6593 { PREFIX_TABLE (PREFIX_VEX_DA) },	7811 { PREFIX_TABLE (PREFIX_VEX_0FDA) },

6594 { PREFIX_TABLE (PREFIX_VEX_DB) },	7812 { PREFIX_TABLE (PREFIX_VEX_0FDB) },

6595 { PREFIX_TABLE (PREFIX_VEX_DC) },	7813 { PREFIX_TABLE (PREFIX_VEX_0FDC) },

6596 { PREFIX_TABLE (PREFIX_VEX_DD) },	7814 { PREFIX_TABLE (PREFIX_VEX_0FDD) },

6597 { PREFIX_TABLE (PREFIX_VEX_DE) },	7815 { PREFIX_TABLE (PREFIX_VEX_0FDE) },

6598 { PREFIX_TABLE (PREFIX_VEX_DF) },	7816 { PREFIX_TABLE (PREFIX_VEX_0FDF) },

6599 /* e0 */	7817 /* e0 */

6600 { PREFIX_TABLE (PREFIX_VEX_E0) },	7818 { PREFIX_TABLE (PREFIX_VEX_0FE0) },

6601 { PREFIX_TABLE (PREFIX_VEX_E1) },	7819 { PREFIX_TABLE (PREFIX_VEX_0FE1) },

6602 { PREFIX_TABLE (PREFIX_VEX_E2) },	7820 { PREFIX_TABLE (PREFIX_VEX_0FE2) },

6603 { PREFIX_TABLE (PREFIX_VEX_E3) },	7821 { PREFIX_TABLE (PREFIX_VEX_0FE3) },

6604 { PREFIX_TABLE (PREFIX_VEX_E4) },	7822 { PREFIX_TABLE (PREFIX_VEX_0FE4) },

6605 { PREFIX_TABLE (PREFIX_VEX_E5) },	7823 { PREFIX_TABLE (PREFIX_VEX_0FE5) },

6606 { PREFIX_TABLE (PREFIX_VEX_E6) },	7824 { PREFIX_TABLE (PREFIX_VEX_0FE6) },

6607 { PREFIX_TABLE (PREFIX_VEX_E7) },	7825 { PREFIX_TABLE (PREFIX_VEX_0FE7) },

6608 /* e8 */	7826 /* e8 */

6609 { PREFIX_TABLE (PREFIX_VEX_E8) },	7827 { PREFIX_TABLE (PREFIX_VEX_0FE8) },

6610 { PREFIX_TABLE (PREFIX_VEX_E9) },	7828 { PREFIX_TABLE (PREFIX_VEX_0FE9) },

6611 { PREFIX_TABLE (PREFIX_VEX_EA) },	7829 { PREFIX_TABLE (PREFIX_VEX_0FEA) },

6612 { PREFIX_TABLE (PREFIX_VEX_EB) },	7830 { PREFIX_TABLE (PREFIX_VEX_0FEB) },

6613 { PREFIX_TABLE (PREFIX_VEX_EC) },	7831 { PREFIX_TABLE (PREFIX_VEX_0FEC) },

6614 { PREFIX_TABLE (PREFIX_VEX_ED) },	7832 { PREFIX_TABLE (PREFIX_VEX_0FED) },

6615 { PREFIX_TABLE (PREFIX_VEX_EE) },	7833 { PREFIX_TABLE (PREFIX_VEX_0FEE) },

6616 { PREFIX_TABLE (PREFIX_VEX_EF) },	7834 { PREFIX_TABLE (PREFIX_VEX_0FEF) },

6617 /* f0 */	7835 /* f0 */

6618 { PREFIX_TABLE (PREFIX_VEX_F0) },	7836 { PREFIX_TABLE (PREFIX_VEX_0FF0) },

6619 { PREFIX_TABLE (PREFIX_VEX_F1) },	7837 { PREFIX_TABLE (PREFIX_VEX_0FF1) },

6620 { PREFIX_TABLE (PREFIX_VEX_F2) },	7838 { PREFIX_TABLE (PREFIX_VEX_0FF2) },

6621 { PREFIX_TABLE (PREFIX_VEX_F3) },	7839 { PREFIX_TABLE (PREFIX_VEX_0FF3) },

6622 { PREFIX_TABLE (PREFIX_VEX_F4) },	7840 { PREFIX_TABLE (PREFIX_VEX_0FF4) },

6623 { PREFIX_TABLE (PREFIX_VEX_F5) },	7841 { PREFIX_TABLE (PREFIX_VEX_0FF5) },

6624 { PREFIX_TABLE (PREFIX_VEX_F6) },	7842 { PREFIX_TABLE (PREFIX_VEX_0FF6) },

6625 { PREFIX_TABLE (PREFIX_VEX_F7) },	7843 { PREFIX_TABLE (PREFIX_VEX_0FF7) },

6626 /* f8 */	7844 /* f8 */

6627 { PREFIX_TABLE (PREFIX_VEX_F8) },	7845 { PREFIX_TABLE (PREFIX_VEX_0FF8) },

6628 { PREFIX_TABLE (PREFIX_VEX_F9) },	7846 { PREFIX_TABLE (PREFIX_VEX_0FF9) },

6629 { PREFIX_TABLE (PREFIX_VEX_FA) },	7847 { PREFIX_TABLE (PREFIX_VEX_0FFA) },

6630 { PREFIX_TABLE (PREFIX_VEX_FB) },	7848 { PREFIX_TABLE (PREFIX_VEX_0FFB) },

6631 { PREFIX_TABLE (PREFIX_VEX_FC) },	7849 { PREFIX_TABLE (PREFIX_VEX_0FFC) },

6632 { PREFIX_TABLE (PREFIX_VEX_FD) },	7850 { PREFIX_TABLE (PREFIX_VEX_0FFD) },

6633 { PREFIX_TABLE (PREFIX_VEX_FE) },	7851 { PREFIX_TABLE (PREFIX_VEX_0FFE) },

6634 { "(bad)",» » { XX } },	7852 { Bad_Opcode },

6635 },	7853 },

6636 /* VEX_0F38 */	7854 /* VEX_0F38 */

6637 {	7855 {

6638 /* 00 */	7856 /* 00 */

6639 { PREFIX_TABLE (PREFIX_VEX_3800) },	7857 { PREFIX_TABLE (PREFIX_VEX_0F3800) },

6640 { PREFIX_TABLE (PREFIX_VEX_3801) },	7858 { PREFIX_TABLE (PREFIX_VEX_0F3801) },

6641 { PREFIX_TABLE (PREFIX_VEX_3802) },	7859 { PREFIX_TABLE (PREFIX_VEX_0F3802) },

6642 { PREFIX_TABLE (PREFIX_VEX_3803) },	7860 { PREFIX_TABLE (PREFIX_VEX_0F3803) },

6643 { PREFIX_TABLE (PREFIX_VEX_3804) },	7861 { PREFIX_TABLE (PREFIX_VEX_0F3804) },

6644 { PREFIX_TABLE (PREFIX_VEX_3805) },	7862 { PREFIX_TABLE (PREFIX_VEX_0F3805) },

6645 { PREFIX_TABLE (PREFIX_VEX_3806) },	7863 { PREFIX_TABLE (PREFIX_VEX_0F3806) },

6646 { PREFIX_TABLE (PREFIX_VEX_3807) },	7864 { PREFIX_TABLE (PREFIX_VEX_0F3807) },

6647 /* 08 */	7865 /* 08 */

6648 { PREFIX_TABLE (PREFIX_VEX_3808) },	7866 { PREFIX_TABLE (PREFIX_VEX_0F3808) },

6649 { PREFIX_TABLE (PREFIX_VEX_3809) },	7867 { PREFIX_TABLE (PREFIX_VEX_0F3809) },

6650 { PREFIX_TABLE (PREFIX_VEX_380A) },	7868 { PREFIX_TABLE (PREFIX_VEX_0F380A) },

6651 { PREFIX_TABLE (PREFIX_VEX_380B) },	7869 { PREFIX_TABLE (PREFIX_VEX_0F380B) },

6652 { PREFIX_TABLE (PREFIX_VEX_380C) },	7870 { PREFIX_TABLE (PREFIX_VEX_0F380C) },

6653 { PREFIX_TABLE (PREFIX_VEX_380D) },	7871 { PREFIX_TABLE (PREFIX_VEX_0F380D) },

6654 { PREFIX_TABLE (PREFIX_VEX_380E) },	7872 { PREFIX_TABLE (PREFIX_VEX_0F380E) },

6655 { PREFIX_TABLE (PREFIX_VEX_380F) },	7873 { PREFIX_TABLE (PREFIX_VEX_0F380F) },

6656 /* 10 */	7874 /* 10 */

6657 { "(bad)",» » { XX } },	7875 { Bad_Opcode },

6658 { "(bad)",» » { XX } },	7876 { Bad_Opcode },

6659 { "(bad)",» » { XX } },	7877 { Bad_Opcode },

6660 { "(bad)",» » { XX } },	7878 { PREFIX_TABLE (PREFIX_VEX_0F3813) },

6661 { "(bad)",» » { XX } },	7879 { Bad_Opcode },

6662 { "(bad)",» » { XX } },	7880 { Bad_Opcode },

6663 { "(bad)",» » { XX } },	7881 { PREFIX_TABLE (PREFIX_VEX_0F3816) },

6664 { PREFIX_TABLE (PREFIX_VEX_3817) },	7882 { PREFIX_TABLE (PREFIX_VEX_0F3817) },

6665 /* 18 */	7883 /* 18 */

6666 { PREFIX_TABLE (PREFIX_VEX_3818) },	7884 { PREFIX_TABLE (PREFIX_VEX_0F3818) },

6667 { PREFIX_TABLE (PREFIX_VEX_3819) },	7885 { PREFIX_TABLE (PREFIX_VEX_0F3819) },

6668 { PREFIX_TABLE (PREFIX_VEX_381A) },	7886 { PREFIX_TABLE (PREFIX_VEX_0F381A) },

6669 { "(bad)",» » { XX } },	7887 { Bad_Opcode },

6670 { PREFIX_TABLE (PREFIX_VEX_381C) },	7888 { PREFIX_TABLE (PREFIX_VEX_0F381C) },

6671 { PREFIX_TABLE (PREFIX_VEX_381D) },	7889 { PREFIX_TABLE (PREFIX_VEX_0F381D) },

6672 { PREFIX_TABLE (PREFIX_VEX_381E) },	7890 { PREFIX_TABLE (PREFIX_VEX_0F381E) },

6673 { "(bad)",» » { XX } },	7891 { Bad_Opcode },

6674 /* 20 */	7892 /* 20 */

6675 { PREFIX_TABLE (PREFIX_VEX_3820) },	7893 { PREFIX_TABLE (PREFIX_VEX_0F3820) },

6676 { PREFIX_TABLE (PREFIX_VEX_3821) },	7894 { PREFIX_TABLE (PREFIX_VEX_0F3821) },

6677 { PREFIX_TABLE (PREFIX_VEX_3822) },	7895 { PREFIX_TABLE (PREFIX_VEX_0F3822) },

6678 { PREFIX_TABLE (PREFIX_VEX_3823) },	7896 { PREFIX_TABLE (PREFIX_VEX_0F3823) },

6679 { PREFIX_TABLE (PREFIX_VEX_3824) },	7897 { PREFIX_TABLE (PREFIX_VEX_0F3824) },

6680 { PREFIX_TABLE (PREFIX_VEX_3825) },	7898 { PREFIX_TABLE (PREFIX_VEX_0F3825) },

6681 { "(bad)",» » { XX } },	7899 { Bad_Opcode },

6682 { "(bad)",» » { XX } },	7900 { Bad_Opcode },

6683 /* 28 */	7901 /* 28 */

6684 { PREFIX_TABLE (PREFIX_VEX_3828) },	7902 { PREFIX_TABLE (PREFIX_VEX_0F3828) },

6685 { PREFIX_TABLE (PREFIX_VEX_3829) },	7903 { PREFIX_TABLE (PREFIX_VEX_0F3829) },

6686 { PREFIX_TABLE (PREFIX_VEX_382A) },	7904 { PREFIX_TABLE (PREFIX_VEX_0F382A) },

6687 { PREFIX_TABLE (PREFIX_VEX_382B) },	7905 { PREFIX_TABLE (PREFIX_VEX_0F382B) },

6688 { PREFIX_TABLE (PREFIX_VEX_382C) },	7906 { PREFIX_TABLE (PREFIX_VEX_0F382C) },

6689 { PREFIX_TABLE (PREFIX_VEX_382D) },	7907 { PREFIX_TABLE (PREFIX_VEX_0F382D) },

6690 { PREFIX_TABLE (PREFIX_VEX_382E) },	7908 { PREFIX_TABLE (PREFIX_VEX_0F382E) },

6691 { PREFIX_TABLE (PREFIX_VEX_382F) },	7909 { PREFIX_TABLE (PREFIX_VEX_0F382F) },

6692 /* 30 */	7910 /* 30 */

6693 { PREFIX_TABLE (PREFIX_VEX_3830) },	7911 { PREFIX_TABLE (PREFIX_VEX_0F3830) },

6694 { PREFIX_TABLE (PREFIX_VEX_3831) },	7912 { PREFIX_TABLE (PREFIX_VEX_0F3831) },

6695 { PREFIX_TABLE (PREFIX_VEX_3832) },	7913 { PREFIX_TABLE (PREFIX_VEX_0F3832) },

6696 { PREFIX_TABLE (PREFIX_VEX_3833) },	7914 { PREFIX_TABLE (PREFIX_VEX_0F3833) },

6697 { PREFIX_TABLE (PREFIX_VEX_3834) },	7915 { PREFIX_TABLE (PREFIX_VEX_0F3834) },

6698 { PREFIX_TABLE (PREFIX_VEX_3835) },	7916 { PREFIX_TABLE (PREFIX_VEX_0F3835) },

6699 { "(bad)",» » { XX } },	7917 { PREFIX_TABLE (PREFIX_VEX_0F3836) },

6700 { PREFIX_TABLE (PREFIX_VEX_3837) },	7918 { PREFIX_TABLE (PREFIX_VEX_0F3837) },

6701 /* 38 */	7919 /* 38 */

6702 { PREFIX_TABLE (PREFIX_VEX_3838) },	7920 { PREFIX_TABLE (PREFIX_VEX_0F3838) },

6703 { PREFIX_TABLE (PREFIX_VEX_3839) },	7921 { PREFIX_TABLE (PREFIX_VEX_0F3839) },

6704 { PREFIX_TABLE (PREFIX_VEX_383A) },	7922 { PREFIX_TABLE (PREFIX_VEX_0F383A) },

6705 { PREFIX_TABLE (PREFIX_VEX_383B) },	7923 { PREFIX_TABLE (PREFIX_VEX_0F383B) },

6706 { PREFIX_TABLE (PREFIX_VEX_383C) },	7924 { PREFIX_TABLE (PREFIX_VEX_0F383C) },

6707 { PREFIX_TABLE (PREFIX_VEX_383D) },	7925 { PREFIX_TABLE (PREFIX_VEX_0F383D) },

6708 { PREFIX_TABLE (PREFIX_VEX_383E) },	7926 { PREFIX_TABLE (PREFIX_VEX_0F383E) },

6709 { PREFIX_TABLE (PREFIX_VEX_383F) },	7927 { PREFIX_TABLE (PREFIX_VEX_0F383F) },

6710 /* 40 */	7928 /* 40 */

6711 { PREFIX_TABLE (PREFIX_VEX_3840) },	7929 { PREFIX_TABLE (PREFIX_VEX_0F3840) },

6712 { PREFIX_TABLE (PREFIX_VEX_3841) },	7930 { PREFIX_TABLE (PREFIX_VEX_0F3841) },

6713 { "(bad)",» » { XX } },	7931 { Bad_Opcode },

6714 { "(bad)",» » { XX } },	7932 { Bad_Opcode },

6715 { "(bad)",» » { XX } },	7933 { Bad_Opcode },

6716 { "(bad)",» » { XX } },	7934 { PREFIX_TABLE (PREFIX_VEX_0F3845) },

6717 { "(bad)",» » { XX } },	7935 { PREFIX_TABLE (PREFIX_VEX_0F3846) },

6718 { "(bad)",» » { XX } },	7936 { PREFIX_TABLE (PREFIX_VEX_0F3847) },

6719 /* 48 */	7937 /* 48 */

6720 { "(bad)",» » { XX } },	7938 { Bad_Opcode },

6721 { "(bad)",» » { XX } },	7939 { Bad_Opcode },

6722 { "(bad)",» » { XX } },	7940 { Bad_Opcode },

6723 { "(bad)",» » { XX } },	7941 { Bad_Opcode },

6724 { "(bad)",» » { XX } },	7942 { Bad_Opcode },

6725 { "(bad)",» » { XX } },	7943 { Bad_Opcode },

6726 { "(bad)",» » { XX } },	7944 { Bad_Opcode },

6727 { "(bad)",» » { XX } },	7945 { Bad_Opcode },

6728 /* 50 */	7946 /* 50 */

6729 { "(bad)",» » { XX } },	7947 { Bad_Opcode },

6730 { "(bad)",» » { XX } },	7948 { Bad_Opcode },

6731 { "(bad)",» » { XX } },	7949 { Bad_Opcode },

6732 { "(bad)",» » { XX } },	7950 { Bad_Opcode },

6733 { "(bad)",» » { XX } },	7951 { Bad_Opcode },

6734 { "(bad)",» » { XX } },	7952 { Bad_Opcode },

6735 { "(bad)",» » { XX } },	7953 { Bad_Opcode },

6736 { "(bad)",» » { XX } },	7954 { Bad_Opcode },

6737 /* 58 */	7955 /* 58 */

6738 { "(bad)",» » { XX } },	7956 { PREFIX_TABLE (PREFIX_VEX_0F3858) },

6739 { "(bad)",» » { XX } },	7957 { PREFIX_TABLE (PREFIX_VEX_0F3859) },

6740 { "(bad)",» » { XX } },	7958 { PREFIX_TABLE (PREFIX_VEX_0F385A) },

6741 { "(bad)",» » { XX } },	7959 { Bad_Opcode },

6742 { "(bad)",» » { XX } },	7960 { Bad_Opcode },

6743 { "(bad)",» » { XX } },	7961 { Bad_Opcode },

6744 { "(bad)",» » { XX } },	7962 { Bad_Opcode },

6745 { "(bad)",» » { XX } },	7963 { Bad_Opcode },

6746 /* 60 */	7964 /* 60 */

6747 { "(bad)",» » { XX } },	7965 { Bad_Opcode },

6748 { "(bad)",» » { XX } },	7966 { Bad_Opcode },

6749 { "(bad)",» » { XX } },	7967 { Bad_Opcode },

6750 { "(bad)",» » { XX } },	7968 { Bad_Opcode },

6751 { "(bad)",» » { XX } },	7969 { Bad_Opcode },

6752 { "(bad)",» » { XX } },	7970 { Bad_Opcode },

6753 { "(bad)",» » { XX } },	7971 { Bad_Opcode },

6754 { "(bad)",» » { XX } },	7972 { Bad_Opcode },

6755 /* 68 */	7973 /* 68 */

6756 { "(bad)",» » { XX } },	7974 { Bad_Opcode },

6757 { "(bad)",» » { XX } },	7975 { Bad_Opcode },

6758 { "(bad)",» » { XX } },	7976 { Bad_Opcode },

6759 { "(bad)",» » { XX } },	7977 { Bad_Opcode },

6760 { "(bad)",» » { XX } },	7978 { Bad_Opcode },

6761 { "(bad)",» » { XX } },	7979 { Bad_Opcode },

6762 { "(bad)",» » { XX } },	7980 { Bad_Opcode },

6763 { "(bad)",» » { XX } },	7981 { Bad_Opcode },

6764 /* 70 */	7982 /* 70 */

6765 { "(bad)",» » { XX } },	7983 { Bad_Opcode },

6766 { "(bad)",» » { XX } },	7984 { Bad_Opcode },

6767 { "(bad)",» » { XX } },	7985 { Bad_Opcode },

6768 { "(bad)",» » { XX } },	7986 { Bad_Opcode },

6769 { "(bad)",» » { XX } },	7987 { Bad_Opcode },

6770 { "(bad)",» » { XX } },	7988 { Bad_Opcode },

6771 { "(bad)",» » { XX } },	7989 { Bad_Opcode },

6772 { "(bad)",» » { XX } },	7990 { Bad_Opcode },

6773 /* 78 */	7991 /* 78 */

6774 { "(bad)",» » { XX } },	7992 { PREFIX_TABLE (PREFIX_VEX_0F3878) },

6775 { "(bad)",» » { XX } },	7993 { PREFIX_TABLE (PREFIX_VEX_0F3879) },

6776 { "(bad)",» » { XX } },	7994 { Bad_Opcode },

6777 { "(bad)",» » { XX } },	7995 { Bad_Opcode },

6778 { "(bad)",» » { XX } },	7996 { Bad_Opcode },

6779 { "(bad)",» » { XX } },	7997 { Bad_Opcode },

6780 { "(bad)",» » { XX } },	7998 { Bad_Opcode },

6781 { "(bad)",» » { XX } },	7999 { Bad_Opcode },

6782 /* 80 */	8000 /* 80 */

6783 { "(bad)",» » { XX } },	8001 { Bad_Opcode },

6784 { "(bad)",» » { XX } },	8002 { Bad_Opcode },

6785 { "(bad)",» » { XX } },	8003 { Bad_Opcode },

6786 { "(bad)",» » { XX } },	8004 { Bad_Opcode },

6787 { "(bad)",» » { XX } },	8005 { Bad_Opcode },

6788 { "(bad)",» » { XX } },	8006 { Bad_Opcode },

6789 { "(bad)",» » { XX } },	8007 { Bad_Opcode },

6790 { "(bad)",» » { XX } },	8008 { Bad_Opcode },

6791 /* 88 */	8009 /* 88 */

6792 { "(bad)",» » { XX } },	8010 { Bad_Opcode },

6793 { "(bad)",» » { XX } },	8011 { Bad_Opcode },

6794 { "(bad)",» » { XX } },	8012 { Bad_Opcode },

6795 { "(bad)",» » { XX } },	8013 { Bad_Opcode },

6796 { "(bad)",» » { XX } },	8014 { PREFIX_TABLE (PREFIX_VEX_0F388C) },

6797 { "(bad)",» » { XX } },	8015 { Bad_Opcode },

6798 { "(bad)",» » { XX } },	8016 { PREFIX_TABLE (PREFIX_VEX_0F388E) },

6799 { "(bad)",» » { XX } },	8017 { Bad_Opcode },

6800 /* 90 */	8018 /* 90 */

6801 { "(bad)",» » { XX } },	8019 { PREFIX_TABLE (PREFIX_VEX_0F3890) },

6802 { "(bad)",» » { XX } },	8020 { PREFIX_TABLE (PREFIX_VEX_0F3891) },

6803 { "(bad)",» » { XX } },	8021 { PREFIX_TABLE (PREFIX_VEX_0F3892) },

6804 { "(bad)",» » { XX } },	8022 { PREFIX_TABLE (PREFIX_VEX_0F3893) },

6805 { "(bad)",» » { XX } },	8023 { Bad_Opcode },

6806 { "(bad)",» » { XX } },	8024 { Bad_Opcode },

6807 { PREFIX_TABLE (PREFIX_VEX_3896) },	8025 { PREFIX_TABLE (PREFIX_VEX_0F3896) },

6808 { PREFIX_TABLE (PREFIX_VEX_3897) },	8026 { PREFIX_TABLE (PREFIX_VEX_0F3897) },

6809 /* 98 */	8027 /* 98 */

6810 { PREFIX_TABLE (PREFIX_VEX_3898) },	8028 { PREFIX_TABLE (PREFIX_VEX_0F3898) },

6811 { PREFIX_TABLE (PREFIX_VEX_3899) },	8029 { PREFIX_TABLE (PREFIX_VEX_0F3899) },

6812 { PREFIX_TABLE (PREFIX_VEX_389A) },	8030 { PREFIX_TABLE (PREFIX_VEX_0F389A) },

6813 { PREFIX_TABLE (PREFIX_VEX_389B) },	8031 { PREFIX_TABLE (PREFIX_VEX_0F389B) },

6814 { PREFIX_TABLE (PREFIX_VEX_389C) },	8032 { PREFIX_TABLE (PREFIX_VEX_0F389C) },

6815 { PREFIX_TABLE (PREFIX_VEX_389D) },	8033 { PREFIX_TABLE (PREFIX_VEX_0F389D) },

6816 { PREFIX_TABLE (PREFIX_VEX_389E) },	8034 { PREFIX_TABLE (PREFIX_VEX_0F389E) },

6817 { PREFIX_TABLE (PREFIX_VEX_389F) },	8035 { PREFIX_TABLE (PREFIX_VEX_0F389F) },

6818 /* a0 */	8036 /* a0 */

6819 { "(bad)",» » { XX } },	8037 { Bad_Opcode },

6820 { "(bad)",» » { XX } },	8038 { Bad_Opcode },

6821 { "(bad)",» » { XX } },	8039 { Bad_Opcode },

6822 { "(bad)",» » { XX } },	8040 { Bad_Opcode },

6823 { "(bad)",» » { XX } },	8041 { Bad_Opcode },

6824 { "(bad)",» » { XX } },	8042 { Bad_Opcode },

6825 { PREFIX_TABLE (PREFIX_VEX_38A6) },	8043 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },

6826 { PREFIX_TABLE (PREFIX_VEX_38A7) },	8044 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },

6827 /* a8 */	8045 /* a8 */

6828 { PREFIX_TABLE (PREFIX_VEX_38A8) },	8046 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },

6829 { PREFIX_TABLE (PREFIX_VEX_38A9) },	8047 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },

6830 { PREFIX_TABLE (PREFIX_VEX_38AA) },	8048 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },

6831 { PREFIX_TABLE (PREFIX_VEX_38AB) },	8049 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },

6832 { PREFIX_TABLE (PREFIX_VEX_38AC) },	8050 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },

6833 { PREFIX_TABLE (PREFIX_VEX_38AD) },	8051 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },

6834 { PREFIX_TABLE (PREFIX_VEX_38AE) },	8052 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },

6835 { PREFIX_TABLE (PREFIX_VEX_38AF) },	8053 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },

6836 /* b0 */	8054 /* b0 */

6837 { "(bad)",» » { XX } },	8055 { Bad_Opcode },

6838 { "(bad)",» » { XX } },	8056 { Bad_Opcode },

6839 { "(bad)",» » { XX } },	8057 { Bad_Opcode },

6840 { "(bad)",» » { XX } },	8058 { Bad_Opcode },

6841 { "(bad)",» » { XX } },	8059 { Bad_Opcode },

6842 { "(bad)",» » { XX } },	8060 { Bad_Opcode },

6843 { PREFIX_TABLE (PREFIX_VEX_38B6) },	8061 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },

6844 { PREFIX_TABLE (PREFIX_VEX_38B7) },	8062 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },

6845 /* b8 */	8063 /* b8 */

6846 { PREFIX_TABLE (PREFIX_VEX_38B8) },	8064 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },

6847 { PREFIX_TABLE (PREFIX_VEX_38B9) },	8065 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },

6848 { PREFIX_TABLE (PREFIX_VEX_38BA) },	8066 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },

6849 { PREFIX_TABLE (PREFIX_VEX_38BB) },	8067 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },

6850 { PREFIX_TABLE (PREFIX_VEX_38BC) },	8068 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },

6851 { PREFIX_TABLE (PREFIX_VEX_38BD) },	8069 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },

6852 { PREFIX_TABLE (PREFIX_VEX_38BE) },	8070 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },

6853 { PREFIX_TABLE (PREFIX_VEX_38BF) },	8071 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },

6854 /* c0 */	8072 /* c0 */

6855 { "(bad)",» » { XX } },	8073 { Bad_Opcode },

6856 { "(bad)",» » { XX } },	8074 { Bad_Opcode },

6857 { "(bad)",» » { XX } },	8075 { Bad_Opcode },

6858 { "(bad)",» » { XX } },	8076 { Bad_Opcode },

6859 { "(bad)",» » { XX } },	8077 { Bad_Opcode },

6860 { "(bad)",» » { XX } },	8078 { Bad_Opcode },

6861 { "(bad)",» » { XX } },	8079 { Bad_Opcode },

6862 { "(bad)",» » { XX } },	8080 { Bad_Opcode },

6863 /* c8 */	8081 /* c8 */

6864 { "(bad)",» » { XX } },	8082 { Bad_Opcode },

6865 { "(bad)",» » { XX } },	8083 { Bad_Opcode },

6866 { "(bad)",» » { XX } },	8084 { Bad_Opcode },

6867 { "(bad)",» » { XX } },	8085 { Bad_Opcode },

6868 { "(bad)",» » { XX } },	8086 { Bad_Opcode },

6869 { "(bad)",» » { XX } },	8087 { Bad_Opcode },

6870 { "(bad)",» » { XX } },	8088 { Bad_Opcode },

6871 { "(bad)",» » { XX } },	8089 { Bad_Opcode },

6872 /* d0 */	8090 /* d0 */

6873 { "(bad)",» » { XX } },	8091 { Bad_Opcode },

6874 { "(bad)",» » { XX } },	8092 { Bad_Opcode },

6875 { "(bad)",» » { XX } },	8093 { Bad_Opcode },

6876 { "(bad)",» » { XX } },	8094 { Bad_Opcode },

6877 { "(bad)",» » { XX } },	8095 { Bad_Opcode },

6878 { "(bad)",» » { XX } },	8096 { Bad_Opcode },

6879 { "(bad)",» » { XX } },	8097 { Bad_Opcode },

6880 { "(bad)",» » { XX } },	8098 { Bad_Opcode },

6881 /* d8 */	8099 /* d8 */

6882 { "(bad)",» » { XX } },	8100 { Bad_Opcode },

6883 { "(bad)",» » { XX } },	8101 { Bad_Opcode },

6884 { "(bad)",» » { XX } },	8102 { Bad_Opcode },

6885 { PREFIX_TABLE (PREFIX_VEX_38DB) },	8103 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },

6886 { PREFIX_TABLE (PREFIX_VEX_38DC) },	8104 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },

6887 { PREFIX_TABLE (PREFIX_VEX_38DD) },	8105 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },

6888 { PREFIX_TABLE (PREFIX_VEX_38DE) },	8106 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },

6889 { PREFIX_TABLE (PREFIX_VEX_38DF) },	8107 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },

6890 /* e0 */	8108 /* e0 */

6891 { "(bad)",» » { XX } },	8109 { Bad_Opcode },

6892 { "(bad)",» » { XX } },	8110 { Bad_Opcode },

6893 { "(bad)",» » { XX } },	8111 { Bad_Opcode },

6894 { "(bad)",» » { XX } },	8112 { Bad_Opcode },

6895 { "(bad)",» » { XX } },	8113 { Bad_Opcode },

6896 { "(bad)",» » { XX } },	8114 { Bad_Opcode },

6897 { "(bad)",» » { XX } },	8115 { Bad_Opcode },

6898 { "(bad)",» » { XX } },	8116 { Bad_Opcode },

6899 /* e8 */	8117 /* e8 */

6900 { "(bad)",» » { XX } },	8118 { Bad_Opcode },

6901 { "(bad)",» » { XX } },	8119 { Bad_Opcode },

6902 { "(bad)",» » { XX } },	8120 { Bad_Opcode },

6903 { "(bad)",» » { XX } },	8121 { Bad_Opcode },

6904 { "(bad)",» » { XX } },	8122 { Bad_Opcode },

6905 { "(bad)",» » { XX } },	8123 { Bad_Opcode },

6906 { "(bad)",» » { XX } },	8124 { Bad_Opcode },

6907 { "(bad)",» » { XX } },	8125 { Bad_Opcode },

6908 /* f0 */	8126 /* f0 */

6909 { "(bad)",» » { XX } },	8127 { Bad_Opcode },

6910 { "(bad)",» » { XX } },	8128 { Bad_Opcode },

6911 { "(bad)",» » { XX } },	8129 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },

6912 { "(bad)",» » { XX } },	8130 { REG_TABLE (REG_VEX_0F38F3) },

6913 { "(bad)",» » { XX } },	8131 { Bad_Opcode },

6914 { "(bad)",» » { XX } },	8132 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },

6915 { "(bad)",» » { XX } },	8133 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },

6916 { "(bad)",» » { XX } },	8134 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },

6917 /* f8 */	8135 /* f8 */

6918 { "(bad)",» » { XX } },	8136 { Bad_Opcode },

6919 { "(bad)",» » { XX } },	8137 { Bad_Opcode },

6920 { "(bad)",» » { XX } },	8138 { Bad_Opcode },

6921 { "(bad)",» » { XX } },	8139 { Bad_Opcode },

6922 { "(bad)",» » { XX } },	8140 { Bad_Opcode },

6923 { "(bad)",» » { XX } },	8141 { Bad_Opcode },

6924 { "(bad)",» » { XX } },	8142 { Bad_Opcode },

6925 { "(bad)",» » { XX } },	8143 { Bad_Opcode },

6926 },	8144 },

6927 /* VEX_0F3A */	8145 /* VEX_0F3A */

6928 {	8146 {

6929 /* 00 */	8147 /* 00 */

6930 { "(bad)",» » { XX } },	8148 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },

6931 { "(bad)",» » { XX } },	8149 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },

6932 { "(bad)",» » { XX } },	8150 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },

6933 { "(bad)",» » { XX } },	8151 { Bad_Opcode },

6934 { PREFIX_TABLE (PREFIX_VEX_3A04) },	8152 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },

6935 { PREFIX_TABLE (PREFIX_VEX_3A05) },	8153 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },

6936 { PREFIX_TABLE (PREFIX_VEX_3A06) },	8154 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },

6937 { "(bad)",» » { XX } },	8155 { Bad_Opcode },

6938 /* 08 */	8156 /* 08 */

6939 { PREFIX_TABLE (PREFIX_VEX_3A08) },	8157 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },

6940 { PREFIX_TABLE (PREFIX_VEX_3A09) },	8158 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },

6941 { PREFIX_TABLE (PREFIX_VEX_3A0A) },	8159 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },

6942 { PREFIX_TABLE (PREFIX_VEX_3A0B) },	8160 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },

6943 { PREFIX_TABLE (PREFIX_VEX_3A0C) },	8161 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },

6944 { PREFIX_TABLE (PREFIX_VEX_3A0D) },	8162 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },

6945 { PREFIX_TABLE (PREFIX_VEX_3A0E) },	8163 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },

6946 { PREFIX_TABLE (PREFIX_VEX_3A0F) },	8164 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },

6947 /* 10 */	8165 /* 10 */

6948 { "(bad)",» » { XX } },	8166 { Bad_Opcode },

6949 { "(bad)",» » { XX } },	8167 { Bad_Opcode },

6950 { "(bad)",» » { XX } },	8168 { Bad_Opcode },

6951 { "(bad)",» » { XX } },	8169 { Bad_Opcode },

6952 { PREFIX_TABLE (PREFIX_VEX_3A14) },	8170 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },

6953 { PREFIX_TABLE (PREFIX_VEX_3A15) },	8171 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },

6954 { PREFIX_TABLE (PREFIX_VEX_3A16) },	8172 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },

6955 { PREFIX_TABLE (PREFIX_VEX_3A17) },	8173 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },

6956 /* 18 */	8174 /* 18 */

6957 { PREFIX_TABLE (PREFIX_VEX_3A18) },	8175 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },

6958 { PREFIX_TABLE (PREFIX_VEX_3A19) },	8176 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },

6959 { "(bad)",» » { XX } },	8177 { Bad_Opcode },

6960 { "(bad)",» » { XX } },	8178 { Bad_Opcode },

6961 { "(bad)",» » { XX } },	8179 { Bad_Opcode },

6962 { "(bad)",» » { XX } },	8180 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },

6963 { "(bad)",» » { XX } },	8181 { Bad_Opcode },

6964 { "(bad)",» » { XX } },	8182 { Bad_Opcode },

6965 /* 20 */	8183 /* 20 */

6966 { PREFIX_TABLE (PREFIX_VEX_3A20) },	8184 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },

6967 { PREFIX_TABLE (PREFIX_VEX_3A21) },	8185 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },

6968 { PREFIX_TABLE (PREFIX_VEX_3A22) },	8186 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },

6969 { "(bad)",» » { XX } },	8187 { Bad_Opcode },

6970 { "(bad)",» » { XX } },	8188 { Bad_Opcode },

6971 { "(bad)",» » { XX } },	8189 { Bad_Opcode },

6972 { "(bad)",» » { XX } },	8190 { Bad_Opcode },

6973 { "(bad)",» » { XX } },	8191 { Bad_Opcode },

6974 /* 28 */	8192 /* 28 */

6975 { "(bad)",» » { XX } },	8193 { Bad_Opcode },

6976 { "(bad)",» » { XX } },	8194 { Bad_Opcode },

6977 { "(bad)",» » { XX } },	8195 { Bad_Opcode },

6978 { "(bad)",» » { XX } },	8196 { Bad_Opcode },

6979 { "(bad)",» » { XX } },	8197 { Bad_Opcode },

6980 { "(bad)",» » { XX } },	8198 { Bad_Opcode },

6981 { "(bad)",» » { XX } },	8199 { Bad_Opcode },

6982 { "(bad)",» » { XX } },	8200 { Bad_Opcode },

6983 /* 30 */	8201 /* 30 */

6984 { "(bad)",» » { XX } },	8202 { Bad_Opcode },

6985 { "(bad)",» » { XX } },	8203 { Bad_Opcode },

6986 { "(bad)",» » { XX } },	8204 { Bad_Opcode },

6987 { "(bad)",» » { XX } },	8205 { Bad_Opcode },

6988 { "(bad)",» » { XX } },	8206 { Bad_Opcode },

6989 { "(bad)",» » { XX } },	8207 { Bad_Opcode },

6990 { "(bad)",» » { XX } },	8208 { Bad_Opcode },

6991 { "(bad)",» » { XX } },	8209 { Bad_Opcode },

6992 /* 38 */	8210 /* 38 */

6993 { "(bad)",» » { XX } },	8211 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },

6994 { "(bad)",» » { XX } },	8212 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },

6995 { "(bad)",» » { XX } },	8213 { Bad_Opcode },

6996 { "(bad)",» » { XX } },	8214 { Bad_Opcode },

6997 { "(bad)",» » { XX } },	8215 { Bad_Opcode },

6998 { "(bad)",» » { XX } },	8216 { Bad_Opcode },

6999 { "(bad)",» » { XX } },	8217 { Bad_Opcode },

7000 { "(bad)",» » { XX } },	8218 { Bad_Opcode },

7001 /* 40 */	8219 /* 40 */

7002 { PREFIX_TABLE (PREFIX_VEX_3A40) },	8220 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },

7003 { PREFIX_TABLE (PREFIX_VEX_3A41) },	8221 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },

7004 { PREFIX_TABLE (PREFIX_VEX_3A42) },	8222 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },

7005 { "(bad)",» » { XX } },	8223 { Bad_Opcode },

7006 { PREFIX_TABLE (PREFIX_VEX_3A44) },	8224 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },

7007 { "(bad)",» » { XX } },	8225 { Bad_Opcode },

7008 { "(bad)",» » { XX } },	8226 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },

7009 { "(bad)",» » { XX } },	8227 { Bad_Opcode },

7010 /* 48 */	8228 /* 48 */

7011 { "(bad)",» » { XX } },	8229 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },

7012 { "(bad)",» » { XX } },	8230 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },

7013 { PREFIX_TABLE (PREFIX_VEX_3A4A) },	8231 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },

7014 { PREFIX_TABLE (PREFIX_VEX_3A4B) },	8232 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },

7015 { PREFIX_TABLE (PREFIX_VEX_3A4C) },	8233 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },

7016 { "(bad)",» » { XX } },	8234 { Bad_Opcode },

7017 { "(bad)",» » { XX } },	8235 { Bad_Opcode },

7018 { "(bad)",» » { XX } },	8236 { Bad_Opcode },

7019 /* 50 */	8237 /* 50 */

7020 { "(bad)",» » { XX } },	8238 { Bad_Opcode },

7021 { "(bad)",» » { XX } },	8239 { Bad_Opcode },

7022 { "(bad)",» » { XX } },	8240 { Bad_Opcode },

7023 { "(bad)",» » { XX } },	8241 { Bad_Opcode },

7024 { "(bad)",» » { XX } },	8242 { Bad_Opcode },

7025 { "(bad)",» » { XX } },	8243 { Bad_Opcode },

7026 { "(bad)",» » { XX } },	8244 { Bad_Opcode },

7027 { "(bad)",» » { XX } },	8245 { Bad_Opcode },

7028 /* 58 */	8246 /* 58 */

7029 { "(bad)",» » { XX } },	8247 { Bad_Opcode },

7030 { "(bad)",» » { XX } },	8248 { Bad_Opcode },

7031 { "(bad)",» » { XX } },	8249 { Bad_Opcode },

7032 { "(bad)",» » { XX } },	8250 { Bad_Opcode },

7033 { PREFIX_TABLE (PREFIX_VEX_3A5C) },	8251 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },

7034 { PREFIX_TABLE (PREFIX_VEX_3A5D) },	8252 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },

7035 { PREFIX_TABLE (PREFIX_VEX_3A5E) },	8253 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },

7036 { PREFIX_TABLE (PREFIX_VEX_3A5F) },	8254 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },

7037 /* 60 */	8255 /* 60 */

7038 { PREFIX_TABLE (PREFIX_VEX_3A60) },	8256 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },

7039 { PREFIX_TABLE (PREFIX_VEX_3A61) },	8257 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },

7040 { PREFIX_TABLE (PREFIX_VEX_3A62) },	8258 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },

7041 { PREFIX_TABLE (PREFIX_VEX_3A63) },	8259 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },

7042 { "(bad)",» » { XX } },	8260 { Bad_Opcode },

7043 { "(bad)",» » { XX } },	8261 { Bad_Opcode },

7044 { "(bad)",» » { XX } },	8262 { Bad_Opcode },

7045 { "(bad)",» » { XX } },	8263 { Bad_Opcode },

7046 /* 68 */	8264 /* 68 */

7047 { PREFIX_TABLE (PREFIX_VEX_3A68) },	8265 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },

7048 { PREFIX_TABLE (PREFIX_VEX_3A69) },	8266 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },

7049 { PREFIX_TABLE (PREFIX_VEX_3A6A) },	8267 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },

7050 { PREFIX_TABLE (PREFIX_VEX_3A6B) },	8268 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },

7051 { PREFIX_TABLE (PREFIX_VEX_3A6C) },	8269 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },

7052 { PREFIX_TABLE (PREFIX_VEX_3A6D) },	8270 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },

7053 { PREFIX_TABLE (PREFIX_VEX_3A6E) },	8271 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },

7054 { PREFIX_TABLE (PREFIX_VEX_3A6F) },	8272 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },

7055 /* 70 */	8273 /* 70 */

7056 { "(bad)",» » { XX } },	8274 { Bad_Opcode },

7057 { "(bad)",» » { XX } },	8275 { Bad_Opcode },

7058 { "(bad)",» » { XX } },	8276 { Bad_Opcode },

7059 { "(bad)",» » { XX } },	8277 { Bad_Opcode },

7060 { "(bad)",» » { XX } },	8278 { Bad_Opcode },

7061 { "(bad)",» » { XX } },	8279 { Bad_Opcode },

7062 { "(bad)",» » { XX } },	8280 { Bad_Opcode },

7063 { "(bad)",» » { XX } },	8281 { Bad_Opcode },

7064 /* 78 */	8282 /* 78 */

7065 { PREFIX_TABLE (PREFIX_VEX_3A78) },	8283 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },

7066 { PREFIX_TABLE (PREFIX_VEX_3A79) },	8284 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },

7067 { PREFIX_TABLE (PREFIX_VEX_3A7A) },	8285 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },

7068 { PREFIX_TABLE (PREFIX_VEX_3A7B) },	8286 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },

7069 { PREFIX_TABLE (PREFIX_VEX_3A7C) },	8287 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },

7070 { PREFIX_TABLE (PREFIX_VEX_3A7D) },	8288 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },

7071 { PREFIX_TABLE (PREFIX_VEX_3A7E) },	8289 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },

7072 { PREFIX_TABLE (PREFIX_VEX_3A7F) },	8290 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },

7073 /* 80 */	8291 /* 80 */

7074 { "(bad)",» » { XX } },	8292 { Bad_Opcode },

7075 { "(bad)",» » { XX } },	8293 { Bad_Opcode },

7076 { "(bad)",» » { XX } },	8294 { Bad_Opcode },

7077 { "(bad)",» » { XX } },	8295 { Bad_Opcode },

7078 { "(bad)",» » { XX } },	8296 { Bad_Opcode },

7079 { "(bad)",» » { XX } },	8297 { Bad_Opcode },

7080 { "(bad)",» » { XX } },	8298 { Bad_Opcode },

7081 { "(bad)",» » { XX } },	8299 { Bad_Opcode },

7082 /* 88 */	8300 /* 88 */

7083 { "(bad)",» » { XX } },	8301 { Bad_Opcode },

7084 { "(bad)",» » { XX } },	8302 { Bad_Opcode },

7085 { "(bad)",» » { XX } },	8303 { Bad_Opcode },

7086 { "(bad)",» » { XX } },	8304 { Bad_Opcode },

7087 { "(bad)",» » { XX } },	8305 { Bad_Opcode },

7088 { "(bad)",» » { XX } },	8306 { Bad_Opcode },

7089 { "(bad)",» » { XX } },	8307 { Bad_Opcode },

7090 { "(bad)",» » { XX } },	8308 { Bad_Opcode },

7091 /* 90 */	8309 /* 90 */

7092 { "(bad)",» » { XX } },	8310 { Bad_Opcode },

7093 { "(bad)",» » { XX } },	8311 { Bad_Opcode },

7094 { "(bad)",» » { XX } },	8312 { Bad_Opcode },

7095 { "(bad)",» » { XX } },	8313 { Bad_Opcode },

7096 { "(bad)",» » { XX } },	8314 { Bad_Opcode },

7097 { "(bad)",» » { XX } },	8315 { Bad_Opcode },

7098 { "(bad)",» » { XX } },	8316 { Bad_Opcode },

7099 { "(bad)",» » { XX } },	8317 { Bad_Opcode },

7100 /* 98 */	8318 /* 98 */

7101 { "(bad)",» » { XX } },	8319 { Bad_Opcode },

7102 { "(bad)",» » { XX } },	8320 { Bad_Opcode },

7103 { "(bad)",» » { XX } },	8321 { Bad_Opcode },

7104 { "(bad)",» » { XX } },	8322 { Bad_Opcode },

7105 { "(bad)",» » { XX } },	8323 { Bad_Opcode },

7106 { "(bad)",» » { XX } },	8324 { Bad_Opcode },

7107 { "(bad)",» » { XX } },	8325 { Bad_Opcode },

7108 { "(bad)",» » { XX } },	8326 { Bad_Opcode },

7109 /* a0 */	8327 /* a0 */

7110 { "(bad)",» » { XX } },	8328 { Bad_Opcode },

7111 { "(bad)",» » { XX } },	8329 { Bad_Opcode },

7112 { "(bad)",» » { XX } },	8330 { Bad_Opcode },

7113 { "(bad)",» » { XX } },	8331 { Bad_Opcode },

7114 { "(bad)",» » { XX } },	8332 { Bad_Opcode },

7115 { "(bad)",» » { XX } },	8333 { Bad_Opcode },

7116 { "(bad)",» » { XX } },	8334 { Bad_Opcode },

7117 { "(bad)",» » { XX } },	8335 { Bad_Opcode },

7118 /* a8 */	8336 /* a8 */

7119 { "(bad)",» » { XX } },	8337 { Bad_Opcode },

7120 { "(bad)",» » { XX } },	8338 { Bad_Opcode },

7121 { "(bad)",» » { XX } },	8339 { Bad_Opcode },

7122 { "(bad)",» » { XX } },	8340 { Bad_Opcode },

7123 { "(bad)",» » { XX } },	8341 { Bad_Opcode },

7124 { "(bad)",» » { XX } },	8342 { Bad_Opcode },

7125 { "(bad)",» » { XX } },	8343 { Bad_Opcode },

7126 { "(bad)",» » { XX } },	8344 { Bad_Opcode },

7127 /* b0 */	8345 /* b0 */

7128 { "(bad)",» » { XX } },	8346 { Bad_Opcode },

7129 { "(bad)",» » { XX } },	8347 { Bad_Opcode },

7130 { "(bad)",» » { XX } },	8348 { Bad_Opcode },

7131 { "(bad)",» » { XX } },	8349 { Bad_Opcode },

7132 { "(bad)",» » { XX } },	8350 { Bad_Opcode },

7133 { "(bad)",» » { XX } },	8351 { Bad_Opcode },

7134 { "(bad)",» » { XX } },	8352 { Bad_Opcode },

7135 { "(bad)",» » { XX } },	8353 { Bad_Opcode },

7136 /* b8 */	8354 /* b8 */

7137 { "(bad)",» » { XX } },	8355 { Bad_Opcode },

7138 { "(bad)",» » { XX } },	8356 { Bad_Opcode },

7139 { "(bad)",» » { XX } },	8357 { Bad_Opcode },

7140 { "(bad)",» » { XX } },	8358 { Bad_Opcode },

7141 { "(bad)",» » { XX } },	8359 { Bad_Opcode },

7142 { "(bad)",» » { XX } },	8360 { Bad_Opcode },

7143 { "(bad)",» » { XX } },	8361 { Bad_Opcode },

7144 { "(bad)",» » { XX } },	8362 { Bad_Opcode },

7145 /* c0 */	8363 /* c0 */

7146 { "(bad)",» » { XX } },	8364 { Bad_Opcode },

7147 { "(bad)",» » { XX } },	8365 { Bad_Opcode },

7148 { "(bad)",» » { XX } },	8366 { Bad_Opcode },

7149 { "(bad)",» » { XX } },	8367 { Bad_Opcode },

7150 { "(bad)",» » { XX } },	8368 { Bad_Opcode },

7151 { "(bad)",» » { XX } },	8369 { Bad_Opcode },

7152 { "(bad)",» » { XX } },	8370 { Bad_Opcode },

7153 { "(bad)",» » { XX } },	8371 { Bad_Opcode },

7154 /* c8 */	8372 /* c8 */

7155 { "(bad)",» » { XX } },	8373 { Bad_Opcode },

7156 { "(bad)",» » { XX } },	8374 { Bad_Opcode },

7157 { "(bad)",» » { XX } },	8375 { Bad_Opcode },

7158 { "(bad)",» » { XX } },	8376 { Bad_Opcode },

7159 { "(bad)",» » { XX } },	8377 { Bad_Opcode },

7160 { "(bad)",» » { XX } },	8378 { Bad_Opcode },

7161 { "(bad)",» » { XX } },	8379 { Bad_Opcode },

7162 { "(bad)",» » { XX } },	8380 { Bad_Opcode },

7163 /* d0 */	8381 /* d0 */

7164 { "(bad)",» » { XX } },	8382 { Bad_Opcode },

7165 { "(bad)",» » { XX } },	8383 { Bad_Opcode },

7166 { "(bad)",» » { XX } },	8384 { Bad_Opcode },

7167 { "(bad)",» » { XX } },	8385 { Bad_Opcode },

7168 { "(bad)",» » { XX } },	8386 { Bad_Opcode },

7169 { "(bad)",» » { XX } },	8387 { Bad_Opcode },

7170 { "(bad)",» » { XX } },	8388 { Bad_Opcode },

7171 { "(bad)",» » { XX } },	8389 { Bad_Opcode },

7172 /* d8 */	8390 /* d8 */

7173 { "(bad)",» » { XX } },	8391 { Bad_Opcode },

7174 { "(bad)",» » { XX } },	8392 { Bad_Opcode },

7175 { "(bad)",» » { XX } },	8393 { Bad_Opcode },

7176 { "(bad)",» » { XX } },	8394 { Bad_Opcode },

7177 { "(bad)",» » { XX } },	8395 { Bad_Opcode },

7178 { "(bad)",» » { XX } },	8396 { Bad_Opcode },

7179 { "(bad)",» » { XX } },	8397 { Bad_Opcode },

7180 { PREFIX_TABLE (PREFIX_VEX_3ADF) },	8398 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },

7181 /* e0 */	8399 /* e0 */

7182 { "(bad)",» » { XX } },	8400 { Bad_Opcode },

7183 { "(bad)",» » { XX } },	8401 { Bad_Opcode },

7184 { "(bad)",» » { XX } },	8402 { Bad_Opcode },

7185 { "(bad)",» » { XX } },	8403 { Bad_Opcode },

7186 { "(bad)",» » { XX } },	8404 { Bad_Opcode },

7187 { "(bad)",» » { XX } },	8405 { Bad_Opcode },

7188 { "(bad)",» » { XX } },	8406 { Bad_Opcode },

7189 { "(bad)",» » { XX } },	8407 { Bad_Opcode },

7190 /* e8 */	8408 /* e8 */

7191 { "(bad)",» » { XX } },	8409 { Bad_Opcode },

7192 { "(bad)",» » { XX } },	8410 { Bad_Opcode },

7193 { "(bad)",» » { XX } },	8411 { Bad_Opcode },

7194 { "(bad)",» » { XX } },	8412 { Bad_Opcode },

7195 { "(bad)",» » { XX } },	8413 { Bad_Opcode },

7196 { "(bad)",» » { XX } },	8414 { Bad_Opcode },

7197 { "(bad)",» » { XX } },	8415 { Bad_Opcode },

7198 { "(bad)",» » { XX } },	8416 { Bad_Opcode },

7199 /* f0 */	8417 /* f0 */

7200 { "(bad)",» » { XX } },	8418 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },

7201 { "(bad)",» » { XX } },	8419 { Bad_Opcode },

7202 { "(bad)",» » { XX } },	8420 { Bad_Opcode },

7203 { "(bad)",» » { XX } },	8421 { Bad_Opcode },

7204 { "(bad)",» » { XX } },	8422 { Bad_Opcode },

7205 { "(bad)",» » { XX } },	8423 { Bad_Opcode },

7206 { "(bad)",» » { XX } },	8424 { Bad_Opcode },

7207 { "(bad)",» » { XX } },	8425 { Bad_Opcode },

7208 /* f8 */	8426 /* f8 */

7209 { "(bad)",» » { XX } },	8427 { Bad_Opcode },

7210 { "(bad)",» » { XX } },	8428 { Bad_Opcode },

7211 { "(bad)",» » { XX } },	8429 { Bad_Opcode },

7212 { "(bad)",» » { XX } },	8430 { Bad_Opcode },

7213 { "(bad)",» » { XX } },	8431 { Bad_Opcode },

7214 { "(bad)",» » { XX } },	8432 { Bad_Opcode },

7215 { "(bad)",» » { XX } },	8433 { Bad_Opcode },

7216 { "(bad)",» » { XX } },	8434 { Bad_Opcode },

7217 },	8435 },

7218 };	8436 };

7219	8437

7220 static const struct dis386 vex_len_table[][2] = {	8438 static const struct dis386 vex_len_table[][2] = {

7221 /* VEX_LEN_10_P_1 */	8439 /* VEX_LEN_0F10_P_1 */

7222 {	8440 {

7223 { "vmovss", { XMVex, Vex128, EXd } },	8441 { VEX_W_TABLE (VEX_W_0F10_P_1) },

7224 { "(bad)", { XX } },	8442 { VEX_W_TABLE (VEX_W_0F10_P_1) },

7225 },	8443 },

7226	8444

7227 /* VEX_LEN_10_P_3 */	8445 /* VEX_LEN_0F10_P_3 */

7228 {	8446 {

7229 { "vmovsd", { XMVex, Vex128, EXq } },	8447 { VEX_W_TABLE (VEX_W_0F10_P_3) },

7230 { "(bad)", { XX } },	8448 { VEX_W_TABLE (VEX_W_0F10_P_3) },

7231 },	8449 },

7232	8450

7233 /* VEX_LEN_11_P_1 */	8451 /* VEX_LEN_0F11_P_1 */

7234 {	8452 {

7235 { "vmovss", { EXdVexS, Vex128, XM } },	8453 { VEX_W_TABLE (VEX_W_0F11_P_1) },

7236 { "(bad)", { XX } },	8454 { VEX_W_TABLE (VEX_W_0F11_P_1) },

7237 },	8455 },

7238	8456

7239 /* VEX_LEN_11_P_3 */	8457 /* VEX_LEN_0F11_P_3 */

7240 {	8458 {

7241 { "vmovsd", { EXqVexS, Vex128, XM } },	8459 { VEX_W_TABLE (VEX_W_0F11_P_3) },

7242 { "(bad)", { XX } },	8460 { VEX_W_TABLE (VEX_W_0F11_P_3) },

7243 },	8461 },

7244	8462

7245 /* VEX_LEN_12_P_0_M_0 */	8463 /* VEX_LEN_0F12_P_0_M_0 */

7246 {	8464 {

	8465 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },

	8466 },

	8467

	8468 /* VEX_LEN_0F12_P_0_M_1 */

	8469 {

	8470 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },

	8471 },

	8472

	8473 /* VEX_LEN_0F12_P_2 */

	8474 {

	8475 { VEX_W_TABLE (VEX_W_0F12_P_2) },

	8476 },

	8477

	8478 /* VEX_LEN_0F13_M_0 */

	8479 {

	8480 { VEX_W_TABLE (VEX_W_0F13_M_0) },

	8481 },

	8482

	8483 /* VEX_LEN_0F16_P_0_M_0 */

	8484 {

	8485 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },

	8486 },

	8487

	8488 /* VEX_LEN_0F16_P_0_M_1 */

	8489 {

	8490 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },

	8491 },

	8492

	8493 /* VEX_LEN_0F16_P_2 */

	8494 {

	8495 { VEX_W_TABLE (VEX_W_0F16_P_2) },

	8496 },

	8497

	8498 /* VEX_LEN_0F17_M_0 */

	8499 {

	8500 { VEX_W_TABLE (VEX_W_0F17_M_0) },

	8501 },

	8502

	8503 /* VEX_LEN_0F2A_P_1 */

	8504 {

	8505 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },

	8506 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },

	8507 },

	8508

	8509 /* VEX_LEN_0F2A_P_3 */

	8510 {

	8511 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },

	8512 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },

	8513 },

	8514

	8515 /* VEX_LEN_0F2C_P_1 */

	8516 {

	8517 { "vcvttss2siY", { Gv, EXdScalar } },

	8518 { "vcvttss2siY", { Gv, EXdScalar } },

	8519 },

	8520

	8521 /* VEX_LEN_0F2C_P_3 */

	8522 {

	8523 { "vcvttsd2siY", { Gv, EXqScalar } },

	8524 { "vcvttsd2siY", { Gv, EXqScalar } },

	8525 },

	8526

	8527 /* VEX_LEN_0F2D_P_1 */

	8528 {

	8529 { "vcvtss2siY", { Gv, EXdScalar } },

	8530 { "vcvtss2siY", { Gv, EXdScalar } },

	8531 },

	8532

	8533 /* VEX_LEN_0F2D_P_3 */

	8534 {

	8535 { "vcvtsd2siY", { Gv, EXqScalar } },

	8536 { "vcvtsd2siY", { Gv, EXqScalar } },

	8537 },

	8538

	8539 /* VEX_LEN_0F2E_P_0 */

	8540 {

	8541 { VEX_W_TABLE (VEX_W_0F2E_P_0) },

	8542 { VEX_W_TABLE (VEX_W_0F2E_P_0) },

	8543 },

	8544

	8545 /* VEX_LEN_0F2E_P_2 */

	8546 {

	8547 { VEX_W_TABLE (VEX_W_0F2E_P_2) },

	8548 { VEX_W_TABLE (VEX_W_0F2E_P_2) },

	8549 },

	8550

	8551 /* VEX_LEN_0F2F_P_0 */

	8552 {

	8553 { VEX_W_TABLE (VEX_W_0F2F_P_0) },

	8554 { VEX_W_TABLE (VEX_W_0F2F_P_0) },

	8555 },

	8556

	8557 /* VEX_LEN_0F2F_P_2 */

	8558 {

	8559 { VEX_W_TABLE (VEX_W_0F2F_P_2) },

	8560 { VEX_W_TABLE (VEX_W_0F2F_P_2) },

	8561 },

	8562

	8563 /* VEX_LEN_0F51_P_1 */

	8564 {

	8565 { VEX_W_TABLE (VEX_W_0F51_P_1) },

	8566 { VEX_W_TABLE (VEX_W_0F51_P_1) },

	8567 },

	8568

	8569 /* VEX_LEN_0F51_P_3 */

	8570 {

	8571 { VEX_W_TABLE (VEX_W_0F51_P_3) },

	8572 { VEX_W_TABLE (VEX_W_0F51_P_3) },

	8573 },

	8574

	8575 /* VEX_LEN_0F52_P_1 */

	8576 {

	8577 { VEX_W_TABLE (VEX_W_0F52_P_1) },

	8578 { VEX_W_TABLE (VEX_W_0F52_P_1) },

	8579 },

	8580

	8581 /* VEX_LEN_0F53_P_1 */

	8582 {

	8583 { VEX_W_TABLE (VEX_W_0F53_P_1) },

	8584 { VEX_W_TABLE (VEX_W_0F53_P_1) },

	8585 },

	8586

	8587 /* VEX_LEN_0F58_P_1 */

	8588 {

	8589 { VEX_W_TABLE (VEX_W_0F58_P_1) },

	8590 { VEX_W_TABLE (VEX_W_0F58_P_1) },

	8591 },

	8592

	8593 /* VEX_LEN_0F58_P_3 */

	8594 {

	8595 { VEX_W_TABLE (VEX_W_0F58_P_3) },

	8596 { VEX_W_TABLE (VEX_W_0F58_P_3) },

	8597 },

	8598

	8599 /* VEX_LEN_0F59_P_1 */

	8600 {

	8601 { VEX_W_TABLE (VEX_W_0F59_P_1) },

	8602 { VEX_W_TABLE (VEX_W_0F59_P_1) },

	8603 },

	8604

	8605 /* VEX_LEN_0F59_P_3 */

	8606 {

	8607 { VEX_W_TABLE (VEX_W_0F59_P_3) },

	8608 { VEX_W_TABLE (VEX_W_0F59_P_3) },

	8609 },

	8610

	8611 /* VEX_LEN_0F5A_P_1 */

	8612 {

	8613 { VEX_W_TABLE (VEX_W_0F5A_P_1) },

	8614 { VEX_W_TABLE (VEX_W_0F5A_P_1) },

	8615 },

	8616

	8617 /* VEX_LEN_0F5A_P_3 */

	8618 {

	8619 { VEX_W_TABLE (VEX_W_0F5A_P_3) },

	8620 { VEX_W_TABLE (VEX_W_0F5A_P_3) },

	8621 },

	8622

	8623 /* VEX_LEN_0F5C_P_1 */

	8624 {

	8625 { VEX_W_TABLE (VEX_W_0F5C_P_1) },

	8626 { VEX_W_TABLE (VEX_W_0F5C_P_1) },

	8627 },

	8628

	8629 /* VEX_LEN_0F5C_P_3 */

	8630 {

	8631 { VEX_W_TABLE (VEX_W_0F5C_P_3) },

	8632 { VEX_W_TABLE (VEX_W_0F5C_P_3) },

	8633 },

	8634

	8635 /* VEX_LEN_0F5D_P_1 */

	8636 {

	8637 { VEX_W_TABLE (VEX_W_0F5D_P_1) },

	8638 { VEX_W_TABLE (VEX_W_0F5D_P_1) },

	8639 },

	8640

	8641 /* VEX_LEN_0F5D_P_3 */

	8642 {

	8643 { VEX_W_TABLE (VEX_W_0F5D_P_3) },

	8644 { VEX_W_TABLE (VEX_W_0F5D_P_3) },

	8645 },

	8646

	8647 /* VEX_LEN_0F5E_P_1 */

	8648 {

	8649 { VEX_W_TABLE (VEX_W_0F5E_P_1) },

	8650 { VEX_W_TABLE (VEX_W_0F5E_P_1) },

	8651 },

	8652

	8653 /* VEX_LEN_0F5E_P_3 */

	8654 {

	8655 { VEX_W_TABLE (VEX_W_0F5E_P_3) },

	8656 { VEX_W_TABLE (VEX_W_0F5E_P_3) },

	8657 },

	8658

	8659 /* VEX_LEN_0F5F_P_1 */

	8660 {

	8661 { VEX_W_TABLE (VEX_W_0F5F_P_1) },

	8662 { VEX_W_TABLE (VEX_W_0F5F_P_1) },

	8663 },

	8664

	8665 /* VEX_LEN_0F5F_P_3 */

	8666 {

	8667 { VEX_W_TABLE (VEX_W_0F5F_P_3) },

	8668 { VEX_W_TABLE (VEX_W_0F5F_P_3) },

	8669 },

	8670

	8671 /* VEX_LEN_0F6E_P_2 */

	8672 {

	8673 { "vmovK", { XMScalar, Edq } },

	8674 { "vmovK", { XMScalar, Edq } },

	8675 },

	8676

	8677 /* VEX_LEN_0F7E_P_1 */

	8678 {

	8679 { VEX_W_TABLE (VEX_W_0F7E_P_1) },

	8680 { VEX_W_TABLE (VEX_W_0F7E_P_1) },

	8681 },

	8682

	8683 /* VEX_LEN_0F7E_P_2 */

	8684 {

	8685 { "vmovK", { Edq, XMScalar } },

	8686 { "vmovK", { Edq, XMScalar } },

	8687 },

	8688

	8689 /* VEX_LEN_0FAE_R_2_M_0 */

	8690 {

	8691 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },

	8692 },

	8693

	8694 /* VEX_LEN_0FAE_R_3_M_0 */

	8695 {

	8696 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },

	8697 },

	8698

	8699 /* VEX_LEN_0FC2_P_1 */

	8700 {

	8701 { VEX_W_TABLE (VEX_W_0FC2_P_1) },

	8702 { VEX_W_TABLE (VEX_W_0FC2_P_1) },

	8703 },

	8704

	8705 /* VEX_LEN_0FC2_P_3 */

	8706 {

	8707 { VEX_W_TABLE (VEX_W_0FC2_P_3) },

	8708 { VEX_W_TABLE (VEX_W_0FC2_P_3) },

	8709 },

	8710

	8711 /* VEX_LEN_0FC4_P_2 */

	8712 {

	8713 { VEX_W_TABLE (VEX_W_0FC4_P_2) },

	8714 },

	8715

	8716 /* VEX_LEN_0FC5_P_2 */

	8717 {

	8718 { VEX_W_TABLE (VEX_W_0FC5_P_2) },

	8719 },

	8720

	8721 /* VEX_LEN_0FD6_P_2 */

	8722 {

	8723 { VEX_W_TABLE (VEX_W_0FD6_P_2) },

	8724 { VEX_W_TABLE (VEX_W_0FD6_P_2) },

	8725 },

	8726

	8727 /* VEX_LEN_0FF7_P_2 */

	8728 {

	8729 { VEX_W_TABLE (VEX_W_0FF7_P_2) },

	8730 },

	8731

	8732 /* VEX_LEN_0F3816_P_2 */

	8733 {

	8734 { Bad_Opcode },

	8735 { VEX_W_TABLE (VEX_W_0F3816_P_2) },

	8736 },

	8737

	8738 /* VEX_LEN_0F3819_P_2 */

	8739 {

	8740 { Bad_Opcode },

	8741 { VEX_W_TABLE (VEX_W_0F3819_P_2) },

	8742 },

	8743

	8744 /* VEX_LEN_0F381A_P_2_M_0 */

	8745 {

	8746 { Bad_Opcode },

	8747 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },

	8748 },

	8749

	8750 /* VEX_LEN_0F3836_P_2 */

	8751 {

	8752 { Bad_Opcode },

	8753 { VEX_W_TABLE (VEX_W_0F3836_P_2) },

	8754 },

	8755

	8756 /* VEX_LEN_0F3841_P_2 */

	8757 {

	8758 { VEX_W_TABLE (VEX_W_0F3841_P_2) },

	8759 },

	8760

	8761 /* VEX_LEN_0F385A_P_2_M_0 */

	8762 {

	8763 { Bad_Opcode },

	8764 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },

	8765 },

	8766

	8767 /* VEX_LEN_0F38DB_P_2 */

	8768 {

	8769 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },

	8770 },

	8771

	8772 /* VEX_LEN_0F38DC_P_2 */

	8773 {

	8774 { VEX_W_TABLE (VEX_W_0F38DC_P_2) },

	8775 },

	8776

	8777 /* VEX_LEN_0F38DD_P_2 */

	8778 {

	8779 { VEX_W_TABLE (VEX_W_0F38DD_P_2) },

	8780 },

	8781

	8782 /* VEX_LEN_0F38DE_P_2 */

	8783 {

	8784 { VEX_W_TABLE (VEX_W_0F38DE_P_2) },

	8785 },

	8786

	8787 /* VEX_LEN_0F38DF_P_2 */

	8788 {

	8789 { VEX_W_TABLE (VEX_W_0F38DF_P_2) },

	8790 },

	8791

	8792 /* VEX_LEN_0F38F2_P_0 */

	8793 {

	8794 { "andnS", { Gdq, VexGdq, Edq } },

	8795 },

	8796

	8797 /* VEX_LEN_0F38F3_R_1_P_0 */

	8798 {

	8799 { "blsrS", { VexGdq, Edq } },

	8800 },

	8801

	8802 /* VEX_LEN_0F38F3_R_2_P_0 */

	8803 {

	8804 { "blsmskS", { VexGdq, Edq } },

	8805 },

	8806

	8807 /* VEX_LEN_0F38F3_R_3_P_0 */

	8808 {

	8809 { "blsiS", { VexGdq, Edq } },

	8810 },

	8811

	8812 /* VEX_LEN_0F38F5_P_0 */

	8813 {

	8814 { "bzhiS", { Gdq, Edq, VexGdq } },

	8815 },

	8816

	8817 /* VEX_LEN_0F38F5_P_1 */

	8818 {

	8819 { "pextS", { Gdq, VexGdq, Edq } },

	8820 },

	8821

	8822 /* VEX_LEN_0F38F5_P_3 */

	8823 {

	8824 { "pdepS", { Gdq, VexGdq, Edq } },

	8825 },

	8826

	8827 /* VEX_LEN_0F38F6_P_3 */

	8828 {

	8829 { "mulxS", { Gdq, VexGdq, Edq } },

	8830 },

	8831

	8832 /* VEX_LEN_0F38F7_P_0 */

	8833 {

	8834 { "bextrS", { Gdq, Edq, VexGdq } },

	8835 },

	8836

	8837 /* VEX_LEN_0F38F7_P_1 */

	8838 {

	8839 { "sarxS", { Gdq, Edq, VexGdq } },

	8840 },

	8841

	8842 /* VEX_LEN_0F38F7_P_2 */

	8843 {

	8844 { "shlxS", { Gdq, Edq, VexGdq } },

	8845 },

	8846

	8847 /* VEX_LEN_0F38F7_P_3 */

	8848 {

	8849 { "shrxS", { Gdq, Edq, VexGdq } },

	8850 },

	8851

	8852 /* VEX_LEN_0F3A00_P_2 */

	8853 {

	8854 { Bad_Opcode },

	8855 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },

	8856 },

	8857

	8858 /* VEX_LEN_0F3A01_P_2 */

	8859 {

	8860 { Bad_Opcode },

	8861 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },

	8862 },

	8863

	8864 /* VEX_LEN_0F3A06_P_2 */

	8865 {

	8866 { Bad_Opcode },

	8867 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },

	8868 },

	8869

	8870 /* VEX_LEN_0F3A0A_P_2 */

	8871 {

	8872 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },

	8873 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },

	8874 },

	8875

	8876 /* VEX_LEN_0F3A0B_P_2 */

	8877 {

	8878 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },

	8879 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },

	8880 },

	8881

	8882 /* VEX_LEN_0F3A14_P_2 */

	8883 {

	8884 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },

	8885 },

	8886

	8887 /* VEX_LEN_0F3A15_P_2 */

	8888 {

	8889 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },

	8890 },

	8891

	8892 /* VEX_LEN_0F3A16_P_2 */

	8893 {

	8894 { "vpextrK", { Edq, XM, Ib } },

	8895 },

	8896

	8897 /* VEX_LEN_0F3A17_P_2 */

	8898 {

	8899 { "vextractps", { Edqd, XM, Ib } },

	8900 },

	8901

	8902 /* VEX_LEN_0F3A18_P_2 */

	8903 {

	8904 { Bad_Opcode },

	8905 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },

	8906 },

	8907

	8908 /* VEX_LEN_0F3A19_P_2 */

	8909 {

	8910 { Bad_Opcode },

	8911 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },

	8912 },

	8913

	8914 /* VEX_LEN_0F3A20_P_2 */

	8915 {

	8916 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },

	8917 },

	8918

	8919 /* VEX_LEN_0F3A21_P_2 */

	8920 {

	8921 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },

	8922 },

	8923

	8924 /* VEX_LEN_0F3A22_P_2 */

	8925 {

	8926 { "vpinsrK", { XM, Vex128, Edq, Ib } },

	8927 },

	8928

	8929 /* VEX_LEN_0F3A38_P_2 */

	8930 {

	8931 { Bad_Opcode },

	8932 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },

	8933 },

	8934

	8935 /* VEX_LEN_0F3A39_P_2 */

	8936 {

	8937 { Bad_Opcode },

	8938 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },

	8939 },

	8940

	8941 /* VEX_LEN_0F3A41_P_2 */

	8942 {

	8943 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },

	8944 },

	8945

	8946 /* VEX_LEN_0F3A44_P_2 */

	8947 {

	8948 { VEX_W_TABLE (VEX_W_0F3A44_P_2) },

	8949 },

	8950

	8951 /* VEX_LEN_0F3A46_P_2 */

	8952 {

	8953 { Bad_Opcode },

	8954 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },

	8955 },

	8956

	8957 /* VEX_LEN_0F3A60_P_2 */

	8958 {

	8959 { VEX_W_TABLE (VEX_W_0F3A60_P_2) },

	8960 },

	8961

	8962 /* VEX_LEN_0F3A61_P_2 */

	8963 {

	8964 { VEX_W_TABLE (VEX_W_0F3A61_P_2) },

	8965 },

	8966

	8967 /* VEX_LEN_0F3A62_P_2 */

	8968 {

	8969 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },

	8970 },

	8971

	8972 /* VEX_LEN_0F3A63_P_2 */

	8973 {

	8974 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },

	8975 },

	8976

	8977 /* VEX_LEN_0F3A6A_P_2 */

	8978 {

	8979 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },

	8980 },

	8981

	8982 /* VEX_LEN_0F3A6B_P_2 */

	8983 {

	8984 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },

	8985 },

	8986

	8987 /* VEX_LEN_0F3A6E_P_2 */

	8988 {

	8989 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },

	8990 },

	8991

	8992 /* VEX_LEN_0F3A6F_P_2 */

	8993 {

	8994 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },

	8995 },

	8996

	8997 /* VEX_LEN_0F3A7A_P_2 */

	8998 {

	8999 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },

	9000 },

	9001

	9002 /* VEX_LEN_0F3A7B_P_2 */

	9003 {

	9004 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },

	9005 },

	9006

	9007 /* VEX_LEN_0F3A7E_P_2 */

	9008 {

	9009 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },

	9010 },

	9011

	9012 /* VEX_LEN_0F3A7F_P_2 */

	9013 {

	9014 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },

	9015 },

	9016

	9017 /* VEX_LEN_0F3ADF_P_2 */

	9018 {

	9019 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },

	9020 },

	9021

	9022 /* VEX_LEN_0F3AF0_P_3 */

	9023 {

	9024 { "rorxS", { Gdq, Edq, Ib } },

	9025 },

	9026

	9027 /* VEX_LEN_0FXOP_08_CC */

	9028 {

	9029 { "vpcomb", { XM, Vex128, EXx, Ib } },

	9030 },

	9031

	9032 /* VEX_LEN_0FXOP_08_CD */

	9033 {

	9034 { "vpcomw", { XM, Vex128, EXx, Ib } },

	9035 },

	9036

	9037 /* VEX_LEN_0FXOP_08_CE */

	9038 {

	9039 { "vpcomd", { XM, Vex128, EXx, Ib } },

	9040 },

	9041

	9042 /* VEX_LEN_0FXOP_08_CF */

	9043 {

	9044 { "vpcomq", { XM, Vex128, EXx, Ib } },

	9045 },

	9046

	9047 /* VEX_LEN_0FXOP_08_EC */

	9048 {

	9049 { "vpcomub", { XM, Vex128, EXx, Ib } },

	9050 },

	9051

	9052 /* VEX_LEN_0FXOP_08_ED */

	9053 {

	9054 { "vpcomuw", { XM, Vex128, EXx, Ib } },

	9055 },

	9056

	9057 /* VEX_LEN_0FXOP_08_EE */

	9058 {

	9059 { "vpcomud", { XM, Vex128, EXx, Ib } },

	9060 },

	9061

	9062 /* VEX_LEN_0FXOP_08_EF */

	9063 {

	9064 { "vpcomuq", { XM, Vex128, EXx, Ib } },

	9065 },

	9066

	9067 /* VEX_LEN_0FXOP_09_80 */

	9068 {

	9069 { "vfrczps", { XM, EXxmm } },

	9070 { "vfrczps", { XM, EXymmq } },

	9071 },

	9072

	9073 /* VEX_LEN_0FXOP_09_81 */

	9074 {

	9075 { "vfrczpd", { XM, EXxmm } },

	9076 { "vfrczpd", { XM, EXymmq } },

	9077 },

	9078 };

	9079

	9080 static const struct dis386 vex_w_table[][2] = {

	9081 {

	9082 /* VEX_W_0F10_P_0 */

	9083 { "vmovups", { XM, EXx } },

	9084 },

	9085 {

	9086 /* VEX_W_0F10_P_1 */

	9087 { "vmovss", { XMVexScalar, VexScalar, EXdScalar } },

	9088 },

	9089 {

	9090 /* VEX_W_0F10_P_2 */

	9091 { "vmovupd", { XM, EXx } },

	9092 },

	9093 {

	9094 /* VEX_W_0F10_P_3 */

	9095 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } },

	9096 },

	9097 {

	9098 /* VEX_W_0F11_P_0 */

	9099 { "vmovups", { EXxS, XM } },

	9100 },

	9101 {

	9102 /* VEX_W_0F11_P_1 */

	9103 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } },

	9104 },

	9105 {

	9106 /* VEX_W_0F11_P_2 */

	9107 { "vmovupd", { EXxS, XM } },

	9108 },

	9109 {

	9110 /* VEX_W_0F11_P_3 */

	9111 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } },

	9112 },

	9113 {

	9114 /* VEX_W_0F12_P_0_M_0 */

7247 { "vmovlps", { XM, Vex128, EXq } },	9115 { "vmovlps", { XM, Vex128, EXq } },

7248 { "(bad)",» » { XX } },	9116 },

7249 },	9117 {

7250	9118 /* VEX_W_0F12_P_0_M_1 */

7251 /* VEX_LEN_12_P_0_M_1 */

7252 {

7253 { "vmovhlps", { XM, Vex128, EXq } },	9119 { "vmovhlps", { XM, Vex128, EXq } },

7254 { "(bad)",» » { XX } },	9120 },

7255 },	9121 {

7256	9122 /* VEX_W_0F12_P_1 */

7257 /* VEX_LEN_12_P_2 */	9123 { "vmovsldup",» { XM, EXx } },

7258 {	9124 },

	9125 {

	9126 /* VEX_W_0F12_P_2 */

7259 { "vmovlpd", { XM, Vex128, EXq } },	9127 { "vmovlpd", { XM, Vex128, EXq } },

7260 { "(bad)",» » { XX } },	9128 },

7261 },	9129 {

7262	9130 /* VEX_W_0F12_P_3 */

7263 /* VEX_LEN_13_M_0 */	9131 { "vmovddup",» { XM, EXymmq } },

7264 {	9132 },

	9133 {

	9134 /* VEX_W_0F13_M_0 */

7265 { "vmovlpX", { EXq, XM } },	9135 { "vmovlpX", { EXq, XM } },

7266 { "(bad)",» » { XX } },	9136 },

7267 },	9137 {

7268	9138 /* VEX_W_0F14 */

7269 /* VEX_LEN_16_P_0_M_0 */	9139 { "vunpcklpX",» { XM, Vex, EXx } },

7270 {	9140 },

	9141 {

	9142 /* VEX_W_0F15 */

	9143 { "vunpckhpX",» { XM, Vex, EXx } },

	9144 },

	9145 {

	9146 /* VEX_W_0F16_P_0_M_0 */

7271 { "vmovhps", { XM, Vex128, EXq } },	9147 { "vmovhps", { XM, Vex128, EXq } },

7272 { "(bad)",» » { XX } },	9148 },

7273 },	9149 {

7274	9150 /* VEX_W_0F16_P_0_M_1 */

7275 /* VEX_LEN_16_P_0_M_1 */

7276 {

7277 { "vmovlhps", { XM, Vex128, EXq } },	9151 { "vmovlhps", { XM, Vex128, EXq } },

7278 { "(bad)",» » { XX } },	9152 },

7279 },	9153 {

7280	9154 /* VEX_W_0F16_P_1 */

7281 /* VEX_LEN_16_P_2 */	9155 { "vmovshdup",» { XM, EXx } },

7282 {	9156 },

	9157 {

	9158 /* VEX_W_0F16_P_2 */

7283 { "vmovhpd", { XM, Vex128, EXq } },	9159 { "vmovhpd", { XM, Vex128, EXq } },

7284 { "(bad)",» » { XX } },	9160 },

7285 },	9161 {

7286	9162 /* VEX_W_0F17_M_0 */

7287 /* VEX_LEN_17_M_0 */

7288 {

7289 { "vmovhpX", { EXq, XM } },	9163 { "vmovhpX", { EXq, XM } },

7290 { "(bad)",» » { XX } },	9164 },

7291 },	9165 {

7292	9166 /* VEX_W_0F28 */

7293 /* VEX_LEN_2A_P_1 */	9167 { "vmovapX",» { XM, EXx } },

7294 {	9168 },

7295 { "vcvtsi2ss%LQ",» { XM, Vex128, Ev } },	9169 {

7296 { "(bad)",» » { XX } },	9170 /* VEX_W_0F29 */

7297 },	9171 { "vmovapX",» { EXxS, XM } },

7298	9172 },

7299 /* VEX_LEN_2A_P_3 */	9173 {

7300 {	9174 /* VEX_W_0F2B_M_0 */

7301 { "vcvtsi2sd%LQ",» { XM, Vex128, Ev } },	9175 { "vmovntpX",» { Mx, XM } },

7302 { "(bad)",» » { XX } },	9176 },

7303 },	9177 {

7304	9178 /* VEX_W_0F2E_P_0 */

7305 /* VEX_LEN_2C_P_1 */	9179 { "vucomiss",» { XMScalar, EXdScalar } },

7306 {	9180 },

7307 { "vcvttss2siY",» { Gv, EXd } },	9181 {

7308 { "(bad)",» » { XX } },	9182 /* VEX_W_0F2E_P_2 */

7309 },	9183 { "vucomisd",» { XMScalar, EXqScalar } },

7310	9184 },

7311 /* VEX_LEN_2C_P_3 */	9185 {

7312 {	9186 /* VEX_W_0F2F_P_0 */

7313 { "vcvttsd2siY",» { Gv, EXq } },	9187 { "vcomiss",» { XMScalar, EXdScalar } },

7314 { "(bad)",» » { XX } },	9188 },

7315 },	9189 {

7316	9190 /* VEX_W_0F2F_P_2 */

7317 /* VEX_LEN_2D_P_1 */	9191 { "vcomisd",» { XMScalar, EXqScalar } },

7318 {	9192 },

7319 { "vcvtss2siY",» { Gv, EXd } },	9193 {

7320 { "(bad)",» » { XX } },	9194 /* VEX_W_0F50_M_0 */

7321 },	9195 { "vmovmskpX",» { Gdq, XS } },

7322	9196 },

7323 /* VEX_LEN_2D_P_3 */	9197 {

7324 {	9198 /* VEX_W_0F51_P_0 */

7325 { "vcvtsd2siY",» { Gv, EXq } },	9199 { "vsqrtps",» { XM, EXx } },

7326 { "(bad)",» » { XX } },	9200 },

7327 },	9201 {

7328	9202 /* VEX_W_0F51_P_1 */

7329 /* VEX_LEN_2E_P_0 */	9203 { "vsqrtss",» { XMScalar, VexScalar, EXdScalar } },

7330 {	9204 },

7331 { "vucomiss",» { XM, EXd } },	9205 {

7332 { "(bad)",» » { XX } },	9206 /* VEX_W_0F51_P_2 */

7333 },	9207 { "vsqrtpd",» { XM, EXx } },

7334	9208 },

7335 /* VEX_LEN_2E_P_2 */	9209 {

7336 {	9210 /* VEX_W_0F51_P_3 */

7337 { "vucomisd",» { XM, EXq } },	9211 { "vsqrtsd",» { XMScalar, VexScalar, EXqScalar } },

7338 { "(bad)",» » { XX } },	9212 },

7339 },	9213 {

7340	9214 /* VEX_W_0F52_P_0 */

7341 /* VEX_LEN_2F_P_0 */	9215 { "vrsqrtps",» { XM, EXx } },

7342 {	9216 },

7343 { "vcomiss",» { XM, EXd } },	9217 {

7344 { "(bad)",» » { XX } },	9218 /* VEX_W_0F52_P_1 */

7345 },	9219 { "vrsqrtss",» { XMScalar, VexScalar, EXdScalar } },

7346	9220 },

7347 /* VEX_LEN_2F_P_2 */	9221 {

7348 {	9222 /* VEX_W_0F53_P_0 */

7349 { "vcomisd",» { XM, EXq } },	9223 { "vrcpps",»» { XM, EXx } },

7350 { "(bad)",» » { XX } },	9224 },

7351 },	9225 {

7352	9226 /* VEX_W_0F53_P_1 */

7353 /* VEX_LEN_51_P_1 */	9227 { "vrcpss",»» { XMScalar, VexScalar, EXdScalar } },

7354 {	9228 },

7355 { "vsqrtss",» { XM, Vex128, EXd } },	9229 {

7356 { "(bad)",» » { XX } },	9230 /* VEX_W_0F58_P_0 */

7357 },	9231 { "vaddps",»» { XM, Vex, EXx } },

7358	9232 },

7359 /* VEX_LEN_51_P_3 */	9233 {

7360 {	9234 /* VEX_W_0F58_P_1 */

7361 { "vsqrtsd",» { XM, Vex128, EXq } },	9235 { "vaddss",»» { XMScalar, VexScalar, EXdScalar } },

7362 { "(bad)",» » { XX } },	9236 },

7363 },	9237 {

7364	9238 /* VEX_W_0F58_P_2 */

7365 /* VEX_LEN_52_P_1 */	9239 { "vaddpd",»» { XM, Vex, EXx } },

7366 {	9240 },

7367 { "vrsqrtss",» { XM, Vex128, EXd } },	9241 {

7368 { "(bad)",» » { XX } },	9242 /* VEX_W_0F58_P_3 */

7369 },	9243 { "vaddsd",»» { XMScalar, VexScalar, EXqScalar } },

7370	9244 },

7371 /* VEX_LEN_53_P_1 */	9245 {

7372 {	9246 /* VEX_W_0F59_P_0 */

7373 { "vrcpss",»» { XM, Vex128, EXd } },	9247 { "vmulps",»» { XM, Vex, EXx } },

7374 { "(bad)",» » { XX } },	9248 },

7375 },	9249 {

7376	9250 /* VEX_W_0F59_P_1 */

7377 /* VEX_LEN_58_P_1 */	9251 { "vmulss",»» { XMScalar, VexScalar, EXdScalar } },

7378 {	9252 },

7379 { "vaddss",»» { XM, Vex128, EXd } },	9253 {

7380 { "(bad)",» » { XX } },	9254 /* VEX_W_0F59_P_2 */

7381 },	9255 { "vmulpd",»» { XM, Vex, EXx } },

7382	9256 },

7383 /* VEX_LEN_58_P_3 */	9257 {

7384 {	9258 /* VEX_W_0F59_P_3 */

7385 { "vaddsd",»» { XM, Vex128, EXq } },	9259 { "vmulsd",»» { XMScalar, VexScalar, EXqScalar } },

7386 { "(bad)",» » { XX } },	9260 },

7387 },	9261 {

7388	9262 /* VEX_W_0F5A_P_0 */

7389 /* VEX_LEN_59_P_1 */	9263 { "vcvtps2pd",» { XM, EXxmmq } },

7390 {	9264 },

7391 { "vmulss",»» { XM, Vex128, EXd } },	9265 {

7392 { "(bad)",» » { XX } },	9266 /* VEX_W_0F5A_P_1 */

7393 },	9267 { "vcvtss2sd",» { XMScalar, VexScalar, EXdScalar } },

7394	9268 },

7395 /* VEX_LEN_59_P_3 */	9269 {

7396 {	9270 /* VEX_W_0F5A_P_3 */

7397 { "vmulsd",»» { XM, Vex128, EXq } },	9271 { "vcvtsd2ss",» { XMScalar, VexScalar, EXqScalar } },

7398 { "(bad)",» » { XX } },	9272 },

7399 },	9273 {

7400	9274 /* VEX_W_0F5B_P_0 */

7401 /* VEX_LEN_5A_P_1 */	9275 { "vcvtdq2ps",» { XM, EXx } },

7402 {	9276 },

7403 { "vcvtss2sd",» { XM, Vex128, EXd } },	9277 {

7404 { "(bad)",» » { XX } },	9278 /* VEX_W_0F5B_P_1 */

7405 },	9279 { "vcvttps2dq",» { XM, EXx } },

7406	9280 },

7407 /* VEX_LEN_5A_P_3 */	9281 {

7408 {	9282 /* VEX_W_0F5B_P_2 */

7409 { "vcvtsd2ss",» { XM, Vex128, EXq } },	9283 { "vcvtps2dq",» { XM, EXx } },

7410 { "(bad)",» » { XX } },	9284 },

7411 },	9285 {

7412	9286 /* VEX_W_0F5C_P_0 */

7413 /* VEX_LEN_5C_P_1 */	9287 { "vsubps",»» { XM, Vex, EXx } },

7414 {	9288 },

7415 { "vsubss",»» { XM, Vex128, EXd } },	9289 {

7416 { "(bad)",» » { XX } },	9290 /* VEX_W_0F5C_P_1 */

7417 },	9291 { "vsubss",»» { XMScalar, VexScalar, EXdScalar } },

7418	9292 },

7419 /* VEX_LEN_5C_P_3 */	9293 {

7420 {	9294 /* VEX_W_0F5C_P_2 */

7421 { "vsubsd",»» { XM, Vex128, EXq } },	9295 { "vsubpd",»» { XM, Vex, EXx } },

7422 { "(bad)",» » { XX } },	9296 },

7423 },	9297 {

7424	9298 /* VEX_W_0F5C_P_3 */

7425 /* VEX_LEN_5D_P_1 */	9299 { "vsubsd",»» { XMScalar, VexScalar, EXqScalar } },

7426 {	9300 },

7427 { "vminss",»» { XM, Vex128, EXd } },	9301 {

7428 { "(bad)",» » { XX } },	9302 /* VEX_W_0F5D_P_0 */

7429 },	9303 { "vminps",»» { XM, Vex, EXx } },

7430	9304 },

7431 /* VEX_LEN_5D_P_3 */	9305 {

7432 {	9306 /* VEX_W_0F5D_P_1 */

7433 { "vminsd",»» { XM, Vex128, EXq } },	9307 { "vminss",»» { XMScalar, VexScalar, EXdScalar } },

7434 { "(bad)",» » { XX } },	9308 },

7435 },	9309 {

7436	9310 /* VEX_W_0F5D_P_2 */

7437 /* VEX_LEN_5E_P_1 */	9311 { "vminpd",»» { XM, Vex, EXx } },

7438 {	9312 },

7439 { "vdivss",»» { XM, Vex128, EXd } },	9313 {

7440 { "(bad)",» » { XX } },	9314 /* VEX_W_0F5D_P_3 */

7441 },	9315 { "vminsd",»» { XMScalar, VexScalar, EXqScalar } },

7442	9316 },

7443 /* VEX_LEN_5E_P_3 */	9317 {

7444 {	9318 /* VEX_W_0F5E_P_0 */

7445 { "vdivsd",»» { XM, Vex128, EXq } },	9319 { "vdivps",»» { XM, Vex, EXx } },

7446 { "(bad)",» » { XX } },	9320 },

7447 },	9321 {

7448	9322 /* VEX_W_0F5E_P_1 */

7449 /* VEX_LEN_5F_P_1 */	9323 { "vdivss",»» { XMScalar, VexScalar, EXdScalar } },

7450 {	9324 },

7451 { "vmaxss",»» { XM, Vex128, EXd } },	9325 {

7452 { "(bad)",» » { XX } },	9326 /* VEX_W_0F5E_P_2 */

7453 },	9327 { "vdivpd",»» { XM, Vex, EXx } },

7454	9328 },

7455 /* VEX_LEN_5F_P_3 */	9329 {

7456 {	9330 /* VEX_W_0F5E_P_3 */

7457 { "vmaxsd",»» { XM, Vex128, EXq } },	9331 { "vdivsd",»» { XMScalar, VexScalar, EXqScalar } },

7458 { "(bad)",» » { XX } },	9332 },

7459 },	9333 {

7460	9334 /* VEX_W_0F5F_P_0 */

7461 /* VEX_LEN_60_P_2 */	9335 { "vmaxps",»» { XM, Vex, EXx } },

7462 {	9336 },

7463 { "vpunpcklbw",» { XM, Vex128, EXx } },	9337 {

7464 { "(bad)",» » { XX } },	9338 /* VEX_W_0F5F_P_1 */

7465 },	9339 { "vmaxss",»» { XMScalar, VexScalar, EXdScalar } },

7466	9340 },

7467 /* VEX_LEN_61_P_2 */	9341 {

7468 {	9342 /* VEX_W_0F5F_P_2 */

7469 { "vpunpcklwd",» { XM, Vex128, EXx } },	9343 { "vmaxpd",»» { XM, Vex, EXx } },

7470 { "(bad)",» » { XX } },	9344 },

7471 },	9345 {

7472	9346 /* VEX_W_0F5F_P_3 */

7473 /* VEX_LEN_62_P_2 */	9347 { "vmaxsd",»» { XMScalar, VexScalar, EXqScalar } },

7474 {	9348 },

7475 { "vpunpckldq",» { XM, Vex128, EXx } },	9349 {

7476 { "(bad)",» » { XX } },	9350 /* VEX_W_0F60_P_2 */

7477 },	9351 { "vpunpcklbw",» { XM, Vex, EXx } },

7478	9352 },

7479 /* VEX_LEN_63_P_2 */	9353 {

7480 {	9354 /* VEX_W_0F61_P_2 */

7481 { "vpacksswb",» { XM, Vex128, EXx } },	9355 { "vpunpcklwd",» { XM, Vex, EXx } },

7482 { "(bad)",» » { XX } },	9356 },

7483 },	9357 {

7484	9358 /* VEX_W_0F62_P_2 */

7485 /* VEX_LEN_64_P_2 */	9359 { "vpunpckldq",» { XM, Vex, EXx } },

7486 {	9360 },

7487 { "vpcmpgtb",» { XM, Vex128, EXx } },	9361 {

7488 { "(bad)",» » { XX } },	9362 /* VEX_W_0F63_P_2 */

7489 },	9363 { "vpacksswb",» { XM, Vex, EXx } },

7490	9364 },

7491 /* VEX_LEN_65_P_2 */	9365 {

7492 {	9366 /* VEX_W_0F64_P_2 */

7493 { "vpcmpgtw",» { XM, Vex128, EXx } },	9367 { "vpcmpgtb",» { XM, Vex, EXx } },

7494 { "(bad)",» » { XX } },	9368 },

7495 },	9369 {

7496	9370 /* VEX_W_0F65_P_2 */

7497 /* VEX_LEN_66_P_2 */	9371 { "vpcmpgtw",» { XM, Vex, EXx } },

7498 {	9372 },

7499 { "vpcmpgtd",» { XM, Vex128, EXx } },	9373 {

7500 { "(bad)",» » { XX } },	9374 /* VEX_W_0F66_P_2 */

7501 },	9375 { "vpcmpgtd",» { XM, Vex, EXx } },

7502	9376 },

7503 /* VEX_LEN_67_P_2 */	9377 {

7504 {	9378 /* VEX_W_0F67_P_2 */

7505 { "vpackuswb",» { XM, Vex128, EXx } },	9379 { "vpackuswb",» { XM, Vex, EXx } },

7506 { "(bad)",» » { XX } },	9380 },

7507 },	9381 {

7508	9382 /* VEX_W_0F68_P_2 */

7509 /* VEX_LEN_68_P_2 */	9383 { "vpunpckhbw",» { XM, Vex, EXx } },

7510 {	9384 },

7511 { "vpunpckhbw",» { XM, Vex128, EXx } },	9385 {

7512 { "(bad)",» » { XX } },	9386 /* VEX_W_0F69_P_2 */

7513 },	9387 { "vpunpckhwd",» { XM, Vex, EXx } },

7514	9388 },

7515 /* VEX_LEN_69_P_2 */	9389 {

7516 {	9390 /* VEX_W_0F6A_P_2 */

7517 { "vpunpckhwd",» { XM, Vex128, EXx } },	9391 { "vpunpckhdq",» { XM, Vex, EXx } },

7518 { "(bad)",» » { XX } },	9392 },

7519 },	9393 {

7520	9394 /* VEX_W_0F6B_P_2 */

7521 /* VEX_LEN_6A_P_2 */	9395 { "vpackssdw",» { XM, Vex, EXx } },

7522 {	9396 },

7523 { "vpunpckhdq",» { XM, Vex128, EXx } },	9397 {

7524 { "(bad)",» » { XX } },	9398 /* VEX_W_0F6C_P_2 */

7525 },	9399 { "vpunpcklqdq",» { XM, Vex, EXx } },

7526	9400 },

7527 /* VEX_LEN_6B_P_2 */	9401 {

7528 {	9402 /* VEX_W_0F6D_P_2 */

7529 { "vpackssdw",» { XM, Vex128, EXx } },	9403 { "vpunpckhqdq",» { XM, Vex, EXx } },

7530 { "(bad)",» » { XX } },	9404 },

7531 },	9405 {

7532	9406 /* VEX_W_0F6F_P_1 */

7533 /* VEX_LEN_6C_P_2 */	9407 { "vmovdqu",» { XM, EXx } },

7534 {	9408 },

7535 { "vpunpcklqdq",» { XM, Vex128, EXx } },	9409 {

7536 { "(bad)",» » { XX } },	9410 /* VEX_W_0F6F_P_2 */

7537 },	9411 { "vmovdqa",» { XM, EXx } },

7538	9412 },

7539 /* VEX_LEN_6D_P_2 */	9413 {

7540 {	9414 /* VEX_W_0F70_P_1 */

7541 { "vpunpckhqdq",» { XM, Vex128, EXx } },

7542 { "(bad)",» » { XX } },

7543 },

7544

7545 /* VEX_LEN_6E_P_2 */

7546 {

7547 { "vmovK",» » { XM, Edq } },

7548 { "(bad)",» » { XX } },

7549 },

7550

7551 /* VEX_LEN_70_P_1 */

7552 {

7553 { "vpshufhw", { XM, EXx, Ib } },	9415 { "vpshufhw", { XM, EXx, Ib } },

7554 { "(bad)",» » { XX } },	9416 },

7555 },	9417 {

7556	9418 /* VEX_W_0F70_P_2 */

7557 /* VEX_LEN_70_P_2 */

7558 {

7559 { "vpshufd", { XM, EXx, Ib } },	9419 { "vpshufd", { XM, EXx, Ib } },

7560 { "(bad)",» » { XX } },	9420 },

7561 },	9421 {

7562	9422 /* VEX_W_0F70_P_3 */

7563 /* VEX_LEN_70_P_3 */

7564 {

7565 { "vpshuflw", { XM, EXx, Ib } },	9423 { "vpshuflw", { XM, EXx, Ib } },

7566 { "(bad)",» » { XX } },	9424 },

7567 },	9425 {

7568	9426 /* VEX_W_0F71_R_2_P_2 */

7569 /* VEX_LEN_71_R_2_P_2 */	9427 { "vpsrlw",»» { Vex, XS, Ib } },

7570 {	9428 },

7571 { "vpsrlw",»» { Vex128, XS, Ib } },	9429 {

7572 { "(bad)",» » { XX } },	9430 /* VEX_W_0F71_R_4_P_2 */

7573 },	9431 { "vpsraw",»» { Vex, XS, Ib } },

7574	9432 },

7575 /* VEX_LEN_71_R_4_P_2 */	9433 {

7576 {	9434 /* VEX_W_0F71_R_6_P_2 */

7577 { "vpsraw",»» { Vex128, XS, Ib } },	9435 { "vpsllw",»» { Vex, XS, Ib } },

7578 { "(bad)",» » { XX } },	9436 },

7579 },	9437 {

7580	9438 /* VEX_W_0F72_R_2_P_2 */

7581 /* VEX_LEN_71_R_6_P_2 */	9439 { "vpsrld",»» { Vex, XS, Ib } },

7582 {	9440 },

7583 { "vpsllw",»» { Vex128, XS, Ib } },	9441 {

7584 { "(bad)",» » { XX } },	9442 /* VEX_W_0F72_R_4_P_2 */

7585 },	9443 { "vpsrad",»» { Vex, XS, Ib } },

7586	9444 },

7587 /* VEX_LEN_72_R_2_P_2 */	9445 {

7588 {	9446 /* VEX_W_0F72_R_6_P_2 */

7589 { "vpsrld",»» { Vex128, XS, Ib } },	9447 { "vpslld",»» { Vex, XS, Ib } },

7590 { "(bad)",» » { XX } },	9448 },

7591 },	9449 {

7592	9450 /* VEX_W_0F73_R_2_P_2 */

7593 /* VEX_LEN_72_R_4_P_2 */	9451 { "vpsrlq",»» { Vex, XS, Ib } },

7594 {	9452 },

7595 { "vpsrad",»» { Vex128, XS, Ib } },	9453 {

7596 { "(bad)",» » { XX } },	9454 /* VEX_W_0F73_R_3_P_2 */

7597 },	9455 { "vpsrldq",» { Vex, XS, Ib } },

7598	9456 },

7599 /* VEX_LEN_72_R_6_P_2 */	9457 {

7600 {	9458 /* VEX_W_0F73_R_6_P_2 */

7601 { "vpslld",»» { Vex128, XS, Ib } },	9459 { "vpsllq",»» { Vex, XS, Ib } },

7602 { "(bad)",» » { XX } },	9460 },

7603 },	9461 {

7604	9462 /* VEX_W_0F73_R_7_P_2 */

7605 /* VEX_LEN_73_R_2_P_2 */	9463 { "vpslldq",» { Vex, XS, Ib } },

7606 {	9464 },

7607 { "vpsrlq",»» { Vex128, XS, Ib } },	9465 {

7608 { "(bad)",» » { XX } },	9466 /* VEX_W_0F74_P_2 */

7609 },	9467 { "vpcmpeqb",» { XM, Vex, EXx } },

7610	9468 },

7611 /* VEX_LEN_73_R_3_P_2 */	9469 {

7612 {	9470 /* VEX_W_0F75_P_2 */

7613 { "vpsrldq",» { Vex128, XS, Ib } },	9471 { "vpcmpeqw",» { XM, Vex, EXx } },

7614 { "(bad)",» » { XX } },	9472 },

7615 },	9473 {

7616	9474 /* VEX_W_0F76_P_2 */

7617 /* VEX_LEN_73_R_6_P_2 */	9475 { "vpcmpeqd",» { XM, Vex, EXx } },

7618 {	9476 },

7619 { "vpsllq",»» { Vex128, XS, Ib } },	9477 {

7620 { "(bad)",» » { XX } },	9478 /* VEX_W_0F77_P_0 */

7621 },	9479 { "",» » { VZERO } },

7622	9480 },

7623 /* VEX_LEN_73_R_7_P_2 */	9481 {

7624 {	9482 /* VEX_W_0F7C_P_2 */

7625 { "vpslldq",» { Vex128, XS, Ib } },	9483 { "vhaddpd",» { XM, Vex, EXx } },

7626 { "(bad)",» » { XX } },	9484 },

7627 },	9485 {

7628	9486 /* VEX_W_0F7C_P_3 */

7629 /* VEX_LEN_74_P_2 */	9487 { "vhaddps",» { XM, Vex, EXx } },

7630 {	9488 },

7631 { "vpcmpeqb",» { XM, Vex128, EXx } },	9489 {

7632 { "(bad)",» » { XX } },	9490 /* VEX_W_0F7D_P_2 */

7633 },	9491 { "vhsubpd",» { XM, Vex, EXx } },

7634	9492 },

7635 /* VEX_LEN_75_P_2 */	9493 {

7636 {	9494 /* VEX_W_0F7D_P_3 */

7637 { "vpcmpeqw",» { XM, Vex128, EXx } },	9495 { "vhsubps",» { XM, Vex, EXx } },

7638 { "(bad)",» » { XX } },	9496 },

7639 },	9497 {

7640	9498 /* VEX_W_0F7E_P_1 */

7641 /* VEX_LEN_76_P_2 */	9499 { "vmovq",» » { XMScalar, EXqScalar } },

7642 {	9500 },

7643 { "vpcmpeqd",» { XM, Vex128, EXx } },	9501 {

7644 { "(bad)",» » { XX } },	9502 /* VEX_W_0F7F_P_1 */

7645 },	9503 { "vmovdqu",» { EXxS, XM } },

7646	9504 },

7647 /* VEX_LEN_7E_P_1 */	9505 {

7648 {	9506 /* VEX_W_0F7F_P_2 */

7649 { "vmovq",» » { XM, EXq } },	9507 { "vmovdqa",» { EXxS, XM } },

7650 { "(bad)",» » { XX } },	9508 },

7651 },	9509 {

7652	9510 /* VEX_W_0FAE_R_2_M_0 */

7653 /* VEX_LEN_7E_P_2 */

7654 {

7655 { "vmovK",» » { Edq, XM } },

7656 { "(bad)",» » { XX } },

7657 },

7658

7659 /* VEX_LEN_AE_R_2_M0 */

7660 {

7661 { "vldmxcsr", { Md } },	9511 { "vldmxcsr", { Md } },

7662 { "(bad)",» » { XX } },	9512 },

7663 },	9513 {

7664	9514 /* VEX_W_0FAE_R_3_M_0 */

7665 /* VEX_LEN_AE_R_3_M0 */

7666 {

7667 { "vstmxcsr", { Md } },	9515 { "vstmxcsr", { Md } },

7668 { "(bad)",» » { XX } },	9516 },

7669 },	9517 {

7670	9518 /* VEX_W_0FC2_P_0 */

7671 /* VEX_LEN_C2_P_1 */	9519 { "vcmpps",»» { XM, Vex, EXx, VCMP } },

7672 {	9520 },

7673 { "vcmpss",»» { XM, Vex128, EXd, VCMP } },	9521 {

7674 { "(bad)",» » { XX } },	9522 /* VEX_W_0FC2_P_1 */

7675 },	9523 { "vcmpss",»» { XMScalar, VexScalar, EXdScalar, VCMP } },

7676	9524 },

7677 /* VEX_LEN_C2_P_3 */	9525 {

7678 {	9526 /* VEX_W_0FC2_P_2 */

7679 { "vcmpsd",»» { XM, Vex128, EXq, VCMP } },	9527 { "vcmppd",»» { XM, Vex, EXx, VCMP } },

7680 { "(bad)",» » { XX } },	9528 },

7681 },	9529 {

7682	9530 /* VEX_W_0FC2_P_3 */

7683 /* VEX_LEN_C4_P_2 */	9531 { "vcmpsd",»» { XMScalar, VexScalar, EXqScalar, VCMP } },

7684 {	9532 },

	9533 {

	9534 /* VEX_W_0FC4_P_2 */

7685 { "vpinsrw", { XM, Vex128, Edqw, Ib } },	9535 { "vpinsrw", { XM, Vex128, Edqw, Ib } },

7686 { "(bad)",» » { XX } },	9536 },

7687 },	9537 {

7688	9538 /* VEX_W_0FC5_P_2 */

7689 /* VEX_LEN_C5_P_2 */

7690 {

7691 { "vpextrw", { Gdq, XS, Ib } },	9539 { "vpextrw", { Gdq, XS, Ib } },

7692 { "(bad)",» » { XX } },	9540 },

7693 },	9541 {

7694	9542 /* VEX_W_0FD0_P_2 */

7695 /* VEX_LEN_D1_P_2 */	9543 { "vaddsubpd",» { XM, Vex, EXx } },

7696 {	9544 },

7697 { "vpsrlw",»» { XM, Vex128, EXx } },	9545 {

7698 { "(bad)",» » { XX } },	9546 /* VEX_W_0FD0_P_3 */

7699 },	9547 { "vaddsubps",» { XM, Vex, EXx } },

7700	9548 },

7701 /* VEX_LEN_D2_P_2 */	9549 {

7702 {	9550 /* VEX_W_0FD1_P_2 */

7703 { "vpsrld",»» { XM, Vex128, EXx } },	9551 { "vpsrlw",»» { XM, Vex, EXxmm } },

7704 { "(bad)",» » { XX } },	9552 },

7705 },	9553 {

7706	9554 /* VEX_W_0FD2_P_2 */

7707 /* VEX_LEN_D3_P_2 */	9555 { "vpsrld",»» { XM, Vex, EXxmm } },

7708 {	9556 },

7709 { "vpsrlq",»» { XM, Vex128, EXx } },	9557 {

7710 { "(bad)",» » { XX } },	9558 /* VEX_W_0FD3_P_2 */

7711 },	9559 { "vpsrlq",»» { XM, Vex, EXxmm } },

7712	9560 },

7713 /* VEX_LEN_D4_P_2 */	9561 {

7714 {	9562 /* VEX_W_0FD4_P_2 */

7715 { "vpaddq",»» { XM, Vex128, EXx } },	9563 { "vpaddq",»» { XM, Vex, EXx } },

7716 { "(bad)",» » { XX } },	9564 },

7717 },	9565 {

7718	9566 /* VEX_W_0FD5_P_2 */

7719 /* VEX_LEN_D5_P_2 */	9567 { "vpmullw",» { XM, Vex, EXx } },

7720 {	9568 },

7721 { "vpmullw",» { XM, Vex128, EXx } },	9569 {

7722 { "(bad)",» » { XX } },	9570 /* VEX_W_0FD6_P_2 */

7723 },	9571 { "vmovq",» » { EXqScalarS, XMScalar } },

7724	9572 },

7725 /* VEX_LEN_D6_P_2 */	9573 {

7726 {	9574 /* VEX_W_0FD7_P_2_M_1 */

7727 { "vmovq",» » { EXqS, XM } },

7728 { "(bad)",» » { XX } },

7729 },

7730

7731 /* VEX_LEN_D7_P_2_M_1 */

7732 {

7733 { "vpmovmskb", { Gdq, XS } },	9575 { "vpmovmskb", { Gdq, XS } },

7734 { "(bad)",» » { XX } },	9576 },

7735 },	9577 {

7736	9578 /* VEX_W_0FD8_P_2 */

7737 /* VEX_LEN_D8_P_2 */	9579 { "vpsubusb",» { XM, Vex, EXx } },

7738 {	9580 },

7739 { "vpsubusb",» { XM, Vex128, EXx } },	9581 {

7740 { "(bad)",» » { XX } },	9582 /* VEX_W_0FD9_P_2 */

7741 },	9583 { "vpsubusw",» { XM, Vex, EXx } },

7742	9584 },

7743 /* VEX_LEN_D9_P_2 */	9585 {

7744 {	9586 /* VEX_W_0FDA_P_2 */

7745 { "vpsubusw",» { XM, Vex128, EXx } },	9587 { "vpminub",» { XM, Vex, EXx } },

7746 { "(bad)",» » { XX } },	9588 },

7747 },	9589 {

7748	9590 /* VEX_W_0FDB_P_2 */

7749 /* VEX_LEN_DA_P_2 */	9591 { "vpand",» » { XM, Vex, EXx } },

7750 {	9592 },

7751 { "vpminub",» { XM, Vex128, EXx } },	9593 {

7752 { "(bad)",» » { XX } },	9594 /* VEX_W_0FDC_P_2 */

7753 },	9595 { "vpaddusb",» { XM, Vex, EXx } },

7754	9596 },

7755 /* VEX_LEN_DB_P_2 */	9597 {

7756 {	9598 /* VEX_W_0FDD_P_2 */

7757 { "vpand",» » { XM, Vex128, EXx } },	9599 { "vpaddusw",» { XM, Vex, EXx } },

7758 { "(bad)",» » { XX } },	9600 },

7759 },	9601 {

7760	9602 /* VEX_W_0FDE_P_2 */

7761 /* VEX_LEN_DC_P_2 */	9603 { "vpmaxub",» { XM, Vex, EXx } },

7762 {	9604 },

7763 { "vpaddusb",» { XM, Vex128, EXx } },	9605 {

7764 { "(bad)",» » { XX } },	9606 /* VEX_W_0FDF_P_2 */

7765 },	9607 { "vpandn",»» { XM, Vex, EXx } },

7766	9608 },

7767 /* VEX_LEN_DD_P_2 */	9609 {

7768 {	9610 /* VEX_W_0FE0_P_2 */

7769 { "vpaddusw",» { XM, Vex128, EXx } },	9611 { "vpavgb",»» { XM, Vex, EXx } },

7770 { "(bad)",» » { XX } },	9612 },

7771 },	9613 {

7772	9614 /* VEX_W_0FE1_P_2 */

7773 /* VEX_LEN_DE_P_2 */	9615 { "vpsraw",»» { XM, Vex, EXxmm } },

7774 {	9616 },

7775 { "vpmaxub",» { XM, Vex128, EXx } },	9617 {

7776 { "(bad)",» » { XX } },	9618 /* VEX_W_0FE2_P_2 */

7777 },	9619 { "vpsrad",»» { XM, Vex, EXxmm } },

7778	9620 },

7779 /* VEX_LEN_DF_P_2 */	9621 {

7780 {	9622 /* VEX_W_0FE3_P_2 */

7781 { "vpandn",»» { XM, Vex128, EXx } },	9623 { "vpavgw",»» { XM, Vex, EXx } },

7782 { "(bad)",» » { XX } },	9624 },

7783 },	9625 {

7784	9626 /* VEX_W_0FE4_P_2 */

7785 /* VEX_LEN_E0_P_2 */	9627 { "vpmulhuw",» { XM, Vex, EXx } },

7786 {	9628 },

7787 { "vpavgb",»» { XM, Vex128, EXx } },	9629 {

7788 { "(bad)",» » { XX } },	9630 /* VEX_W_0FE5_P_2 */

7789 },	9631 { "vpmulhw",» { XM, Vex, EXx } },

7790	9632 },

7791 /* VEX_LEN_E1_P_2 */	9633 {

7792 {	9634 /* VEX_W_0FE6_P_1 */

7793 { "vpsraw",»» { XM, Vex128, EXx } },	9635 { "vcvtdq2pd",» { XM, EXxmmq } },

7794 { "(bad)",» » { XX } },	9636 },

7795 },	9637 {

7796	9638 /* VEX_W_0FE6_P_2 */

7797 /* VEX_LEN_E2_P_2 */	9639 { "vcvttpd2dq%XY",» { XMM, EXx } },

7798 {	9640 },

7799 { "vpsrad",»» { XM, Vex128, EXx } },	9641 {

7800 { "(bad)",» » { XX } },	9642 /* VEX_W_0FE6_P_3 */

7801 },	9643 { "vcvtpd2dq%XY",» { XMM, EXx } },

7802	9644 },

7803 /* VEX_LEN_E3_P_2 */	9645 {

7804 {	9646 /* VEX_W_0FE7_P_2_M_0 */

7805 { "vpavgw",»» { XM, Vex128, EXx } },	9647 { "vmovntdq",» { Mx, XM } },

7806 { "(bad)",» » { XX } },	9648 },

7807 },	9649 {

7808	9650 /* VEX_W_0FE8_P_2 */

7809 /* VEX_LEN_E4_P_2 */	9651 { "vpsubsb",» { XM, Vex, EXx } },

7810 {	9652 },

7811 { "vpmulhuw",» { XM, Vex128, EXx } },	9653 {

7812 { "(bad)",» » { XX } },	9654 /* VEX_W_0FE9_P_2 */

7813 },	9655 { "vpsubsw",» { XM, Vex, EXx } },

7814	9656 },

7815 /* VEX_LEN_E5_P_2 */	9657 {

7816 {	9658 /* VEX_W_0FEA_P_2 */

7817 { "vpmulhw",» { XM, Vex128, EXx } },	9659 { "vpminsw",» { XM, Vex, EXx } },

7818 { "(bad)",» » { XX } },	9660 },

7819 },	9661 {

7820	9662 /* VEX_W_0FEB_P_2 */

7821 /* VEX_LEN_E8_P_2 */	9663 { "vpor",» » { XM, Vex, EXx } },

7822 {	9664 },

7823 { "vpsubsb",» { XM, Vex128, EXx } },	9665 {

7824 { "(bad)",» » { XX } },	9666 /* VEX_W_0FEC_P_2 */

7825 },	9667 { "vpaddsb",» { XM, Vex, EXx } },

7826	9668 },

7827 /* VEX_LEN_E9_P_2 */	9669 {

7828 {	9670 /* VEX_W_0FED_P_2 */

7829 { "vpsubsw",» { XM, Vex128, EXx } },	9671 { "vpaddsw",» { XM, Vex, EXx } },

7830 { "(bad)",» » { XX } },	9672 },

7831 },	9673 {

7832	9674 /* VEX_W_0FEE_P_2 */

7833 /* VEX_LEN_EA_P_2 */	9675 { "vpmaxsw",» { XM, Vex, EXx } },

7834 {	9676 },

7835 { "vpminsw",» { XM, Vex128, EXx } },	9677 {

7836 { "(bad)",» » { XX } },	9678 /* VEX_W_0FEF_P_2 */

7837 },	9679 { "vpxor",» » { XM, Vex, EXx } },

7838	9680 },

7839 /* VEX_LEN_EB_P_2 */	9681 {

7840 {	9682 /* VEX_W_0FF0_P_3_M_0 */

7841 { "vpor",» » { XM, Vex128, EXx } },	9683 { "vlddqu",»» { XM, M } },

7842 { "(bad)",» » { XX } },	9684 },

7843 },	9685 {

7844	9686 /* VEX_W_0FF1_P_2 */

7845 /* VEX_LEN_EC_P_2 */	9687 { "vpsllw",»» { XM, Vex, EXxmm } },

7846 {	9688 },

7847 { "vpaddsb",» { XM, Vex128, EXx } },	9689 {

7848 { "(bad)",» » { XX } },	9690 /* VEX_W_0FF2_P_2 */

7849 },	9691 { "vpslld",»» { XM, Vex, EXxmm } },

7850	9692 },

7851 /* VEX_LEN_ED_P_2 */	9693 {

7852 {	9694 /* VEX_W_0FF3_P_2 */

7853 { "vpaddsw",» { XM, Vex128, EXx } },	9695 { "vpsllq",»» { XM, Vex, EXxmm } },

7854 { "(bad)",» » { XX } },	9696 },

7855 },	9697 {

7856	9698 /* VEX_W_0FF4_P_2 */

7857 /* VEX_LEN_EE_P_2 */	9699 { "vpmuludq",» { XM, Vex, EXx } },

7858 {	9700 },

7859 { "vpmaxsw",» { XM, Vex128, EXx } },	9701 {

7860 { "(bad)",» » { XX } },	9702 /* VEX_W_0FF5_P_2 */

7861 },	9703 { "vpmaddwd",» { XM, Vex, EXx } },

7862	9704 },

7863 /* VEX_LEN_EF_P_2 */	9705 {

7864 {	9706 /* VEX_W_0FF6_P_2 */

7865 { "vpxor",» » { XM, Vex128, EXx } },	9707 { "vpsadbw",» { XM, Vex, EXx } },

7866 { "(bad)",» » { XX } },	9708 },

7867 },	9709 {

7868	9710 /* VEX_W_0FF7_P_2 */

7869 /* VEX_LEN_F1_P_2 */

7870 {

7871 { "vpsllw",»» { XM, Vex128, EXx } },

7872 { "(bad)",» » { XX } },

7873 },

7874

7875 /* VEX_LEN_F2_P_2 */

7876 {

7877 { "vpslld",»» { XM, Vex128, EXx } },

7878 { "(bad)",» » { XX } },

7879 },

7880

7881 /* VEX_LEN_F3_P_2 */

7882 {

7883 { "vpsllq",»» { XM, Vex128, EXx } },

7884 { "(bad)",» » { XX } },

7885 },

7886

7887 /* VEX_LEN_F4_P_2 */

7888 {

7889 { "vpmuludq",» { XM, Vex128, EXx } },

7890 { "(bad)",» » { XX } },

7891 },

7892

7893 /* VEX_LEN_F5_P_2 */

7894 {

7895 { "vpmaddwd",» { XM, Vex128, EXx } },

7896 { "(bad)",» » { XX } },

7897 },

7898

7899 /* VEX_LEN_F6_P_2 */

7900 {

7901 { "vpsadbw",» { XM, Vex128, EXx } },

7902 { "(bad)",» » { XX } },

7903 },

7904

7905 /* VEX_LEN_F7_P_2 */

7906 {

7907 { "vmaskmovdqu", { XM, XS } },	9711 { "vmaskmovdqu", { XM, XS } },

7908 { "(bad)",» » { XX } },	9712 },

7909 },	9713 {

7910	9714 /* VEX_W_0FF8_P_2 */

7911 /* VEX_LEN_F8_P_2 */	9715 { "vpsubb",»» { XM, Vex, EXx } },

7912 {	9716 },

7913 { "vpsubb",»» { XM, Vex128, EXx } },	9717 {

7914 { "(bad)",» » { XX } },	9718 /* VEX_W_0FF9_P_2 */

7915 },	9719 { "vpsubw",»» { XM, Vex, EXx } },

7916	9720 },

7917 /* VEX_LEN_F9_P_2 */	9721 {

7918 {	9722 /* VEX_W_0FFA_P_2 */

7919 { "vpsubw",»» { XM, Vex128, EXx } },	9723 { "vpsubd",»» { XM, Vex, EXx } },

7920 { "(bad)",» » { XX } },	9724 },

7921 },	9725 {

7922	9726 /* VEX_W_0FFB_P_2 */

7923 /* VEX_LEN_FA_P_2 */	9727 { "vpsubq",»» { XM, Vex, EXx } },

7924 {	9728 },

7925 { "vpsubd",»» { XM, Vex128, EXx } },	9729 {

7926 { "(bad)",» » { XX } },	9730 /* VEX_W_0FFC_P_2 */

7927 },	9731 { "vpaddb",»» { XM, Vex, EXx } },

7928	9732 },

7929 /* VEX_LEN_FB_P_2 */	9733 {

7930 {	9734 /* VEX_W_0FFD_P_2 */

7931 { "vpsubq",»» { XM, Vex128, EXx } },	9735 { "vpaddw",»» { XM, Vex, EXx } },

7932 { "(bad)",» » { XX } },	9736 },

7933 },	9737 {

7934	9738 /* VEX_W_0FFE_P_2 */

7935 /* VEX_LEN_FC_P_2 */	9739 { "vpaddd",»» { XM, Vex, EXx } },

7936 {	9740 },

7937 { "vpaddb",»» { XM, Vex128, EXx } },	9741 {

7938 { "(bad)",» » { XX } },	9742 /* VEX_W_0F3800_P_2 */

7939 },	9743 { "vpshufb",» { XM, Vex, EXx } },

7940	9744 },

7941 /* VEX_LEN_FD_P_2 */	9745 {

7942 {	9746 /* VEX_W_0F3801_P_2 */

7943 { "vpaddw",»» { XM, Vex128, EXx } },	9747 { "vphaddw",» { XM, Vex, EXx } },

7944 { "(bad)",» » { XX } },	9748 },

7945 },	9749 {

7946	9750 /* VEX_W_0F3802_P_2 */

7947 /* VEX_LEN_FE_P_2 */	9751 { "vphaddd",» { XM, Vex, EXx } },

7948 {	9752 },

7949 { "vpaddd",»» { XM, Vex128, EXx } },	9753 {

7950 { "(bad)",» » { XX } },	9754 /* VEX_W_0F3803_P_2 */

7951 },	9755 { "vphaddsw",» { XM, Vex, EXx } },

7952	9756 },

7953 /* VEX_LEN_3800_P_2 */	9757 {

7954 {	9758 /* VEX_W_0F3804_P_2 */

7955 { "vpshufb",» { XM, Vex128, EXx } },	9759 { "vpmaddubsw",» { XM, Vex, EXx } },

7956 { "(bad)",» » { XX } },	9760 },

7957 },	9761 {

7958	9762 /* VEX_W_0F3805_P_2 */

7959 /* VEX_LEN_3801_P_2 */	9763 { "vphsubw",» { XM, Vex, EXx } },

7960 {	9764 },

7961 { "vphaddw",» { XM, Vex128, EXx } },	9765 {

7962 { "(bad)",» » { XX } },	9766 /* VEX_W_0F3806_P_2 */

7963 },	9767 { "vphsubd",» { XM, Vex, EXx } },

7964	9768 },

7965 /* VEX_LEN_3802_P_2 */	9769 {

7966 {	9770 /* VEX_W_0F3807_P_2 */

7967 { "vphaddd",» { XM, Vex128, EXx } },	9771 { "vphsubsw",» { XM, Vex, EXx } },

7968 { "(bad)",» » { XX } },	9772 },

7969 },	9773 {

7970	9774 /* VEX_W_0F3808_P_2 */

7971 /* VEX_LEN_3803_P_2 */	9775 { "vpsignb",» { XM, Vex, EXx } },

7972 {	9776 },

7973 { "vphaddsw",» { XM, Vex128, EXx } },	9777 {

7974 { "(bad)",» » { XX } },	9778 /* VEX_W_0F3809_P_2 */

7975 },	9779 { "vpsignw",» { XM, Vex, EXx } },

7976	9780 },

7977 /* VEX_LEN_3804_P_2 */	9781 {

7978 {	9782 /* VEX_W_0F380A_P_2 */

7979 { "vpmaddubsw",» { XM, Vex128, EXx } },	9783 { "vpsignd",» { XM, Vex, EXx } },

7980 { "(bad)",» » { XX } },	9784 },

7981 },	9785 {

7982	9786 /* VEX_W_0F380B_P_2 */

7983 /* VEX_LEN_3805_P_2 */	9787 { "vpmulhrsw",» { XM, Vex, EXx } },

7984 {	9788 },

7985 { "vphsubw",» { XM, Vex128, EXx } },	9789 {

7986 { "(bad)",» » { XX } },	9790 /* VEX_W_0F380C_P_2 */

7987 },	9791 { "vpermilps",» { XM, Vex, EXx } },

7988	9792 },

7989 /* VEX_LEN_3806_P_2 */	9793 {

7990 {	9794 /* VEX_W_0F380D_P_2 */

7991 { "vphsubd",» { XM, Vex128, EXx } },	9795 { "vpermilpd",» { XM, Vex, EXx } },

7992 { "(bad)",» » { XX } },	9796 },

7993 },	9797 {

7994	9798 /* VEX_W_0F380E_P_2 */

7995 /* VEX_LEN_3807_P_2 */	9799 { "vtestps",» { XM, EXx } },

7996 {	9800 },

7997 { "vphsubsw",» { XM, Vex128, EXx } },	9801 {

7998 { "(bad)",» » { XX } },	9802 /* VEX_W_0F380F_P_2 */

7999 },	9803 { "vtestpd",» { XM, EXx } },

8000	9804 },

8001 /* VEX_LEN_3808_P_2 */	9805 {

8002 {	9806 /* VEX_W_0F3816_P_2 */

8003 { "vpsignb",» { XM, Vex128, EXx } },	9807 { "vpermps",» { XM, Vex, EXx } },

8004 { "(bad)",» » { XX } },	9808 },

8005 },	9809 {

8006	9810 /* VEX_W_0F3817_P_2 */

8007 /* VEX_LEN_3809_P_2 */	9811 { "vptest",»» { XM, EXx } },

8008 {	9812 },

8009 { "vpsignw",» { XM, Vex128, EXx } },	9813 {

8010 { "(bad)",» » { XX } },	9814 /* VEX_W_0F3818_P_2 */

8011 },	9815 { "vbroadcastss",» { XM, EXxmm_md } },

8012	9816 },

8013 /* VEX_LEN_380A_P_2 */	9817 {

8014 {	9818 /* VEX_W_0F3819_P_2 */

8015 { "vpsignd",» { XM, Vex128, EXx } },	9819 { "vbroadcastsd",» { XM, EXxmm_mq } },

8016 { "(bad)",» » { XX } },	9820 },

8017 },	9821 {

8018	9822 /* VEX_W_0F381A_P_2_M_0 */

8019 /* VEX_LEN_380B_P_2 */

8020 {

8021 { "vpmulhrsw",» { XM, Vex128, EXx } },

8022 { "(bad)",» » { XX } },

8023 },

8024

8025 /* VEX_LEN_3819_P_2_M_0 */

8026 {

8027 { "(bad)",» » { XX } },

8028 { "vbroadcastsd",» { XM, Mq } },

8029 },

8030

8031 /* VEX_LEN_381A_P_2_M_0 */

8032 {

8033 { "(bad)",» » { XX } },

8034 { "vbroadcastf128", { XM, Mxmm } },	9823 { "vbroadcastf128", { XM, Mxmm } },

8035 },	9824 },

8036	9825 {

8037 /* VEX_LEN_381C_P_2 */	9826 /* VEX_W_0F381C_P_2 */

8038 {

8039 { "vpabsb", { XM, EXx } },	9827 { "vpabsb", { XM, EXx } },

8040 { "(bad)",» » { XX } },	9828 },

8041 },	9829 {

8042	9830 /* VEX_W_0F381D_P_2 */

8043 /* VEX_LEN_381D_P_2 */

8044 {

8045 { "vpabsw", { XM, EXx } },	9831 { "vpabsw", { XM, EXx } },

8046 { "(bad)",» » { XX } },	9832 },

8047 },	9833 {

8048	9834 /* VEX_W_0F381E_P_2 */

8049 /* VEX_LEN_381E_P_2 */

8050 {

8051 { "vpabsd", { XM, EXx } },	9835 { "vpabsd", { XM, EXx } },

8052 { "(bad)",» » { XX } },	9836 },

8053 },	9837 {

8054	9838 /* VEX_W_0F3820_P_2 */

8055 /* VEX_LEN_3820_P_2 */	9839 { "vpmovsxbw",» { XM, EXxmmq } },

8056 {	9840 },

8057 { "vpmovsxbw",» { XM, EXq } },	9841 {

8058 { "(bad)",» » { XX } },	9842 /* VEX_W_0F3821_P_2 */

8059 },	9843 { "vpmovsxbd",» { XM, EXxmmqd } },

8060	9844 },

8061 /* VEX_LEN_3821_P_2 */	9845 {

8062 {	9846 /* VEX_W_0F3822_P_2 */

8063 { "vpmovsxbd",» { XM, EXd } },	9847 { "vpmovsxbq",» { XM, EXxmmdw } },

8064 { "(bad)",» » { XX } },	9848 },

8065 },	9849 {

8066	9850 /* VEX_W_0F3823_P_2 */

8067 /* VEX_LEN_3822_P_2 */	9851 { "vpmovsxwd",» { XM, EXxmmq } },

8068 {	9852 },

8069 { "vpmovsxbq",» { XM, EXw } },	9853 {

8070 { "(bad)",» » { XX } },	9854 /* VEX_W_0F3824_P_2 */

8071 },	9855 { "vpmovsxwq",» { XM, EXxmmqd } },

8072	9856 },

8073 /* VEX_LEN_3823_P_2 */	9857 {

8074 {	9858 /* VEX_W_0F3825_P_2 */

8075 { "vpmovsxwd",» { XM, EXq } },	9859 { "vpmovsxdq",» { XM, EXxmmq } },

8076 { "(bad)",» » { XX } },	9860 },

8077 },	9861 {

8078	9862 /* VEX_W_0F3828_P_2 */

8079 /* VEX_LEN_3824_P_2 */	9863 { "vpmuldq",» { XM, Vex, EXx } },

8080 {	9864 },

8081 { "vpmovsxwq",» { XM, EXd } },	9865 {

8082 { "(bad)",» » { XX } },	9866 /* VEX_W_0F3829_P_2 */

8083 },	9867 { "vpcmpeqq",» { XM, Vex, EXx } },

8084	9868 },

8085 /* VEX_LEN_3825_P_2 */	9869 {

8086 {	9870 /* VEX_W_0F382A_P_2_M_0 */

8087 { "vpmovsxdq",» { XM, EXq } },

8088 { "(bad)",» » { XX } },

8089 },

8090

8091 /* VEX_LEN_3828_P_2 */

8092 {

8093 { "vpmuldq",» { XM, Vex128, EXx } },

8094 { "(bad)",» » { XX } },

8095 },

8096

8097 /* VEX_LEN_3829_P_2 */

8098 {

8099 { "vpcmpeqq",» { XM, Vex128, EXx } },

8100 { "(bad)",» » { XX } },

8101 },

8102

8103 /* VEX_LEN_382A_P_2_M_0 */

8104 {

8105 { "vmovntdqa", { XM, Mx } },	9871 { "vmovntdqa", { XM, Mx } },

8106 { "(bad)",» » { XX } },	9872 },

8107 },	9873 {

8108	9874 /* VEX_W_0F382B_P_2 */

8109 /* VEX_LEN_382B_P_2 */	9875 { "vpackusdw",» { XM, Vex, EXx } },

8110 {	9876 },

8111 { "vpackusdw",» { XM, Vex128, EXx } },	9877 {

8112 { "(bad)",» » { XX } },	9878 /* VEX_W_0F382C_P_2_M_0 */

8113 },	9879 { "vmaskmovps",» { XM, Vex, Mx } },

8114	9880 },

8115 /* VEX_LEN_3830_P_2 */	9881 {

8116 {	9882 /* VEX_W_0F382D_P_2_M_0 */

8117 { "vpmovzxbw",» { XM, EXq } },	9883 { "vmaskmovpd",» { XM, Vex, Mx } },

8118 { "(bad)",» » { XX } },	9884 },

8119 },	9885 {

8120	9886 /* VEX_W_0F382E_P_2_M_0 */

8121 /* VEX_LEN_3831_P_2 */	9887 { "vmaskmovps",» { Mx, Vex, XM } },

8122 {	9888 },

8123 { "vpmovzxbd",» { XM, EXd } },	9889 {

8124 { "(bad)",» » { XX } },	9890 /* VEX_W_0F382F_P_2_M_0 */

8125 },	9891 { "vmaskmovpd",» { Mx, Vex, XM } },

8126	9892 },

8127 /* VEX_LEN_3832_P_2 */	9893 {

8128 {	9894 /* VEX_W_0F3830_P_2 */

8129 { "vpmovzxbq",» { XM, EXw } },	9895 { "vpmovzxbw",» { XM, EXxmmq } },

8130 { "(bad)",» » { XX } },	9896 },

8131 },	9897 {

8132	9898 /* VEX_W_0F3831_P_2 */

8133 /* VEX_LEN_3833_P_2 */	9899 { "vpmovzxbd",» { XM, EXxmmqd } },

8134 {	9900 },

8135 { "vpmovzxwd",» { XM, EXq } },	9901 {

8136 { "(bad)",» » { XX } },	9902 /* VEX_W_0F3832_P_2 */

8137 },	9903 { "vpmovzxbq",» { XM, EXxmmdw } },

8138	9904 },

8139 /* VEX_LEN_3834_P_2 */	9905 {

8140 {	9906 /* VEX_W_0F3833_P_2 */

8141 { "vpmovzxwq",» { XM, EXd } },	9907 { "vpmovzxwd",» { XM, EXxmmq } },

8142 { "(bad)",» » { XX } },	9908 },

8143 },	9909 {

8144	9910 /* VEX_W_0F3834_P_2 */

8145 /* VEX_LEN_3835_P_2 */	9911 { "vpmovzxwq",» { XM, EXxmmqd } },

8146 {	9912 },

8147 { "vpmovzxdq",» { XM, EXq } },	9913 {

8148 { "(bad)",» » { XX } },	9914 /* VEX_W_0F3835_P_2 */

8149 },	9915 { "vpmovzxdq",» { XM, EXxmmq } },

8150	9916 },

8151 /* VEX_LEN_3837_P_2 */	9917 {

8152 {	9918 /* VEX_W_0F3836_P_2 */

8153 { "vpcmpgtq",» { XM, Vex128, EXx } },	9919 { "vpermd",»» { XM, Vex, EXx } },

8154 { "(bad)",» » { XX } },	9920 },

8155 },	9921 {

8156	9922 /* VEX_W_0F3837_P_2 */

8157 /* VEX_LEN_3838_P_2 */	9923 { "vpcmpgtq",» { XM, Vex, EXx } },

8158 {	9924 },

8159 { "vpminsb",» { XM, Vex128, EXx } },	9925 {

8160 { "(bad)",» » { XX } },	9926 /* VEX_W_0F3838_P_2 */

8161 },	9927 { "vpminsb",» { XM, Vex, EXx } },

8162	9928 },

8163 /* VEX_LEN_3839_P_2 */	9929 {

8164 {	9930 /* VEX_W_0F3839_P_2 */

8165 { "vpminsd",» { XM, Vex128, EXx } },	9931 { "vpminsd",» { XM, Vex, EXx } },

8166 { "(bad)",» » { XX } },	9932 },

8167 },	9933 {

8168	9934 /* VEX_W_0F383A_P_2 */

8169 /* VEX_LEN_383A_P_2 */	9935 { "vpminuw",» { XM, Vex, EXx } },

8170 {	9936 },

8171 { "vpminuw",» { XM, Vex128, EXx } },	9937 {

8172 { "(bad)",» » { XX } },	9938 /* VEX_W_0F383B_P_2 */

8173 },	9939 { "vpminud",» { XM, Vex, EXx } },

8174	9940 },

8175 /* VEX_LEN_383B_P_2 */	9941 {

8176 {	9942 /* VEX_W_0F383C_P_2 */

8177 { "vpminud",» { XM, Vex128, EXx } },	9943 { "vpmaxsb",» { XM, Vex, EXx } },

8178 { "(bad)",» » { XX } },	9944 },

8179 },	9945 {

8180	9946 /* VEX_W_0F383D_P_2 */

8181 /* VEX_LEN_383C_P_2 */	9947 { "vpmaxsd",» { XM, Vex, EXx } },

8182 {	9948 },

8183 { "vpmaxsb",» { XM, Vex128, EXx } },	9949 {

8184 { "(bad)",» » { XX } },	9950 /* VEX_W_0F383E_P_2 */

8185 },	9951 { "vpmaxuw",» { XM, Vex, EXx } },

8186	9952 },

8187 /* VEX_LEN_383D_P_2 */	9953 {

8188 {	9954 /* VEX_W_0F383F_P_2 */

8189 { "vpmaxsd",» { XM, Vex128, EXx } },	9955 { "vpmaxud",» { XM, Vex, EXx } },

8190 { "(bad)",» » { XX } },	9956 },

8191 },	9957 {

8192	9958 /* VEX_W_0F3840_P_2 */

8193 /* VEX_LEN_383E_P_2 */	9959 { "vpmulld",» { XM, Vex, EXx } },

8194 {	9960 },

8195 { "vpmaxuw",» { XM, Vex128, EXx } },	9961 {

8196 { "(bad)",» » { XX } },	9962 /* VEX_W_0F3841_P_2 */

8197 },

8198

8199 /* VEX_LEN_383F_P_2 */

8200 {

8201 { "vpmaxud",» { XM, Vex128, EXx } },

8202 { "(bad)",» » { XX } },

8203 },

8204

8205 /* VEX_LEN_3840_P_2 */

8206 {

8207 { "vpmulld",» { XM, Vex128, EXx } },

8208 { "(bad)",» » { XX } },

8209 },

8210

8211 /* VEX_LEN_3841_P_2 */

8212 {

8213 { "vphminposuw", { XM, EXx } },	9963 { "vphminposuw", { XM, EXx } },

8214 { "(bad)",» » { XX } },	9964 },

8215 },	9965 {

8216	9966 /* VEX_W_0F3846_P_2 */

8217 /* VEX_LEN_38DB_P_2 */	9967 { "vpsravd",» { XM, Vex, EXx } },

8218 {	9968 },

	9969 {

	9970 /* VEX_W_0F3858_P_2 */

	9971 { "vpbroadcastd", { XM, EXxmm_md } },

	9972 },

	9973 {

	9974 /* VEX_W_0F3859_P_2 */

	9975 { "vpbroadcastq",» { XM, EXxmm_mq } },

	9976 },

	9977 {

	9978 /* VEX_W_0F385A_P_2_M_0 */

	9979 { "vbroadcasti128", { XM, Mxmm } },

	9980 },

	9981 {

	9982 /* VEX_W_0F3878_P_2 */

	9983 { "vpbroadcastb",» { XM, EXxmm_mb } },

	9984 },

	9985 {

	9986 /* VEX_W_0F3879_P_2 */

	9987 { "vpbroadcastw",» { XM, EXxmm_mw } },

	9988 },

	9989 {

	9990 /* VEX_W_0F38DB_P_2 */

8219 { "vaesimc", { XM, EXx } },	9991 { "vaesimc", { XM, EXx } },

8220 { "(bad)",» » { XX } },	9992 },

8221 },	9993 {

8222	9994 /* VEX_W_0F38DC_P_2 */

8223 /* VEX_LEN_38DC_P_2 */

8224 {

8225 { "vaesenc", { XM, Vex128, EXx } },	9995 { "vaesenc", { XM, Vex128, EXx } },

8226 { "(bad)",» » { XX } },	9996 },

8227 },	9997 {

8228	9998 /* VEX_W_0F38DD_P_2 */

8229 /* VEX_LEN_38DD_P_2 */

8230 {

8231 { "vaesenclast", { XM, Vex128, EXx } },	9999 { "vaesenclast", { XM, Vex128, EXx } },

8232 { "(bad)",» » { XX } },	10000 },

8233 },	10001 {

8234	10002 /* VEX_W_0F38DE_P_2 */

8235 /* VEX_LEN_38DE_P_2 */

8236 {

8237 { "vaesdec", { XM, Vex128, EXx } },	10003 { "vaesdec", { XM, Vex128, EXx } },

8238 { "(bad)",» » { XX } },	10004 },

8239 },	10005 {

8240	10006 /* VEX_W_0F38DF_P_2 */

8241 /* VEX_LEN_38DF_P_2 */

8242 {

8243 { "vaesdeclast", { XM, Vex128, EXx } },	10007 { "vaesdeclast", { XM, Vex128, EXx } },

8244 { "(bad)",» » { XX } },	10008 },

8245 },	10009 {

8246	10010 /* VEX_W_0F3A00_P_2 */

8247 /* VEX_LEN_3A06_P_2 */	10011 { Bad_Opcode },

8248 {	10012 { "vpermq",»» { XM, EXx, Ib } },

8249 { "(bad)",» » { XX } },	10013 },

	10014 {

	10015 /* VEX_W_0F3A01_P_2 */

	10016 { Bad_Opcode },

	10017 { "vpermpd",» { XM, EXx, Ib } },

	10018 },

	10019 {

	10020 /* VEX_W_0F3A02_P_2 */

	10021 { "vpblendd",» { XM, Vex, EXx, Ib } },

	10022 },

	10023 {

	10024 /* VEX_W_0F3A04_P_2 */

	10025 { "vpermilps",» { XM, EXx, Ib } },

	10026 },

	10027 {

	10028 /* VEX_W_0F3A05_P_2 */

	10029 { "vpermilpd",» { XM, EXx, Ib } },

	10030 },

	10031 {

	10032 /* VEX_W_0F3A06_P_2 */

8250 { "vperm2f128", { XM, Vex256, EXx, Ib } },	10033 { "vperm2f128", { XM, Vex256, EXx, Ib } },

8251 },	10034 },

8252	10035 {

8253 /* VEX_LEN_3A0A_P_2 */	10036 /* VEX_W_0F3A08_P_2 */

8254 {	10037 { "vroundps",» { XM, EXx, Ib } },

8255 { "vroundss",» { XM, Vex128, EXd, Ib } },	10038 },

8256 { "(bad)",» » { XX } },	10039 {

8257 },	10040 /* VEX_W_0F3A09_P_2 */

8258	10041 { "vroundpd",» { XM, EXx, Ib } },

8259 /* VEX_LEN_3A0B_P_2 */	10042 },

8260 {	10043 {

8261 { "vroundsd",» { XM, Vex128, EXq, Ib } },	10044 /* VEX_W_0F3A0A_P_2 */

8262 { "(bad)",» » { XX } },	10045 { "vroundss",» { XMScalar, VexScalar, EXdScalar, Ib } },

8263 },	10046 },

8264	10047 {

8265 /* VEX_LEN_3A0E_P_2 */	10048 /* VEX_W_0F3A0B_P_2 */

8266 {	10049 { "vroundsd",» { XMScalar, VexScalar, EXqScalar, Ib } },

8267 { "vpblendw",» { XM, Vex128, EXx, Ib } },	10050 },

8268 { "(bad)",» » { XX } },	10051 {

8269 },	10052 /* VEX_W_0F3A0C_P_2 */

8270	10053 { "vblendps",» { XM, Vex, EXx, Ib } },

8271 /* VEX_LEN_3A0F_P_2 */	10054 },

8272 {	10055 {

8273 { "vpalignr",» { XM, Vex128, EXx, Ib } },	10056 /* VEX_W_0F3A0D_P_2 */

8274 { "(bad)",» » { XX } },	10057 { "vblendpd",» { XM, Vex, EXx, Ib } },

8275 },	10058 },

8276	10059 {

8277 /* VEX_LEN_3A14_P_2 */	10060 /* VEX_W_0F3A0E_P_2 */

8278 {	10061 { "vpblendw",» { XM, Vex, EXx, Ib } },

	10062 },

	10063 {

	10064 /* VEX_W_0F3A0F_P_2 */

	10065 { "vpalignr",» { XM, Vex, EXx, Ib } },

	10066 },

	10067 {

	10068 /* VEX_W_0F3A14_P_2 */

8279 { "vpextrb", { Edqb, XM, Ib } },	10069 { "vpextrb", { Edqb, XM, Ib } },

8280 { "(bad)",» » { XX } },	10070 },

8281 },	10071 {

8282	10072 /* VEX_W_0F3A15_P_2 */

8283 /* VEX_LEN_3A15_P_2 */

8284 {

8285 { "vpextrw", { Edqw, XM, Ib } },	10073 { "vpextrw", { Edqw, XM, Ib } },

8286 { "(bad)",» » { XX } },	10074 },

8287 },	10075 {

8288	10076 /* VEX_W_0F3A18_P_2 */

8289 /* VEX_LEN_3A16_P_2 */

8290 {

8291 { "vpextrK",» { Edq, XM, Ib } },

8292 { "(bad)",» » { XX } },

8293 },

8294

8295 /* VEX_LEN_3A17_P_2 */

8296 {

8297 { "vextractps",» { Edqd, XM, Ib } },

8298 { "(bad)",» » { XX } },

8299 },

8300

8301 /* VEX_LEN_3A18_P_2 */

8302 {

8303 { "(bad)",» » { XX } },

8304 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },	10077 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },

8305 },	10078 },

8306	10079 {

8307 /* VEX_LEN_3A19_P_2 */	10080 /* VEX_W_0F3A19_P_2 */

8308 {

8309 { "(bad)",» » { XX } },

8310 { "vextractf128", { EXxmm, XM, Ib } },	10081 { "vextractf128", { EXxmm, XM, Ib } },

8311 },	10082 },

8312	10083 {

8313 /* VEX_LEN_3A20_P_2 */	10084 /* VEX_W_0F3A20_P_2 */

8314 {

8315 { "vpinsrb", { XM, Vex128, Edqb, Ib } },	10085 { "vpinsrb", { XM, Vex128, Edqb, Ib } },

8316 { "(bad)",» » { XX } },	10086 },

8317 },	10087 {

8318	10088 /* VEX_W_0F3A21_P_2 */

8319 /* VEX_LEN_3A21_P_2 */

8320 {

8321 { "vinsertps", { XM, Vex128, EXd, Ib } },	10089 { "vinsertps", { XM, Vex128, EXd, Ib } },

8322 { "(bad)",» » { XX } },	10090 },

8323 },	10091 {

8324	10092 /* VEX_W_0F3A38_P_2 */

8325 /* VEX_LEN_3A22_P_2 */	10093 { "vinserti128",» { XM, Vex256, EXxmm, Ib } },

8326 {	10094 },

8327 { "vpinsrK",» { XM, Vex128, Edq, Ib } },	10095 {

8328 { "(bad)",» » { XX } },	10096 /* VEX_W_0F3A39_P_2 */

8329 },	10097 { "vextracti128",» { EXxmm, XM, Ib } },

8330	10098 },

8331 /* VEX_LEN_3A41_P_2 */	10099 {

8332 {	10100 /* VEX_W_0F3A40_P_2 */

	10101 { "vdpps",» » { XM, Vex, EXx, Ib } },

	10102 },

	10103 {

	10104 /* VEX_W_0F3A41_P_2 */

8333 { "vdppd", { XM, Vex128, EXx, Ib } },	10105 { "vdppd", { XM, Vex128, EXx, Ib } },

8334 { "(bad)",» » { XX } },	10106 },

8335 },	10107 {

8336	10108 /* VEX_W_0F3A42_P_2 */

8337 /* VEX_LEN_3A42_P_2 */	10109 { "vmpsadbw",» { XM, Vex, EXx, Ib } },

8338 {	10110 },

8339 { "vmpsadbw",» { XM, Vex128, EXx, Ib } },	10111 {

8340 { "(bad)",» » { XX } },	10112 /* VEX_W_0F3A44_P_2 */

8341 },

8342

8343 /* VEX_LEN_3A44_P_2 */

8344 {

8345 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },	10113 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },

8346 { "(bad)",» » { XX } },	10114 },

8347 },	10115 {

8348	10116 /* VEX_W_0F3A46_P_2 */

8349 /* VEX_LEN_3A4C_P_2 */	10117 { "vperm2i128",» { XM, Vex256, EXx, Ib } },

8350 {	10118 },

8351 { "vpblendvb",» { XM, Vex128, EXx, XMVexI4 } },	10119 {

8352 { "(bad)",» » { XX } },	10120 /* VEX_W_0F3A48_P_2 */

8353 },	10121 { "vpermil2ps",» { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },

8354	10122 { "vpermil2ps",» { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },

8355 /* VEX_LEN_3A60_P_2 */	10123 },

8356 {	10124 {

	10125 /* VEX_W_0F3A49_P_2 */

	10126 { "vpermil2pd",» { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },

	10127 { "vpermil2pd",» { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },

	10128 },

	10129 {

	10130 /* VEX_W_0F3A4A_P_2 */

	10131 { "vblendvps",» { XM, Vex, EXx, XMVexI4 } },

	10132 },

	10133 {

	10134 /* VEX_W_0F3A4B_P_2 */

	10135 { "vblendvpd",» { XM, Vex, EXx, XMVexI4 } },

	10136 },

	10137 {

	10138 /* VEX_W_0F3A4C_P_2 */

	10139 { "vpblendvb",» { XM, Vex, EXx, XMVexI4 } },

	10140 },

	10141 {

	10142 /* VEX_W_0F3A60_P_2 */

8357 { "vpcmpestrm", { XM, EXx, Ib } },	10143 { "vpcmpestrm", { XM, EXx, Ib } },

8358 { "(bad)",» » { XX } },	10144 },

8359 },	10145 {

8360	10146 /* VEX_W_0F3A61_P_2 */

8361 /* VEX_LEN_3A61_P_2 */

8362 {

8363 { "vpcmpestri", { XM, EXx, Ib } },	10147 { "vpcmpestri", { XM, EXx, Ib } },

8364 { "(bad)",» » { XX } },	10148 },

8365 },	10149 {

8366	10150 /* VEX_W_0F3A62_P_2 */

8367 /* VEX_LEN_3A62_P_2 */

8368 {

8369 { "vpcmpistrm", { XM, EXx, Ib } },	10151 { "vpcmpistrm", { XM, EXx, Ib } },

8370 { "(bad)",» » { XX } },	10152 },

8371 },	10153 {

8372	10154 /* VEX_W_0F3A63_P_2 */

8373 /* VEX_LEN_3A63_P_2 */

8374 {

8375 { "vpcmpistri", { XM, EXx, Ib } },	10155 { "vpcmpistri", { XM, EXx, Ib } },

8376 { "(bad)",» » { XX } },	10156 },

8377 },	10157 {

8378	10158 /* VEX_W_0F3ADF_P_2 */

8379 /* VEX_LEN_3A6A_P_2 */

8380 {

8381 { "vfmaddss",» { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },

8382 { "(bad)",» » { XX } },

8383 },

8384

8385 /* VEX_LEN_3A6B_P_2 */

8386 {

8387 { "vfmaddsd",» { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },

8388 { "(bad)",» » { XX } },

8389 },

8390

8391 /* VEX_LEN_3A6E_P_2 */

8392 {

8393 { "vfmsubss",» { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },

8394 { "(bad)",» » { XX } },

8395 },

8396

8397 /* VEX_LEN_3A6F_P_2 */

8398 {

8399 { "vfmsubsd",» { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },

8400 { "(bad)",» » { XX } },

8401 },

8402

8403 /* VEX_LEN_3A7A_P_2 */

8404 {

8405 { "vfnmaddss",» { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },

8406 { "(bad)",» » { XX } },

8407 },

8408

8409 /* VEX_LEN_3A7B_P_2 */

8410 {

8411 { "vfnmaddsd",» { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },

8412 { "(bad)",» » { XX } },

8413 },

8414

8415 /* VEX_LEN_3A7E_P_2 */

8416 {

8417 { "vfnmsubss",» { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },

8418 { "(bad)",» » { XX } },

8419 },

8420

8421 /* VEX_LEN_3A7F_P_2 */

8422 {

8423 { "vfnmsubsd",» { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },

8424 { "(bad)",» » { XX } },

8425 },

8426

8427 /* VEX_LEN_3ADF_P_2 */

8428 {

8429 { "vaeskeygenassist", { XM, EXx, Ib } },	10159 { "vaeskeygenassist", { XM, EXx, Ib } },

8430 { "(bad)", { XX } },

8431 },	10160 },

8432 };	10161 };

8433	10162

8434 static const struct dis386 mod_table[][2] = {	10163 static const struct dis386 mod_table[][2] = {

8435 {	10164 {

8436 /* MOD_8D */	10165 /* MOD_8D */

8437 { "leaS", { Gv, M } },	10166 { "leaS", { Gv, M } },

8438 { "(bad)",» » { XX } },	10167 },

	10168 {

	10169 /* MOD_C6_REG_7 */

	10170 { Bad_Opcode },

	10171 { RM_TABLE (RM_C6_REG_7) },

	10172 },

	10173 {

	10174 /* MOD_C7_REG_7 */

	10175 { Bad_Opcode },

	10176 { RM_TABLE (RM_C7_REG_7) },

8439 },	10177 },

8440 {	10178 {

8441 /* MOD_0F01_REG_0 */	10179 /* MOD_0F01_REG_0 */

8442 { X86_64_TABLE (X86_64_0F01_REG_0) },	10180 { X86_64_TABLE (X86_64_0F01_REG_0) },

8443 { RM_TABLE (RM_0F01_REG_0) },	10181 { RM_TABLE (RM_0F01_REG_0) },

8444 },	10182 },

8445 {	10183 {

8446 /* MOD_0F01_REG_1 */	10184 /* MOD_0F01_REG_1 */

8447 { X86_64_TABLE (X86_64_0F01_REG_1) },	10185 { X86_64_TABLE (X86_64_0F01_REG_1) },

8448 { RM_TABLE (RM_0F01_REG_1) },	10186 { RM_TABLE (RM_0F01_REG_1) },

(...skipping 14 matching lines...) Expand all Loading...
8463 { RM_TABLE (RM_0F01_REG_7) },	10201 { RM_TABLE (RM_0F01_REG_7) },

8464 },	10202 },

8465 {	10203 {

8466 /* MOD_0F12_PREFIX_0 */	10204 /* MOD_0F12_PREFIX_0 */

8467 { "movlps", { XM, EXq } },	10205 { "movlps", { XM, EXq } },

8468 { "movhlps", { XM, EXq } },	10206 { "movhlps", { XM, EXq } },

8469 },	10207 },

8470 {	10208 {

8471 /* MOD_0F13 */	10209 /* MOD_0F13 */

8472 { "movlpX", { EXq, XM } },	10210 { "movlpX", { EXq, XM } },

8473 { "(bad)", { XX } },

8474 },	10211 },

8475 {	10212 {

8476 /* MOD_0F16_PREFIX_0 */	10213 /* MOD_0F16_PREFIX_0 */

8477 { "movhps", { XM, EXq } },	10214 { "movhps", { XM, EXq } },

8478 { "movlhps", { XM, EXq } },	10215 { "movlhps", { XM, EXq } },

8479 },	10216 },

8480 {	10217 {

8481 /* MOD_0F17 */	10218 /* MOD_0F17 */

8482 { "movhpX", { EXq, XM } },	10219 { "movhpX", { EXq, XM } },

8483 { "(bad)", { XX } },

8484 },	10220 },

8485 {	10221 {

8486 /* MOD_0F18_REG_0 */	10222 /* MOD_0F18_REG_0 */

8487 { "prefetchnta", { Mb } },	10223 { "prefetchnta", { Mb } },

8488 { "(bad)", { XX } },

8489 },	10224 },

8490 {	10225 {

8491 /* MOD_0F18_REG_1 */	10226 /* MOD_0F18_REG_1 */

8492 { "prefetcht0", { Mb } },	10227 { "prefetcht0", { Mb } },

8493 { "(bad)", { XX } },

8494 },	10228 },

8495 {	10229 {

8496 /* MOD_0F18_REG_2 */	10230 /* MOD_0F18_REG_2 */

8497 { "prefetcht1", { Mb } },	10231 { "prefetcht1", { Mb } },

8498 { "(bad)", { XX } },

8499 },	10232 },

8500 {	10233 {

8501 /* MOD_0F18_REG_3 */	10234 /* MOD_0F18_REG_3 */

8502 { "prefetcht2", { Mb } },	10235 { "prefetcht2", { Mb } },

8503 { "(bad)",» » { XX } },	10236 },

	10237 {

	10238 /* MOD_0F18_REG_4 */

	10239 { "nop/reserved",» { Mb } },

	10240 },

	10241 {

	10242 /* MOD_0F18_REG_5 */

	10243 { "nop/reserved",» { Mb } },

	10244 },

	10245 {

	10246 /* MOD_0F18_REG_6 */

	10247 { "nop/reserved",» { Mb } },

	10248 },

	10249 {

	10250 /* MOD_0F18_REG_7 */

	10251 { "nop/reserved",» { Mb } },

8504 },	10252 },

8505 {	10253 {

8506 /* MOD_0F20 */	10254 /* MOD_0F20 */

8507 { "(bad)",» » { XX } },	10255 { Bad_Opcode },

8508 { "movZ", { Rm, Cm } },	10256 { "movZ", { Rm, Cm } },

8509 },	10257 },

8510 {	10258 {

8511 /* MOD_0F21 */	10259 /* MOD_0F21 */

8512 { "(bad)",» » { XX } },	10260 { Bad_Opcode },

8513 { "movZ", { Rm, Dm } },	10261 { "movZ", { Rm, Dm } },

8514 },	10262 },

8515 {	10263 {

8516 /* MOD_0F22 */	10264 /* MOD_0F22 */

8517 { "(bad)",» » { XX } },	10265 { Bad_Opcode },

8518 { "movZ", { Cm, Rm } },	10266 { "movZ", { Cm, Rm } },

8519 },	10267 },

8520 {	10268 {

8521 /* MOD_0F23 */	10269 /* MOD_0F23 */

8522 { "(bad)",» » { XX } },	10270 { Bad_Opcode },

8523 { "movZ", { Dm, Rm } },	10271 { "movZ", { Dm, Rm } },

8524 },	10272 },

8525 {	10273 {

8526 /* MOD_0F24 */	10274 /* MOD_0F24 */

8527 { "(bad)",» » { XX } },	10275 { Bad_Opcode },

8528 { "movL", { Rd, Td } },	10276 { "movL", { Rd, Td } },

8529 },	10277 },

8530 {	10278 {

8531 /* MOD_0F26 */	10279 /* MOD_0F26 */

8532 { "(bad)",» » { XX } },	10280 { Bad_Opcode },

8533 { "movL", { Td, Rd } },	10281 { "movL", { Td, Rd } },

8534 },	10282 },

8535 {	10283 {

8536 /* MOD_0F2B_PREFIX_0 */	10284 /* MOD_0F2B_PREFIX_0 */

8537 {"movntps", { Mx, XM } },	10285 {"movntps", { Mx, XM } },

8538 { "(bad)", { XX } },

8539 },	10286 },

8540 {	10287 {

8541 /* MOD_0F2B_PREFIX_1 */	10288 /* MOD_0F2B_PREFIX_1 */

8542 {"movntss", { Md, XM } },	10289 {"movntss", { Md, XM } },

8543 { "(bad)", { XX } },

8544 },	10290 },

8545 {	10291 {

8546 /* MOD_0F2B_PREFIX_2 */	10292 /* MOD_0F2B_PREFIX_2 */

8547 {"movntpd", { Mx, XM } },	10293 {"movntpd", { Mx, XM } },

8548 { "(bad)", { XX } },

8549 },	10294 },

8550 {	10295 {

8551 /* MOD_0F2B_PREFIX_3 */	10296 /* MOD_0F2B_PREFIX_3 */

8552 {"movntsd", { Mq, XM } },	10297 {"movntsd", { Mq, XM } },

8553 { "(bad)", { XX } },

8554 },	10298 },

8555 {	10299 {

8556 /* MOD_0F51 */	10300 /* MOD_0F51 */

8557 { "(bad)",» » { XX } },	10301 { Bad_Opcode },

8558 { "movmskpX", { Gdq, XS } },	10302 { "movmskpX", { Gdq, XS } },

8559 },	10303 },

8560 {	10304 {

8561 /* MOD_0F71_REG_2 */	10305 /* MOD_0F71_REG_2 */

8562 { "(bad)",» » { XX } },	10306 { Bad_Opcode },

8563 { "psrlw", { MS, Ib } },	10307 { "psrlw", { MS, Ib } },

8564 },	10308 },

8565 {	10309 {

8566 /* MOD_0F71_REG_4 */	10310 /* MOD_0F71_REG_4 */

8567 { "(bad)",» » { XX } },	10311 { Bad_Opcode },

8568 { "psraw", { MS, Ib } },	10312 { "psraw", { MS, Ib } },

8569 },	10313 },

8570 {	10314 {

8571 /* MOD_0F71_REG_6 */	10315 /* MOD_0F71_REG_6 */

8572 { "(bad)",» » { XX } },	10316 { Bad_Opcode },

8573 { "psllw", { MS, Ib } },	10317 { "psllw", { MS, Ib } },

8574 },	10318 },

8575 {	10319 {

8576 /* MOD_0F72_REG_2 */	10320 /* MOD_0F72_REG_2 */

8577 { "(bad)",» » { XX } },	10321 { Bad_Opcode },

8578 { "psrld", { MS, Ib } },	10322 { "psrld", { MS, Ib } },

8579 },	10323 },

8580 {	10324 {

8581 /* MOD_0F72_REG_4 */	10325 /* MOD_0F72_REG_4 */

8582 { "(bad)",» » { XX } },	10326 { Bad_Opcode },

8583 { "psrad", { MS, Ib } },	10327 { "psrad", { MS, Ib } },

8584 },	10328 },

8585 {	10329 {

8586 /* MOD_0F72_REG_6 */	10330 /* MOD_0F72_REG_6 */

8587 { "(bad)",» » { XX } },	10331 { Bad_Opcode },

8588 { "pslld", { MS, Ib } },	10332 { "pslld", { MS, Ib } },

8589 },	10333 },

8590 {	10334 {

8591 /* MOD_0F73_REG_2 */	10335 /* MOD_0F73_REG_2 */

8592 { "(bad)",» » { XX } },	10336 { Bad_Opcode },

8593 { "psrlq", { MS, Ib } },	10337 { "psrlq", { MS, Ib } },

8594 },	10338 },

8595 {	10339 {

8596 /* MOD_0F73_REG_3 */	10340 /* MOD_0F73_REG_3 */

8597 { "(bad)",» » { XX } },	10341 { Bad_Opcode },

8598 { PREFIX_TABLE (PREFIX_0F73_REG_3) },	10342 { PREFIX_TABLE (PREFIX_0F73_REG_3) },

8599 },	10343 },

8600 {	10344 {

8601 /* MOD_0F73_REG_6 */	10345 /* MOD_0F73_REG_6 */

8602 { "(bad)",» » { XX } },	10346 { Bad_Opcode },

8603 { "psllq", { MS, Ib } },	10347 { "psllq", { MS, Ib } },

8604 },	10348 },

8605 {	10349 {

8606 /* MOD_0F73_REG_7 */	10350 /* MOD_0F73_REG_7 */

8607 { "(bad)",» » { XX } },	10351 { Bad_Opcode },

8608 { PREFIX_TABLE (PREFIX_0F73_REG_7) },	10352 { PREFIX_TABLE (PREFIX_0F73_REG_7) },

8609 },	10353 },

8610 {	10354 {

8611 /* MOD_0FAE_REG_0 */	10355 /* MOD_0FAE_REG_0 */

8612 { "fxsave",»» { M } },	10356 { "fxsave",»» { FXSAVE } },

8613 { "(bad)",» » { XX } },	10357 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },

8614 },	10358 },

8615 {	10359 {

8616 /* MOD_0FAE_REG_1 */	10360 /* MOD_0FAE_REG_1 */

8617 { "fxrstor",» { M } },	10361 { "fxrstor",» { FXSAVE } },

8618 { "(bad)",» » { XX } },	10362 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },

8619 },	10363 },

8620 {	10364 {

8621 /* MOD_0FAE_REG_2 */	10365 /* MOD_0FAE_REG_2 */

8622 { "ldmxcsr", { Md } },	10366 { "ldmxcsr", { Md } },

8623 { "(bad)",» » { XX } },	10367 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },

8624 },	10368 },

8625 {	10369 {

8626 /* MOD_0FAE_REG_3 */	10370 /* MOD_0FAE_REG_3 */

8627 { "stmxcsr", { Md } },	10371 { "stmxcsr", { Md } },

8628 { "(bad)",» » { XX } },	10372 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },

8629 },	10373 },

8630 {	10374 {

8631 /* MOD_0FAE_REG_4 */	10375 /* MOD_0FAE_REG_4 */

8632 { "xsave",» » { M } },	10376 { "xsave",» » { FXSAVE } },

8633 { "(bad)",» » { XX } },

8634 },	10377 },

8635 {	10378 {

8636 /* MOD_0FAE_REG_5 */	10379 /* MOD_0FAE_REG_5 */

8637 { "xrstor",»» { M } },	10380 { "xrstor",»» { FXSAVE } },

8638 { RM_TABLE (RM_0FAE_REG_5) },	10381 { RM_TABLE (RM_0FAE_REG_5) },

8639 },	10382 },

8640 {	10383 {

8641 /* MOD_0FAE_REG_6 */	10384 /* MOD_0FAE_REG_6 */

8642 { "xsaveopt",» { M } },	10385 { "xsaveopt",» { FXSAVE } },

8643 { RM_TABLE (RM_0FAE_REG_6) },	10386 { RM_TABLE (RM_0FAE_REG_6) },

8644 },	10387 },

8645 {	10388 {

8646 /* MOD_0FAE_REG_7 */	10389 /* MOD_0FAE_REG_7 */

8647 { "clflush", { Mb } },	10390 { "clflush", { Mb } },

8648 { RM_TABLE (RM_0FAE_REG_7) },	10391 { RM_TABLE (RM_0FAE_REG_7) },

8649 },	10392 },

8650 {	10393 {

8651 /* MOD_0FB2 */	10394 /* MOD_0FB2 */

8652 { "lssS", { Gv, Mp } },	10395 { "lssS", { Gv, Mp } },

8653 { "(bad)", { XX } },

8654 },	10396 },

8655 {	10397 {

8656 /* MOD_0FB4 */	10398 /* MOD_0FB4 */

8657 { "lfsS", { Gv, Mp } },	10399 { "lfsS", { Gv, Mp } },

8658 { "(bad)", { XX } },

8659 },	10400 },

8660 {	10401 {

8661 /* MOD_0FB5 */	10402 /* MOD_0FB5 */

8662 { "lgsS", { Gv, Mp } },	10403 { "lgsS", { Gv, Mp } },

8663 { "(bad)", { XX } },

8664 },	10404 },

8665 {	10405 {

8666 /* MOD_0FC7_REG_6 */	10406 /* MOD_0FC7_REG_6 */

8667 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },	10407 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },

8668 { "(bad)",» » { XX } },	10408 { "rdrand",»» { Ev } },

8669 },	10409 },

8670 {	10410 {

8671 /* MOD_0FC7_REG_7 */	10411 /* MOD_0FC7_REG_7 */

8672 { "vmptrst", { Mq } },	10412 { "vmptrst", { Mq } },

8673 { "(bad)",» » { XX } },	10413 { "rdseed",»» { Ev } },

8674 },	10414 },

8675 {	10415 {

8676 /* MOD_0FD7 */	10416 /* MOD_0FD7 */

8677 { "(bad)",» » { XX } },	10417 { Bad_Opcode },

8678 { "pmovmskb", { Gdq, MS } },	10418 { "pmovmskb", { Gdq, MS } },

8679 },	10419 },

8680 {	10420 {

8681 /* MOD_0FE7_PREFIX_2 */	10421 /* MOD_0FE7_PREFIX_2 */

8682 { "movntdq", { Mx, XM } },	10422 { "movntdq", { Mx, XM } },

8683 { "(bad)", { XX } },

8684 },	10423 },

8685 {	10424 {

8686 /* MOD_0FF0_PREFIX_3 */	10425 /* MOD_0FF0_PREFIX_3 */

8687 { "lddqu", { XM, M } },	10426 { "lddqu", { XM, M } },

8688 { "(bad)", { XX } },

8689 },	10427 },

8690 {	10428 {

8691 /* MOD_0F382A_PREFIX_2 */	10429 /* MOD_0F382A_PREFIX_2 */

8692 { "movntdqa", { XM, Mx } },	10430 { "movntdqa", { XM, Mx } },

8693 { "(bad)", { XX } },

8694 },	10431 },

8695 {	10432 {

8696 /* MOD_62_32BIT */	10433 /* MOD_62_32BIT */

8697 { "bound{S\|}", { Gv, Ma } },	10434 { "bound{S\|}", { Gv, Ma } },

8698 { "(bad)", { XX } },

8699 },	10435 },

8700 {	10436 {

8701 /* MOD_C4_32BIT */	10437 /* MOD_C4_32BIT */

8702 { "lesS", { Gv, Mp } },	10438 { "lesS", { Gv, Mp } },

8703 { VEX_C4_TABLE (VEX_0F) },	10439 { VEX_C4_TABLE (VEX_0F) },

8704 },	10440 },

8705 {	10441 {

8706 /* MOD_C5_32BIT */	10442 /* MOD_C5_32BIT */

8707 { "ldsS", { Gv, Mp } },	10443 { "ldsS", { Gv, Mp } },

8708 { VEX_C5_TABLE (VEX_0F) },	10444 { VEX_C5_TABLE (VEX_0F) },

8709 },	10445 },

8710 {	10446 {

8711 /* MOD_VEX_12_PREFIX_0 */	10447 /* MOD_VEX_0F12_PREFIX_0 */

8712 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },	10448 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },

8713 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },	10449 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },

8714 },	10450 },

8715 {	10451 {

8716 /* MOD_VEX_13 */	10452 /* MOD_VEX_0F13 */

8717 { VEX_LEN_TABLE (VEX_LEN_13_M_0) },	10453 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },

8718 { "(bad)",» » { XX } },

8719 },	10454 },

8720 {	10455 {

8721 /* MOD_VEX_16_PREFIX_0 */	10456 /* MOD_VEX_0F16_PREFIX_0 */

8722 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },	10457 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },

8723 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },	10458 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },

8724 },	10459 },

8725 {	10460 {

8726 /* MOD_VEX_17 */	10461 /* MOD_VEX_0F17 */

8727 { VEX_LEN_TABLE (VEX_LEN_17_M_0) },	10462 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },

8728 { "(bad)",» » { XX } },

8729 },	10463 },

8730 {	10464 {

8731 /* MOD_VEX_2B */	10465 /* MOD_VEX_0F2B */

8732 { "vmovntpX",» { Mx, XM } },	10466 { VEX_W_TABLE (VEX_W_0F2B_M_0) },

8733 { "(bad)",» » { XX } },

8734 },	10467 },

8735 {	10468 {

8736 /* MOD_VEX_51 */	10469 /* MOD_VEX_0F50 */

8737 { "(bad)",» » { XX } },	10470 { Bad_Opcode },

8738 { "vmovmskpX",» { Gdq, XS } },	10471 { VEX_W_TABLE (VEX_W_0F50_M_0) },

8739 },	10472 },

8740 {	10473 {

8741 /* MOD_VEX_71_REG_2 */	10474 /* MOD_VEX_0F71_REG_2 */

8742 { "(bad)",» » { XX } },	10475 { Bad_Opcode },

8743 { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },	10476 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },

8744 },	10477 },

8745 {	10478 {

8746 /* MOD_VEX_71_REG_4 */	10479 /* MOD_VEX_0F71_REG_4 */

8747 { "(bad)",» » { XX } },	10480 { Bad_Opcode },

8748 { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },	10481 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },

8749 },	10482 },

8750 {	10483 {

8751 /* MOD_VEX_71_REG_6 */	10484 /* MOD_VEX_0F71_REG_6 */

8752 { "(bad)",» » { XX } },	10485 { Bad_Opcode },

8753 { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },	10486 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },

8754 },	10487 },

8755 {	10488 {

8756 /* MOD_VEX_72_REG_2 */	10489 /* MOD_VEX_0F72_REG_2 */

8757 { "(bad)",» » { XX } },	10490 { Bad_Opcode },

8758 { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },	10491 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },

8759 },	10492 },

8760 {	10493 {

8761 /* MOD_VEX_72_REG_4 */	10494 /* MOD_VEX_0F72_REG_4 */

8762 { "(bad)",» » { XX } },	10495 { Bad_Opcode },

8763 { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },	10496 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },

8764 },	10497 },

8765 {	10498 {

8766 /* MOD_VEX_72_REG_6 */	10499 /* MOD_VEX_0F72_REG_6 */

8767 { "(bad)",» » { XX } },	10500 { Bad_Opcode },

8768 { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },	10501 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },

8769 },	10502 },

8770 {	10503 {

8771 /* MOD_VEX_73_REG_2 */	10504 /* MOD_VEX_0F73_REG_2 */

8772 { "(bad)",» » { XX } },	10505 { Bad_Opcode },

8773 { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },	10506 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },

8774 },	10507 },

8775 {	10508 {

8776 /* MOD_VEX_73_REG_3 */	10509 /* MOD_VEX_0F73_REG_3 */

8777 { "(bad)",» » { XX } },	10510 { Bad_Opcode },

8778 { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },	10511 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },

8779 },	10512 },

8780 {	10513 {

8781 /* MOD_VEX_73_REG_6 */	10514 /* MOD_VEX_0F73_REG_6 */

8782 { "(bad)",» » { XX } },	10515 { Bad_Opcode },

8783 { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },	10516 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },

8784 },	10517 },

8785 {	10518 {

8786 /* MOD_VEX_73_REG_7 */	10519 /* MOD_VEX_0F73_REG_7 */

8787 { "(bad)",» » { XX } },	10520 { Bad_Opcode },

8788 { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },	10521 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },

8789 },	10522 },

8790 {	10523 {

8791 /* MOD_VEX_AE_REG_2 */	10524 /* MOD_VEX_0FAE_REG_2 */

8792 { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },	10525 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },

8793 { "(bad)",» » { XX } },

8794 },	10526 },

8795 {	10527 {

8796 /* MOD_VEX_AE_REG_3 */	10528 /* MOD_VEX_0FAE_REG_3 */

8797 { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },	10529 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },

8798 { "(bad)",» » { XX } },

8799 },	10530 },

8800 {	10531 {

8801 /* MOD_VEX_D7_PREFIX_2 */	10532 /* MOD_VEX_0FD7_PREFIX_2 */

8802 { "(bad)",» » { XX } },	10533 { Bad_Opcode },

8803 { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },	10534 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },

8804 },	10535 },

8805 {	10536 {

8806 /* MOD_VEX_E7_PREFIX_2 */	10537 /* MOD_VEX_0FE7_PREFIX_2 */

8807 { "vmovntdq",» { Mx, XM } },	10538 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },

8808 { "(bad)",» » { XX } },

8809 },	10539 },

8810 {	10540 {

8811 /* MOD_VEX_F0_PREFIX_3 */	10541 /* MOD_VEX_0FF0_PREFIX_3 */

8812 { "vlddqu",»» { XM, M } },	10542 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },

8813 { "(bad)",» » { XX } },

8814 },	10543 },

8815 {	10544 {

8816 /* MOD_VEX_3818_PREFIX_2 */	10545 /* MOD_VEX_0F381A_PREFIX_2 */

8817 { "vbroadcastss",» { XM, Md } },	10546 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },

8818 { "(bad)",» » { XX } },

8819 },	10547 },

8820 {	10548 {

8821 /* MOD_VEX_3819_PREFIX_2 */	10549 /* MOD_VEX_0F382A_PREFIX_2 */

8822 { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },	10550 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },

8823 { "(bad)",» » { XX } },

8824 },	10551 },

8825 {	10552 {

8826 /* MOD_VEX_381A_PREFIX_2 */	10553 /* MOD_VEX_0F382C_PREFIX_2 */

8827 { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },	10554 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },

8828 { "(bad)",» » { XX } },

8829 },	10555 },

8830 {	10556 {

8831 /* MOD_VEX_382A_PREFIX_2 */	10557 /* MOD_VEX_0F382D_PREFIX_2 */

8832 { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },	10558 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },

8833 { "(bad)",» » { XX } },

8834 },	10559 },

8835 {	10560 {

8836 /* MOD_VEX_382C_PREFIX_2 */	10561 /* MOD_VEX_0F382E_PREFIX_2 */

8837 { "vmaskmovps",» { XM, Vex, Mx } },	10562 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },

8838 { "(bad)",» » { XX } },

8839 },	10563 },

8840 {	10564 {

8841 /* MOD_VEX_382D_PREFIX_2 */	10565 /* MOD_VEX_0F382F_PREFIX_2 */

8842 { "vmaskmovpd",» { XM, Vex, Mx } },	10566 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },

8843 { "(bad)",» » { XX } },

8844 },	10567 },

8845 {	10568 {

8846 /* MOD_VEX_382E_PREFIX_2 */	10569 /* MOD_VEX_0F385A_PREFIX_2 */

8847 { "vmaskmovps",» { Mx, Vex, XM } },	10570 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },

8848 { "(bad)",» » { XX } },

8849 },	10571 },

8850 {	10572 {

8851 /* MOD_VEX_382F_PREFIX_2 */	10573 /* MOD_VEX_0F388C_PREFIX_2 */

8852 { "vmaskmovpd",» { Mx, Vex, XM } },	10574 { "vpmaskmov%LW",» { XM, Vex, Mx } },

8853 { "(bad)",» » { XX } },	10575 },

	10576 {

	10577 /* MOD_VEX_0F388E_PREFIX_2 */

	10578 { "vpmaskmov%LW",» { Mx, Vex, XM } },

8854 },	10579 },

8855 };	10580 };

8856	10581

8857 static const struct dis386 rm_table[][8] = {	10582 static const struct dis386 rm_table[][8] = {

8858 {	10583 {

	10584 /* RM_C6_REG_7 */

	10585 { "xabort", { Skip_MODRM, Ib } },

	10586 },

	10587 {

	10588 /* RM_C7_REG_7 */

	10589 { "xbeginT", { Skip_MODRM, Jv } },

	10590 },

	10591 {

8859 /* RM_0F01_REG_0 */	10592 /* RM_0F01_REG_0 */

8860 { "(bad)",» » { XX } },	10593 { Bad_Opcode },

8861 { "vmcall", { Skip_MODRM } },	10594 { "vmcall", { Skip_MODRM } },

8862 { "vmlaunch", { Skip_MODRM } },	10595 { "vmlaunch", { Skip_MODRM } },

8863 { "vmresume", { Skip_MODRM } },	10596 { "vmresume", { Skip_MODRM } },

8864 { "vmxoff", { Skip_MODRM } },	10597 { "vmxoff", { Skip_MODRM } },

8865 { "(bad)", { XX } },

8866 { "(bad)", { XX } },

8867 { "(bad)", { XX } },

8868 },	10598 },

8869 {	10599 {

8870 /* RM_0F01_REG_1 */	10600 /* RM_0F01_REG_1 */

8871 { "monitor", { { OP_Monitor, 0 } } },	10601 { "monitor", { { OP_Monitor, 0 } } },

8872 { "mwait", { { OP_Mwait, 0 } } },	10602 { "mwait", { { OP_Mwait, 0 } } },

8873 { "(bad)",» » { XX } },	10603 { "clac",» » { Skip_MODRM } },

8874 { "(bad)",» » { XX } },	10604 { "stac",» » { Skip_MODRM } },

8875 { "(bad)",» » { XX } },

8876 { "(bad)",» » { XX } },

8877 { "(bad)",» » { XX } },

8878 { "(bad)",» » { XX } },

8879 },	10605 },

8880 {	10606 {

8881 /* RM_0F01_REG_2 */	10607 /* RM_0F01_REG_2 */

8882 { "xgetbv", { Skip_MODRM } },	10608 { "xgetbv", { Skip_MODRM } },

8883 { "xsetbv", { Skip_MODRM } },	10609 { "xsetbv", { Skip_MODRM } },

8884 { "(bad)",» » { XX } },	10610 { Bad_Opcode },

8885 { "(bad)",» » { XX } },	10611 { Bad_Opcode },

8886 { "(bad)",» » { XX } },	10612 { "vmfunc",»» { Skip_MODRM } },

8887 { "(bad)",» » { XX } },	10613 { "xend",» » { Skip_MODRM } },

8888 { "(bad)",» » { XX } },	10614 { "xtest",» » { Skip_MODRM } },

8889 { "(bad)",» » { XX } },	10615 { Bad_Opcode },

8890 },	10616 },

8891 {	10617 {

8892 /* RM_0F01_REG_3 */	10618 /* RM_0F01_REG_3 */

8893 { "vmrun", { Skip_MODRM } },	10619 { "vmrun", { Skip_MODRM } },

8894 { "vmmcall", { Skip_MODRM } },	10620 { "vmmcall", { Skip_MODRM } },

8895 { "vmload", { Skip_MODRM } },	10621 { "vmload", { Skip_MODRM } },

8896 { "vmsave", { Skip_MODRM } },	10622 { "vmsave", { Skip_MODRM } },

8897 { "stgi", { Skip_MODRM } },	10623 { "stgi", { Skip_MODRM } },

8898 { "clgi", { Skip_MODRM } },	10624 { "clgi", { Skip_MODRM } },

8899 { "skinit", { Skip_MODRM } },	10625 { "skinit", { Skip_MODRM } },

8900 { "invlpga", { Skip_MODRM } },	10626 { "invlpga", { Skip_MODRM } },

8901 },	10627 },

8902 {	10628 {

8903 /* RM_0F01_REG_7 */	10629 /* RM_0F01_REG_7 */

8904 { "swapgs", { Skip_MODRM } },	10630 { "swapgs", { Skip_MODRM } },

8905 { "rdtscp", { Skip_MODRM } },	10631 { "rdtscp", { Skip_MODRM } },

8906 { "(bad)", { XX } },

8907 { "(bad)", { XX } },

8908 { "(bad)", { XX } },

8909 { "(bad)", { XX } },

8910 { "(bad)", { XX } },

8911 { "(bad)", { XX } },

8912 },	10632 },

8913 {	10633 {

8914 /* RM_0FAE_REG_5 */	10634 /* RM_0FAE_REG_5 */

8915 { "lfence", { Skip_MODRM } },	10635 { "lfence", { Skip_MODRM } },

8916 { "(bad)", { XX } },

8917 { "(bad)", { XX } },

8918 { "(bad)", { XX } },

8919 { "(bad)", { XX } },

8920 { "(bad)", { XX } },

8921 { "(bad)", { XX } },

8922 { "(bad)", { XX } },

8923 },	10636 },

8924 {	10637 {

8925 /* RM_0FAE_REG_6 */	10638 /* RM_0FAE_REG_6 */

8926 { "mfence", { Skip_MODRM } },	10639 { "mfence", { Skip_MODRM } },

8927 { "(bad)", { XX } },

8928 { "(bad)", { XX } },

8929 { "(bad)", { XX } },

8930 { "(bad)", { XX } },

8931 { "(bad)", { XX } },

8932 { "(bad)", { XX } },

8933 { "(bad)", { XX } },

8934 },	10640 },

8935 {	10641 {

8936 /* RM_0FAE_REG_7 */	10642 /* RM_0FAE_REG_7 */

8937 { "sfence", { Skip_MODRM } },	10643 { "sfence", { Skip_MODRM } },

8938 { "(bad)", { XX } },

8939 { "(bad)", { XX } },

8940 { "(bad)", { XX } },

8941 { "(bad)", { XX } },

8942 { "(bad)", { XX } },

8943 { "(bad)", { XX } },

8944 { "(bad)", { XX } },

8945 },	10644 },

8946 };	10645 };

8947	10646

8948 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")	10647 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")

8949	10648

8950 static void	10649 /* We use the high bit to indicate different name for the same

	10650 prefix. */

	10651 #define ADDR16_PREFIX» (0x67 \| 0x100)

	10652 #define ADDR32_PREFIX» (0x67 \| 0x200)

	10653 #define DATA16_PREFIX» (0x66 \| 0x100)

	10654 #define DATA32_PREFIX» (0x66 \| 0x200)

	10655 #define REP_PREFIX» (0xf3 \| 0x100)

	10656 #define XACQUIRE_PREFIX»(0xf2 \| 0x200)

	10657 #define XRELEASE_PREFIX»(0xf3 \| 0x400)

	10658

	10659 static int

8951 ckprefix (void)	10660 ckprefix (void)

8952 {	10661 {

8953 int newrex;	10662 int newrex, i, length;

8954 rex = 0;	10663 rex = 0;

8955 rex_original = 0;

8956 rex_ignored = 0;	10664 rex_ignored = 0;

8957 prefixes = 0;	10665 prefixes = 0;

8958 used_prefixes = 0;	10666 used_prefixes = 0;

8959 rex_used = 0;	10667 rex_used = 0;

8960 while (1)	10668 last_lock_prefix = -1;

	10669 last_repz_prefix = -1;

	10670 last_repnz_prefix = -1;

	10671 last_data_prefix = -1;

	10672 last_addr_prefix = -1;

	10673 last_rex_prefix = -1;

	10674 last_seg_prefix = -1;

	10675 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)

	10676 all_prefixes[i] = 0;

	10677 i = 0;

	10678 length = 0;

	10679 /* The maximum instruction length is 15bytes. */

	10680 while (length < MAX_CODE_LENGTH - 1)

8961 {	10681 {

8962 FETCH_DATA (the_info, codep + 1);	10682 FETCH_DATA (the_info, codep + 1);

8963 newrex = 0;	10683 newrex = 0;

8964 switch (*codep)	10684 switch (*codep)

8965 {	10685 {

8966 /* REX prefixes family. */	10686 /* REX prefixes family. */

8967 case 0x40:	10687 case 0x40:

8968 case 0x41:	10688 case 0x41:

8969 case 0x42:	10689 case 0x42:

8970 case 0x43:	10690 case 0x43:

8971 case 0x44:	10691 case 0x44:

8972 case 0x45:	10692 case 0x45:

8973 case 0x46:	10693 case 0x46:

8974 case 0x47:	10694 case 0x47:

8975 case 0x48:	10695 case 0x48:

8976 case 0x49:	10696 case 0x49:

8977 case 0x4a:	10697 case 0x4a:

8978 case 0x4b:	10698 case 0x4b:

8979 case 0x4c:	10699 case 0x4c:

8980 case 0x4d:	10700 case 0x4d:

8981 case 0x4e:	10701 case 0x4e:

8982 case 0x4f:	10702 case 0x4f:

8983 » if (address_mode == mode_64bit)	10703 » if (address_mode == mode_64bit)

8984 » newrex = *codep;	10704 » newrex = *codep;

8985 » else	10705 » else

8986 » return;	10706 » return 1;

	10707 » last_rex_prefix = i;

8987 break;	10708 break;

8988 case 0xf3:	10709 case 0xf3:

8989 prefixes \|= PREFIX_REPZ;	10710 prefixes \|= PREFIX_REPZ;

	10711 last_repz_prefix = i;

8990 break;	10712 break;

8991 case 0xf2:	10713 case 0xf2:

8992 prefixes \|= PREFIX_REPNZ;	10714 prefixes \|= PREFIX_REPNZ;

	10715 last_repnz_prefix = i;

8993 break;	10716 break;

8994 case 0xf0:	10717 case 0xf0:

8995 prefixes \|= PREFIX_LOCK;	10718 prefixes \|= PREFIX_LOCK;

	10719 last_lock_prefix = i;

8996 break;	10720 break;

8997 case 0x2e:	10721 case 0x2e:

8998 prefixes \|= PREFIX_CS;	10722 prefixes \|= PREFIX_CS;

	10723 last_seg_prefix = i;

8999 break;	10724 break;

9000 case 0x36:	10725 case 0x36:

9001 prefixes \|= PREFIX_SS;	10726 prefixes \|= PREFIX_SS;

	10727 last_seg_prefix = i;

9002 break;	10728 break;

9003 case 0x3e:	10729 case 0x3e:

9004 prefixes \|= PREFIX_DS;	10730 prefixes \|= PREFIX_DS;

	10731 last_seg_prefix = i;

9005 break;	10732 break;

9006 case 0x26:	10733 case 0x26:

9007 prefixes \|= PREFIX_ES;	10734 prefixes \|= PREFIX_ES;

	10735 last_seg_prefix = i;

9008 break;	10736 break;

9009 case 0x64:	10737 case 0x64:

9010 prefixes \|= PREFIX_FS;	10738 prefixes \|= PREFIX_FS;

	10739 last_seg_prefix = i;

9011 break;	10740 break;

9012 case 0x65:	10741 case 0x65:

9013 prefixes \|= PREFIX_GS;	10742 prefixes \|= PREFIX_GS;

	10743 last_seg_prefix = i;

9014 break;	10744 break;

9015 case 0x66:	10745 case 0x66:

9016 prefixes \|= PREFIX_DATA;	10746 prefixes \|= PREFIX_DATA;

	10747 last_data_prefix = i;

9017 break;	10748 break;

9018 case 0x67:	10749 case 0x67:

9019 prefixes \|= PREFIX_ADDR;	10750 prefixes \|= PREFIX_ADDR;

	10751 last_addr_prefix = i;

9020 break;	10752 break;

9021 case FWAIT_OPCODE:	10753 case FWAIT_OPCODE:

9022 /* fwait is really an instruction. If there are prefixes	10754 /* fwait is really an instruction. If there are prefixes

9023 before the fwait, they belong to the fwait, not to the	10755 before the fwait, they belong to the fwait, not to the

9024 following instruction. */	10756 following instruction. */

9025 if (prefixes \|\| rex)	10757 if (prefixes \|\| rex)

9026 {	10758 {

9027 prefixes \|= PREFIX_FWAIT;	10759 prefixes \|= PREFIX_FWAIT;

9028 codep++;	10760 codep++;

9029 » return;	10761 » /* This ensures that the previous REX prefixes are noticed

	10762 » » as unused prefixes, as in the return case below. */

	10763 » rex_used = rex;

	10764 » return 1;

9030 }	10765 }

9031 prefixes = PREFIX_FWAIT;	10766 prefixes = PREFIX_FWAIT;

9032 break;	10767 break;

9033 default:	10768 default:

9034 » return;	10769 » return 1;

9035 }	10770 }

9036 /* Rex is ignored when followed by another prefix. */	10771 /* Rex is ignored when followed by another prefix. */

9037 if (rex)	10772 if (rex)

9038 {	10773 {

9039 rex_used = rex;	10774 rex_used = rex;

9040 » return;	10775 » return 1;

9041 }	10776 }

	10777 if (*codep != FWAIT_OPCODE)

	10778 all_prefixes[i++] = *codep;

9042 rex = newrex;	10779 rex = newrex;

9043 rex_original = rex;

9044 codep++;	10780 codep++;

	10781 length++;

	10782 }

	10783 return 0;

	10784 }

	10785

	10786 static int

	10787 seg_prefix (int pref)

	10788 {

	10789 switch (pref)

	10790 {

	10791 case 0x2e:

	10792 return PREFIX_CS;

	10793 case 0x36:

	10794 return PREFIX_SS;

	10795 case 0x3e:

	10796 return PREFIX_DS;

	10797 case 0x26:

	10798 return PREFIX_ES;

	10799 case 0x64:

	10800 return PREFIX_FS;

	10801 case 0x65:

	10802 return PREFIX_GS;

	10803 default:

	10804 return 0;

9045 }	10805 }

9046 }	10806 }

9047	10807

9048 /* Return the name of the prefix byte PREF, or NULL if PREF is not a	10808 /* Return the name of the prefix byte PREF, or NULL if PREF is not a

9049 prefix byte. */	10809 prefix byte. */

9050	10810

9051 static const char *	10811 static const char *

9052 prefix_name (int pref, int sizeflag)	10812 prefix_name (int pref, int sizeflag)

9053 {	10813 {

9054 static const char *rexes [16] =	10814 static const char *rexes [16] =

(...skipping 56 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
9111 return "gs";	10871 return "gs";

9112 case 0x66:	10872 case 0x66:

9113 return (sizeflag & DFLAG) ? "data16" : "data32";	10873 return (sizeflag & DFLAG) ? "data16" : "data32";

9114 case 0x67:	10874 case 0x67:

9115 if (address_mode == mode_64bit)	10875 if (address_mode == mode_64bit)

9116 return (sizeflag & AFLAG) ? "addr32" : "addr64";	10876 return (sizeflag & AFLAG) ? "addr32" : "addr64";

9117 else	10877 else

9118 return (sizeflag & AFLAG) ? "addr16" : "addr32";	10878 return (sizeflag & AFLAG) ? "addr16" : "addr32";

9119 case FWAIT_OPCODE:	10879 case FWAIT_OPCODE:

9120 return "fwait";	10880 return "fwait";

	10881 case ADDR16_PREFIX:

	10882 return "addr16";

	10883 case ADDR32_PREFIX:

	10884 return "addr32";

	10885 case DATA16_PREFIX:

	10886 return "data16";

	10887 case DATA32_PREFIX:

	10888 return "data32";

	10889 case REP_PREFIX:

	10890 return "rep";

	10891 case XACQUIRE_PREFIX:

	10892 return "xacquire";

	10893 case XRELEASE_PREFIX:

	10894 return "xrelease";

9121 default:	10895 default:

9122 return NULL;	10896 return NULL;

9123 }	10897 }

9124 }	10898 }

9125	10899

9126 static char op_out[MAX_OPERANDS][100];	10900 static char op_out[MAX_OPERANDS][100];

9127 static int op_ad, op_index[MAX_OPERANDS];	10901 static int op_ad, op_index[MAX_OPERANDS];

9128 static int two_source_ops;	10902 static int two_source_ops;

9129 static bfd_vma op_address[MAX_OPERANDS];	10903 static bfd_vma op_address[MAX_OPERANDS];

9130 static bfd_vma op_riprel[MAX_OPERANDS];	10904 static bfd_vma op_riprel[MAX_OPERANDS];

(...skipping 59 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
9190 fprintf (stream, _(" intel-mnemonic\n"	10964 fprintf (stream, _(" intel-mnemonic\n"

9191 " Display instruction in Intel mnemonic\n"));	10965 " Display instruction in Intel mnemonic\n"));

9192 fprintf (stream, _(" addr64 Assume 64bit address size\n"));	10966 fprintf (stream, _(" addr64 Assume 64bit address size\n"));

9193 fprintf (stream, _(" addr32 Assume 32bit address size\n"));	10967 fprintf (stream, _(" addr32 Assume 32bit address size\n"));

9194 fprintf (stream, _(" addr16 Assume 16bit address size\n"));	10968 fprintf (stream, _(" addr16 Assume 16bit address size\n"));

9195 fprintf (stream, _(" data32 Assume 32bit data size\n"));	10969 fprintf (stream, _(" data32 Assume 32bit data size\n"));

9196 fprintf (stream, _(" data16 Assume 16bit data size\n"));	10970 fprintf (stream, _(" data16 Assume 16bit data size\n"));

9197 fprintf (stream, _(" suffix Always display instruction suffix in AT&T sy ntax\n"));	10971 fprintf (stream, _(" suffix Always display instruction suffix in AT&T sy ntax\n"));

9198 }	10972 }

9199	10973

	10974 /* Bad opcode. */

	10975 static const struct dis386 bad_opcode = { "(bad)", { XX } };

	10976

9200 /* Get a pointer to struct dis386 with a valid name. */	10977 /* Get a pointer to struct dis386 with a valid name. */

9201	10978

9202 static const struct dis386 *	10979 static const struct dis386 *

9203 get_valid_dis386 (const struct dis386 dp, disassemble_info info)	10980 get_valid_dis386 (const struct dis386 dp, disassemble_info info)

9204 {	10981 {

9205 int index, vex_table_index;	10982 int vindex, vex_table_index;

9206	10983

9207 if (dp->name != NULL)	10984 if (dp->name != NULL)

9208 return dp;	10985 return dp;

9209	10986

9210 switch (dp->op[0].bytemode)	10987 switch (dp->op[0].bytemode)

9211 {	10988 {

9212 case USE_REG_TABLE:	10989 case USE_REG_TABLE:

9213 dp = &reg_table[dp->op[1].bytemode][modrm.reg];	10990 dp = &reg_table[dp->op[1].bytemode][modrm.reg];

9214 break;	10991 break;

9215	10992

9216 case USE_MOD_TABLE:	10993 case USE_MOD_TABLE:

9217 index = modrm.mod == 0x3 ? 1 : 0;	10994 vindex = modrm.mod == 0x3 ? 1 : 0;

9218 dp = &mod_table[dp->op[1].bytemode][index];	10995 dp = &mod_table[dp->op[1].bytemode][vindex];

9219 break;	10996 break;

9220	10997

9221 case USE_RM_TABLE:	10998 case USE_RM_TABLE:

9222 dp = &rm_table[dp->op[1].bytemode][modrm.rm];	10999 dp = &rm_table[dp->op[1].bytemode][modrm.rm];

9223 break;	11000 break;

9224	11001

9225 case USE_PREFIX_TABLE:	11002 case USE_PREFIX_TABLE:

9226 if (need_vex)	11003 if (need_vex)

9227 {	11004 {

9228 /* The prefix in VEX is implicit. */	11005 /* The prefix in VEX is implicit. */

9229 switch (vex.prefix)	11006 switch (vex.prefix)

9230 {	11007 {

9231 case 0:	11008 case 0:

9232 » index = 0;	11009 » vindex = 0;

9233 break;	11010 break;

9234 case REPE_PREFIX_OPCODE:	11011 case REPE_PREFIX_OPCODE:

9235 » index = 1;	11012 » vindex = 1;

9236 break;	11013 break;

9237 case DATA_PREFIX_OPCODE:	11014 case DATA_PREFIX_OPCODE:

9238 » index = 2;	11015 » vindex = 2;

9239 break;	11016 break;

9240 case REPNE_PREFIX_OPCODE:	11017 case REPNE_PREFIX_OPCODE:

9241 » index = 3;	11018 » vindex = 3;

9242 break;	11019 break;

9243 default:	11020 default:

9244 abort ();	11021 abort ();

9245 break;	11022 break;

9246 }	11023 }

9247 }	11024 }

9248 else	11025 else

9249 {	11026 {

9250 » index = 0;	11027 » vindex = 0;

9251 used_prefixes \|= (prefixes & PREFIX_REPZ);	11028 used_prefixes \|= (prefixes & PREFIX_REPZ);

9252 if (prefixes & PREFIX_REPZ)	11029 if (prefixes & PREFIX_REPZ)

9253 {	11030 {

9254 » index = 1;	11031 » vindex = 1;

9255 » repz_prefix = NULL;	11032 » all_prefixes[last_repz_prefix] = 0;

9256 }	11033 }

9257 else	11034 else

9258 {	11035 {

9259 /* We should check PREFIX_REPNZ and PREFIX_REPZ before	11036 /* We should check PREFIX_REPNZ and PREFIX_REPZ before

9260 PREFIX_DATA. */	11037 PREFIX_DATA. */

9261 used_prefixes \|= (prefixes & PREFIX_REPNZ);	11038 used_prefixes \|= (prefixes & PREFIX_REPNZ);

9262 if (prefixes & PREFIX_REPNZ)	11039 if (prefixes & PREFIX_REPNZ)

9263 {	11040 {

9264 » » index = 3;	11041 » » vindex = 3;

9265 » » repnz_prefix = NULL;	11042 » » all_prefixes[last_repnz_prefix] = 0;

9266 }	11043 }

9267 else	11044 else

9268 {	11045 {

9269 used_prefixes \|= (prefixes & PREFIX_DATA);	11046 used_prefixes \|= (prefixes & PREFIX_DATA);

9270 if (prefixes & PREFIX_DATA)	11047 if (prefixes & PREFIX_DATA)

9271 {	11048 {

9272 » » index = 2;	11049 » » vindex = 2;

9273 » » data_prefix = NULL;	11050 » » all_prefixes[last_data_prefix] = 0;

9274 }	11051 }

9275 }	11052 }

9276 }	11053 }

9277 }	11054 }

9278 dp = &prefix_table[dp->op[1].bytemode][index];	11055 dp = &prefix_table[dp->op[1].bytemode][vindex];

9279 break;	11056 break;

9280	11057

9281 case USE_X86_64_TABLE:	11058 case USE_X86_64_TABLE:

9282 index = address_mode == mode_64bit ? 1 : 0;	11059 vindex = address_mode == mode_64bit ? 1 : 0;

9283 dp = &x86_64_table[dp->op[1].bytemode][index];	11060 dp = &x86_64_table[dp->op[1].bytemode][vindex];

9284 break;	11061 break;

9285	11062

9286 case USE_3BYTE_TABLE:	11063 case USE_3BYTE_TABLE:

9287 FETCH_DATA (info, codep + 2);	11064 FETCH_DATA (info, codep + 2);

9288 index = *codep++;	11065 vindex = *codep++;

9289 dp = &three_byte_table[dp->op[1].bytemode][index];	11066 dp = &three_byte_table[dp->op[1].bytemode][vindex];

9290 modrm.mod = (*codep >> 6) & 3;	11067 modrm.mod = (*codep >> 6) & 3;

9291 modrm.reg = (*codep >> 3) & 7;	11068 modrm.reg = (*codep >> 3) & 7;

9292 modrm.rm = *codep & 7;	11069 modrm.rm = *codep & 7;

9293 break;	11070 break;

9294	11071

9295 case USE_VEX_LEN_TABLE:	11072 case USE_VEX_LEN_TABLE:

9296 if (!need_vex)	11073 if (!need_vex)

9297 abort ();	11074 abort ();

9298	11075

9299 switch (vex.length)	11076 switch (vex.length)

9300 {	11077 {

9301 case 128:	11078 case 128:

9302 » index = 0;	11079 » vindex = 0;

9303 break;	11080 break;

9304 case 256:	11081 case 256:

9305 » index = 1;	11082 » vindex = 1;

9306 break;	11083 break;

9307 default:	11084 default:

9308 abort ();	11085 abort ();

9309 break;	11086 break;

9310 }	11087 }

9311	11088

9312 dp = &vex_len_table[dp->op[1].bytemode][index];	11089 dp = &vex_len_table[dp->op[1].bytemode][vindex];

	11090 break;

	11091

	11092 case USE_XOP_8F_TABLE:

	11093 FETCH_DATA (info, codep + 3);

	11094 /* All bits in the REX prefix are ignored. */

	11095 rex_ignored = rex;

	11096 rex = ~(*codep >> 5) & 0x7;

	11097

	11098 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */

	11099 switch ((*codep & 0x1f))

	11100 » {

	11101 » default:

	11102 » dp = &bad_opcode;

	11103 » return dp;

	11104 » case 0x8:

	11105 » vex_table_index = XOP_08;

	11106 » break;

	11107 » case 0x9:

	11108 » vex_table_index = XOP_09;

	11109 » break;

	11110 » case 0xa:

	11111 » vex_table_index = XOP_0A;

	11112 » break;

	11113 » }

	11114 codep++;

	11115 vex.w = *codep & 0x80;

	11116 if (vex.w && address_mode == mode_64bit)

	11117 » rex \|= REX_W;

	11118

	11119 vex.register_specifier = (~(*codep >> 3)) & 0xf;

	11120 if (address_mode != mode_64bit

	11121 » && vex.register_specifier > 0x7)

	11122 » {

	11123 » dp = &bad_opcode;

	11124 » return dp;

	11125 » }

	11126

	11127 vex.length = (*codep & 0x4) ? 256 : 128;

	11128 switch ((*codep & 0x3))

	11129 » {

	11130 » case 0:

	11131 » vex.prefix = 0;

	11132 » break;

	11133 » case 1:

	11134 » vex.prefix = DATA_PREFIX_OPCODE;

	11135 » break;

	11136 » case 2:

	11137 » vex.prefix = REPE_PREFIX_OPCODE;

	11138 » break;

	11139 » case 3:

	11140 » vex.prefix = REPNE_PREFIX_OPCODE;

	11141 » break;

	11142 » }

	11143 need_vex = 1;

	11144 need_vex_reg = 1;

	11145 codep++;

	11146 vindex = *codep++;

	11147 dp = &xop_table[vex_table_index][vindex];

	11148

	11149 FETCH_DATA (info, codep + 1);

	11150 modrm.mod = (*codep >> 6) & 3;

	11151 modrm.reg = (*codep >> 3) & 7;

	11152 modrm.rm = *codep & 7;

9313 break;	11153 break;

9314	11154

9315 case USE_VEX_C4_TABLE:	11155 case USE_VEX_C4_TABLE:

9316 FETCH_DATA (info, codep + 3);	11156 FETCH_DATA (info, codep + 3);

9317 /* All bits in the REX prefix are ignored. */	11157 /* All bits in the REX prefix are ignored. */

9318 rex_ignored = rex;	11158 rex_ignored = rex;

9319 rex = ~(*codep >> 5) & 0x7;	11159 rex = ~(*codep >> 5) & 0x7;

9320 switch ((*codep & 0x1f))	11160 switch ((*codep & 0x1f))

9321 {	11161 {

9322 default:	11162 default:

9323 » BadOp ();	11163 » dp = &bad_opcode;

	11164 » return dp;

9324 case 0x1:	11165 case 0x1:

9325 » vex_table_index = 0;	11166 » vex_table_index = VEX_0F;

9326 break;	11167 break;

9327 case 0x2:	11168 case 0x2:

9328 » vex_table_index = 1;	11169 » vex_table_index = VEX_0F38;

9329 break;	11170 break;

9330 case 0x3:	11171 case 0x3:

9331 » vex_table_index = 2;	11172 » vex_table_index = VEX_0F3A;

9332 break;	11173 break;

9333 }	11174 }

9334 codep++;	11175 codep++;

9335 vex.w = *codep & 0x80;	11176 vex.w = *codep & 0x80;

9336 if (vex.w && address_mode == mode_64bit)	11177 if (vex.w && address_mode == mode_64bit)

9337 rex \|= REX_W;	11178 rex \|= REX_W;

9338	11179

9339 vex.register_specifier = (~(*codep >> 3)) & 0xf;	11180 vex.register_specifier = (~(*codep >> 3)) & 0xf;

9340 if (address_mode != mode_64bit	11181 if (address_mode != mode_64bit

9341 && vex.register_specifier > 0x7)	11182 && vex.register_specifier > 0x7)

9342 » BadOp ();	11183 » {

	11184 » dp = &bad_opcode;

	11185 » return dp;

	11186 » }

9343	11187

9344 vex.length = (*codep & 0x4) ? 256 : 128;	11188 vex.length = (*codep & 0x4) ? 256 : 128;

9345 switch ((*codep & 0x3))	11189 switch ((*codep & 0x3))

9346 {	11190 {

9347 case 0:	11191 case 0:

9348 vex.prefix = 0;	11192 vex.prefix = 0;

9349 break;	11193 break;

9350 case 1:	11194 case 1:

9351 vex.prefix = DATA_PREFIX_OPCODE;	11195 vex.prefix = DATA_PREFIX_OPCODE;

9352 break;	11196 break;

9353 case 2:	11197 case 2:

9354 vex.prefix = REPE_PREFIX_OPCODE;	11198 vex.prefix = REPE_PREFIX_OPCODE;

9355 break;	11199 break;

9356 case 3:	11200 case 3:

9357 vex.prefix = REPNE_PREFIX_OPCODE;	11201 vex.prefix = REPNE_PREFIX_OPCODE;

9358 break;	11202 break;

9359 }	11203 }

9360 need_vex = 1;	11204 need_vex = 1;

9361 need_vex_reg = 1;	11205 need_vex_reg = 1;

9362 codep++;	11206 codep++;

9363 index = *codep++;	11207 vindex = *codep++;

9364 dp = &vex_table[vex_table_index][index];	11208 dp = &vex_table[vex_table_index][vindex];

9365 /* There is no MODRM byte for VEX [82\|77]. */	11209 /* There is no MODRM byte for VEX [82\|77]. */

9366 if (index != 0x77 && index != 0x82)	11210 if (vindex != 0x77 && vindex != 0x82)

9367 {	11211 {

9368 FETCH_DATA (info, codep + 1);	11212 FETCH_DATA (info, codep + 1);

9369 modrm.mod = (*codep >> 6) & 3;	11213 modrm.mod = (*codep >> 6) & 3;

9370 modrm.reg = (*codep >> 3) & 7;	11214 modrm.reg = (*codep >> 3) & 7;

9371 modrm.rm = *codep & 7;	11215 modrm.rm = *codep & 7;

9372 }	11216 }

9373 break;	11217 break;

9374	11218

9375 case USE_VEX_C5_TABLE:	11219 case USE_VEX_C5_TABLE:

9376 FETCH_DATA (info, codep + 2);	11220 FETCH_DATA (info, codep + 2);

9377 /* All bits in the REX prefix are ignored. */	11221 /* All bits in the REX prefix are ignored. */

9378 rex_ignored = rex;	11222 rex_ignored = rex;

9379 rex = (*codep & 0x80) ? 0 : REX_R;	11223 rex = (*codep & 0x80) ? 0 : REX_R;

9380	11224

9381 vex.register_specifier = (~(*codep >> 3)) & 0xf;	11225 vex.register_specifier = (~(*codep >> 3)) & 0xf;

9382 if (address_mode != mode_64bit	11226 if (address_mode != mode_64bit

9383 && vex.register_specifier > 0x7)	11227 && vex.register_specifier > 0x7)

9384 » BadOp ();	11228 » {

	11229 » dp = &bad_opcode;

	11230 » return dp;

	11231 » }

	11232

	11233 vex.w = 0;

9385	11234

9386 vex.length = (*codep & 0x4) ? 256 : 128;	11235 vex.length = (*codep & 0x4) ? 256 : 128;

9387 switch ((*codep & 0x3))	11236 switch ((*codep & 0x3))

9388 {	11237 {

9389 case 0:	11238 case 0:

9390 vex.prefix = 0;	11239 vex.prefix = 0;

9391 break;	11240 break;

9392 case 1:	11241 case 1:

9393 vex.prefix = DATA_PREFIX_OPCODE;	11242 vex.prefix = DATA_PREFIX_OPCODE;

9394 break;	11243 break;

9395 case 2:	11244 case 2:

9396 vex.prefix = REPE_PREFIX_OPCODE;	11245 vex.prefix = REPE_PREFIX_OPCODE;

9397 break;	11246 break;

9398 case 3:	11247 case 3:

9399 vex.prefix = REPNE_PREFIX_OPCODE;	11248 vex.prefix = REPNE_PREFIX_OPCODE;

9400 break;	11249 break;

9401 }	11250 }

9402 need_vex = 1;	11251 need_vex = 1;

9403 need_vex_reg = 1;	11252 need_vex_reg = 1;

9404 codep++;	11253 codep++;

9405 index = *codep++;	11254 vindex = *codep++;

9406 dp = &vex_table[dp->op[1].bytemode][index];	11255 dp = &vex_table[dp->op[1].bytemode][vindex];

9407 /* There is no MODRM byte for VEX [82\|77]. */	11256 /* There is no MODRM byte for VEX [82\|77]. */

9408 if (index != 0x77 && index != 0x82)	11257 if (vindex != 0x77 && vindex != 0x82)

9409 {	11258 {

9410 FETCH_DATA (info, codep + 1);	11259 FETCH_DATA (info, codep + 1);

9411 modrm.mod = (*codep >> 6) & 3;	11260 modrm.mod = (*codep >> 6) & 3;

9412 modrm.reg = (*codep >> 3) & 7;	11261 modrm.reg = (*codep >> 3) & 7;

9413 modrm.rm = *codep & 7;	11262 modrm.rm = *codep & 7;

9414 }	11263 }

9415 break;	11264 break;

9416	11265

	11266 case USE_VEX_W_TABLE:

	11267 if (!need_vex)

	11268 abort ();

	11269

	11270 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];

	11271 break;

	11272

	11273 case 0:

	11274 dp = &bad_opcode;

	11275 break;

	11276

9417 default:	11277 default:

9418 abort ();	11278 abort ();

9419 }	11279 }

9420	11280

9421 if (dp->name != NULL)	11281 if (dp->name != NULL)

9422 return dp;	11282 return dp;

9423 else	11283 else

9424 return get_valid_dis386 (dp, info);	11284 return get_valid_dis386 (dp, info);

9425 }	11285 }

9426	11286

	11287 static void

	11288 get_sib (disassemble_info *info, int sizeflag)

	11289 {

	11290 /* If modrm.mod == 3, operand must be register. */

	11291 if (need_modrm

	11292 && ((sizeflag & AFLAG) \|\| address_mode == mode_64bit)

	11293 && modrm.mod != 3

	11294 && modrm.rm == 4)

	11295 {

	11296 FETCH_DATA (info, codep + 2);

	11297 sib.index = (codep [1] >> 3) & 7;

	11298 sib.scale = (codep [1] >> 6) & 3;

	11299 sib.base = codep [1] & 7;

	11300 }

	11301 }

	11302

9427 static int	11303 static int

9428 print_insn (bfd_vma pc, disassemble_info *info)	11304 print_insn (bfd_vma pc, disassemble_info *info)

9429 {	11305 {

9430 const struct dis386 *dp;	11306 const struct dis386 *dp;

9431 int i;	11307 int i;

9432 char *op_txt[MAX_OPERANDS];	11308 char *op_txt[MAX_OPERANDS];

9433 int needcomma;	11309 int needcomma;

9434 int sizeflag;	11310 int sizeflag;

9435 const char *p;	11311 const char *p;

9436 struct dis_private priv;	11312 struct dis_private priv;

9437 unsigned char op;	11313 int prefix_length;

9438 char prefix_obuf[32];	11314 int default_prefixes;

9439 char *prefix_obufp;

9440	11315

9441 if (info->mach == bfd_mach_x86_64_intel_syntax	11316 priv.orig_sizeflag = AFLAG \| DFLAG;

9442 \|\| info->mach == bfd_mach_x86_64	11317 if ((info->mach & bfd_mach_i386_i386) != 0)

9443 \|\| info->mach == bfd_mach_l1om	11318 address_mode = mode_32bit;

9444 \|\| info->mach == bfd_mach_l1om_intel_syntax)	11319 else if (info->mach == bfd_mach_i386_i8086)

	11320 {

	11321 address_mode = mode_16bit;

	11322 priv.orig_sizeflag = 0;

	11323 }

	11324 else

9445 address_mode = mode_64bit;	11325 address_mode = mode_64bit;

9446 else

9447 address_mode = mode_32bit;

9448	11326

9449 if (intel_syntax == (char) -1)	11327 if (intel_syntax == (char) -1)

9450 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax	11328 intel_syntax = (info->mach & bfd_mach_i386_i386_intel_syntax) != 0;

9451 » » \|\| info->mach == bfd_mach_x86_64_intel_syntax

9452 » » \|\| info->mach == bfd_mach_l1om_intel_syntax);

9453

9454 if (info->mach == bfd_mach_i386_i386

9455 \|\| info->mach == bfd_mach_x86_64

9456 \|\| info->mach == bfd_mach_l1om

9457 \|\| info->mach == bfd_mach_i386_i386_intel_syntax

9458 \|\| info->mach == bfd_mach_x86_64_intel_syntax

9459 \|\| info->mach == bfd_mach_l1om_intel_syntax)

9460 priv.orig_sizeflag = AFLAG \| DFLAG;

9461 else if (info->mach == bfd_mach_i386_i8086)

9462 priv.orig_sizeflag = 0;

9463 else

9464 abort ();

9465	11329

9466 for (p = info->disassembler_options; p != NULL; )	11330 for (p = info->disassembler_options; p != NULL; )

9467 {	11331 {

9468 if (CONST_STRNEQ (p, "x86-64"))	11332 if (CONST_STRNEQ (p, "x86-64"))

9469 {	11333 {

9470 address_mode = mode_64bit;	11334 address_mode = mode_64bit;

9471 priv.orig_sizeflag = AFLAG \| DFLAG;	11335 priv.orig_sizeflag = AFLAG \| DFLAG;

9472 }	11336 }

9473 else if (CONST_STRNEQ (p, "i386"))	11337 else if (CONST_STRNEQ (p, "i386"))

9474 {	11338 {

(...skipping 50 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
9525 }	11389 }

9526	11390

9527 if (intel_syntax)	11391 if (intel_syntax)

9528 {	11392 {

9529 names64 = intel_names64;	11393 names64 = intel_names64;

9530 names32 = intel_names32;	11394 names32 = intel_names32;

9531 names16 = intel_names16;	11395 names16 = intel_names16;

9532 names8 = intel_names8;	11396 names8 = intel_names8;

9533 names8rex = intel_names8rex;	11397 names8rex = intel_names8rex;

9534 names_seg = intel_names_seg;	11398 names_seg = intel_names_seg;

	11399 names_mm = intel_names_mm;

	11400 names_xmm = intel_names_xmm;

	11401 names_ymm = intel_names_ymm;

9535 index64 = intel_index64;	11402 index64 = intel_index64;

9536 index32 = intel_index32;	11403 index32 = intel_index32;

9537 index16 = intel_index16;	11404 index16 = intel_index16;

9538 open_char = '[';	11405 open_char = '[';

9539 close_char = ']';	11406 close_char = ']';

9540 separator_char = '+';	11407 separator_char = '+';

9541 scale_char = '*';	11408 scale_char = '*';

9542 }	11409 }

9543 else	11410 else

9544 {	11411 {

9545 names64 = att_names64;	11412 names64 = att_names64;

9546 names32 = att_names32;	11413 names32 = att_names32;

9547 names16 = att_names16;	11414 names16 = att_names16;

9548 names8 = att_names8;	11415 names8 = att_names8;

9549 names8rex = att_names8rex;	11416 names8rex = att_names8rex;

9550 names_seg = att_names_seg;	11417 names_seg = att_names_seg;

	11418 names_mm = att_names_mm;

	11419 names_xmm = att_names_xmm;

	11420 names_ymm = att_names_ymm;

9551 index64 = att_index64;	11421 index64 = att_index64;

9552 index32 = att_index32;	11422 index32 = att_index32;

9553 index16 = att_index16;	11423 index16 = att_index16;

9554 open_char = '(';	11424 open_char = '(';

9555 close_char = ')';	11425 close_char = ')';

9556 separator_char = ',';	11426 separator_char = ',';

9557 scale_char = ',';	11427 scale_char = ',';

9558 }	11428 }

9559	11429

9560 /* The output looks better if we put 7 bytes on a line, since that	11430 /* The output looks better if we put 7 bytes on a line, since that

9561 puts most long word instructions on a single line. Use 8 bytes	11431 puts most long word instructions on a single line. Use 8 bytes

9562 for Intel L1OM. */	11432 for Intel L1OM. */

9563 if (info->mach == bfd_mach_l1om	11433 if ((info->mach & bfd_mach_l1om) != 0)

9564 \|\| info->mach == bfd_mach_l1om_intel_syntax)

9565 info->bytes_per_line = 8;	11434 info->bytes_per_line = 8;

9566 else	11435 else

9567 info->bytes_per_line = 7;	11436 info->bytes_per_line = 7;

9568	11437

9569 info->private_data = &priv;	11438 info->private_data = &priv;

9570 priv.max_fetched = priv.the_buffer;	11439 priv.max_fetched = priv.the_buffer;

9571 priv.insn_start = pc;	11440 priv.insn_start = pc;

9572	11441

9573 obuf[0] = 0;	11442 obuf[0] = 0;

9574 for (i = 0; i < MAX_OPERANDS; ++i)	11443 for (i = 0; i < MAX_OPERANDS; ++i)

(...skipping 26 matching lines...) Expand all Loading...
9601 (unsigned int) priv.the_buffer[0]);	11470 (unsigned int) priv.the_buffer[0]);

9602 }	11471 }

9603	11472

9604 return 1;	11473 return 1;

9605 }	11474 }

9606	11475

9607 return -1;	11476 return -1;

9608 }	11477 }

9609	11478

9610 obufp = obuf;	11479 obufp = obuf;

9611 ckprefix ();	11480 sizeflag = priv.orig_sizeflag;

	11481

	11482 if (!ckprefix () \|\| rex_used)

	11483 {

	11484 /* Too many prefixes or unused REX prefixes. */

	11485 for (i = 0;

	11486 » i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];

	11487 » i++)

	11488 » (*info->fprintf_func) (info->stream, "%s%s",

	11489 » » » i == 0 ? "" : " ",

	11490 » » » prefix_name (all_prefixes[i], sizeflag));

	11491 return i;

	11492 }

9612	11493

9613 insn_codep = codep;	11494 insn_codep = codep;

9614 sizeflag = priv.orig_sizeflag;

9615	11495

9616 FETCH_DATA (info, codep + 1);	11496 FETCH_DATA (info, codep + 1);

9617 two_source_ops = (codep == 0x62) \|\| (codep == 0xc8);	11497 two_source_ops = (codep == 0x62) \|\| (codep == 0xc8);

9618	11498

9619 if (((prefixes & PREFIX_FWAIT)	11499 if (((prefixes & PREFIX_FWAIT)

9620 && ((codep < 0xd8) \|\| (codep > 0xdf)))	11500 && ((codep < 0xd8) \|\| (codep > 0xdf))))

9621 \|\| (rex && rex_used))

9622 {	11501 {

9623 const char *name;	11502 (*info->fprintf_func) (info->stream, "fwait");

9624

9625 /* fwait not followed by floating point instruction, or rex followed

9626 » by other prefixes. Print the first prefix. */

9627 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);

9628 if (name == NULL)

9629 » name = INTERNAL_DISASSEMBLER_ERROR;

9630 (*info->fprintf_func) (info->stream, "%s", name);

9631 return 1;	11503 return 1;

9632 }	11504 }

9633	11505

9634 op = 0;

9635

9636 if (*codep == 0x0f)	11506 if (*codep == 0x0f)

9637 {	11507 {

9638 unsigned char threebyte;	11508 unsigned char threebyte;

9639 FETCH_DATA (info, codep + 2);	11509 FETCH_DATA (info, codep + 2);

9640 threebyte = *++codep;	11510 threebyte = *++codep;

9641 dp = &dis386_twobyte[threebyte];	11511 dp = &dis386_twobyte[threebyte];

9642 need_modrm = twobyte_has_modrm[*codep];	11512 need_modrm = twobyte_has_modrm[*codep];

9643 codep++;	11513 codep++;

9644 }	11514 }

9645 else	11515 else

9646 {	11516 {

9647 dp = &dis386[*codep];	11517 dp = &dis386[*codep];

9648 need_modrm = onebyte_has_modrm[*codep];	11518 need_modrm = onebyte_has_modrm[*codep];

9649 codep++;	11519 codep++;

9650 }	11520 }

9651	11521

9652 if ((prefixes & PREFIX_REPZ))	11522 if ((prefixes & PREFIX_REPZ))

9653 {	11523 used_prefixes \|= PREFIX_REPZ;

9654 repz_prefix = "repz ";	11524 if ((prefixes & PREFIX_REPNZ))

9655 used_prefixes \|= PREFIX_REPZ;	11525 used_prefixes \|= PREFIX_REPNZ;

9656 }	11526 if ((prefixes & PREFIX_LOCK))

9657 else	11527 used_prefixes \|= PREFIX_LOCK;

9658 repz_prefix = NULL;

9659	11528

9660 if ((prefixes & PREFIX_REPNZ))	11529 default_prefixes = 0;

9661 {

9662 repnz_prefix = "repnz ";

9663 used_prefixes \|= PREFIX_REPNZ;

9664 }

9665 else

9666 repnz_prefix = NULL;

9667

9668 if ((prefixes & PREFIX_LOCK))

9669 {

9670 lock_prefix = "lock ";

9671 used_prefixes \|= PREFIX_LOCK;

9672 }

9673 else

9674 lock_prefix = NULL;

9675

9676 addr_prefix = NULL;

9677 if (prefixes & PREFIX_ADDR)	11530 if (prefixes & PREFIX_ADDR)

9678 {	11531 {

9679 sizeflag ^= AFLAG;	11532 sizeflag ^= AFLAG;

9680 if (dp->op[2].bytemode != loop_jcxz_mode \|\| intel_syntax)	11533 if (dp->op[2].bytemode != loop_jcxz_mode \|\| intel_syntax)

9681 {	11534 {

9682 if ((sizeflag & AFLAG) \|\| address_mode == mode_64bit)	11535 if ((sizeflag & AFLAG) \|\| address_mode == mode_64bit)

9683 » addr_prefix = "addr32 ";	11536 » all_prefixes[last_addr_prefix] = ADDR32_PREFIX;

9684 else	11537 else

9685 » addr_prefix = "addr16 ";	11538 » all_prefixes[last_addr_prefix] = ADDR16_PREFIX;

9686 » used_prefixes \|= PREFIX_ADDR;	11539 » default_prefixes \|= PREFIX_ADDR;

9687 }	11540 }

9688 }	11541 }

9689	11542

9690 data_prefix = NULL;

9691 if ((prefixes & PREFIX_DATA))	11543 if ((prefixes & PREFIX_DATA))

9692 {	11544 {

9693 sizeflag ^= DFLAG;	11545 sizeflag ^= DFLAG;

9694 if (dp->op[2].bytemode == cond_jump_mode	11546 if (dp->op[2].bytemode == cond_jump_mode

9695 && dp->op[0].bytemode == v_mode	11547 && dp->op[0].bytemode == v_mode

9696 && !intel_syntax)	11548 && !intel_syntax)

9697 {	11549 {

9698 if (sizeflag & DFLAG)	11550 if (sizeflag & DFLAG)

9699 » data_prefix = "data32 ";	11551 » all_prefixes[last_data_prefix] = DATA32_PREFIX;

9700 else	11552 else

9701 » data_prefix = "data16 ";	11553 » all_prefixes[last_data_prefix] = DATA16_PREFIX;

9702 » used_prefixes \|= PREFIX_DATA;	11554 » default_prefixes \|= PREFIX_DATA;

	11555 » }

	11556 else if (rex & REX_W)

	11557 » {

	11558 » /* REX_W will override PREFIX_DATA. */

	11559 » default_prefixes \|= PREFIX_DATA;

9703 }	11560 }

9704 }	11561 }

9705	11562

9706 if (need_modrm)	11563 if (need_modrm)

9707 {	11564 {

9708 FETCH_DATA (info, codep + 1);	11565 FETCH_DATA (info, codep + 1);

9709 modrm.mod = (*codep >> 6) & 3;	11566 modrm.mod = (*codep >> 6) & 3;

9710 modrm.reg = (*codep >> 3) & 7;	11567 modrm.reg = (*codep >> 3) & 7;

9711 modrm.rm = *codep & 7;	11568 modrm.rm = *codep & 7;

9712 }	11569 }

9713	11570

	11571 need_vex = 0;

	11572 need_vex_reg = 0;

	11573 vex_w_done = 0;

	11574

9714 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)	11575 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)

9715 {	11576 {

	11577 get_sib (info, sizeflag);

9716 dofloat (sizeflag);	11578 dofloat (sizeflag);

9717 }	11579 }

9718 else	11580 else

9719 {	11581 {

9720 need_vex = 0;

9721 need_vex_reg = 0;

9722 vex_w_done = 0;

9723 dp = get_valid_dis386 (dp, info);	11582 dp = get_valid_dis386 (dp, info);

9724 if (dp != NULL && putop (dp->name, sizeflag) == 0)	11583 if (dp != NULL && putop (dp->name, sizeflag) == 0)

9725 {	11584 » {

	11585 » get_sib (info, sizeflag);

9726 for (i = 0; i < MAX_OPERANDS; ++i)	11586 for (i = 0; i < MAX_OPERANDS; ++i)

9727 {	11587 {

9728 obufp = op_out[i];	11588 obufp = op_out[i];

9729 op_ad = MAX_OPERANDS - 1 - i;	11589 op_ad = MAX_OPERANDS - 1 - i;

9730 if (dp->op[i].rtn)	11590 if (dp->op[i].rtn)

9731 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);	11591 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);

9732 }	11592 }

9733 }	11593 }

9734 }	11594 }

9735	11595

9736 /* See if any prefixes were not used. If so, print the first one	11596 /* See if any prefixes were not used. If so, print the first one

9737 separately. If we don't do this, we'll wind up printing an	11597 separately. If we don't do this, we'll wind up printing an

9738 instruction stream which does not precisely correspond to the	11598 instruction stream which does not precisely correspond to the

9739 bytes we are disassembling. */	11599 bytes we are disassembling. */

9740 if ((prefixes & ~used_prefixes) != 0)	11600 if ((prefixes & ~(used_prefixes \| default_prefixes)) != 0)

9741 {	11601 {

9742 const char *name;	11602 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)

9743	11603 » if (all_prefixes[i])

9744 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);	11604 » {

9745 if (name == NULL)	11605 » const char *name;

9746 » name = INTERNAL_DISASSEMBLER_ERROR;	11606 » name = prefix_name (all_prefixes[i], priv.orig_sizeflag);

9747 (*info->fprintf_func) (info->stream, "%s", name);	11607 » if (name == NULL)

9748 return 1;	11608 » name = INTERNAL_DISASSEMBLER_ERROR;

9749 }	11609 » (*info->fprintf_func) (info->stream, "%s", name);

9750 if ((rex_original & ~rex_used) \|\| rex_ignored)	11610 » return 1;

9751 {	11611 » }

9752 const char *name;

9753 name = prefix_name (rex_original, priv.orig_sizeflag);

9754 if (name == NULL)

9755 » name = INTERNAL_DISASSEMBLER_ERROR;

9756 (*info->fprintf_func) (info->stream, "%s ", name);

9757 }	11612 }

9758	11613

9759 prefix_obuf[0] = 0;	11614 /* Check if the REX prefix is used. */

9760 prefix_obufp = prefix_obuf;	11615 if (rex_ignored == 0 && (rex ^ rex_used) == 0)

9761 if (lock_prefix)	11616 all_prefixes[last_rex_prefix] = 0;

9762 prefix_obufp = stpcpy (prefix_obufp, lock_prefix);

9763 if (repz_prefix)

9764 prefix_obufp = stpcpy (prefix_obufp, repz_prefix);

9765 if (repnz_prefix)

9766 prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);

9767 if (addr_prefix)

9768 prefix_obufp = stpcpy (prefix_obufp, addr_prefix);

9769 if (data_prefix)

9770 prefix_obufp = stpcpy (prefix_obufp, data_prefix);

9771	11617

9772 if (prefix_obuf[0] != 0)	11618 /* Check if the SEG prefix is used. */

9773 (*info->fprintf_func) (info->stream, "%s", prefix_obuf);	11619 if ((prefixes & (PREFIX_CS \| PREFIX_SS \| PREFIX_DS \| PREFIX_ES

	11620 » » \| PREFIX_FS \| PREFIX_GS)) != 0

	11621 && (used_prefixes

	11622 » & seg_prefix (all_prefixes[last_seg_prefix])) != 0)

	11623 all_prefixes[last_seg_prefix] = 0;

	11624

	11625 /* Check if the ADDR prefix is used. */

	11626 if ((prefixes & PREFIX_ADDR) != 0

	11627 && (used_prefixes & PREFIX_ADDR) != 0)

	11628 all_prefixes[last_addr_prefix] = 0;

	11629

	11630 /* Check if the DATA prefix is used. */

	11631 if ((prefixes & PREFIX_DATA) != 0

	11632 && (used_prefixes & PREFIX_DATA) != 0)

	11633 all_prefixes[last_data_prefix] = 0;

	11634

	11635 prefix_length = 0;

	11636 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)

	11637 if (all_prefixes[i])

	11638 {

	11639 » const char *name;

	11640 » name = prefix_name (all_prefixes[i], sizeflag);

	11641 » if (name == NULL)

	11642 » abort ();

	11643 » prefix_length += strlen (name) + 1;

	11644 » (*info->fprintf_func) (info->stream, "%s ", name);

	11645 }

	11646

	11647 /* Check maximum code length. */

	11648 if ((codep - start_codep) > MAX_CODE_LENGTH)

	11649 {

	11650 (*info->fprintf_func) (info->stream, "(bad)");

	11651 return MAX_CODE_LENGTH;

	11652 }

9774	11653

9775 obufp = mnemonicendp;	11654 obufp = mnemonicendp;

9776 for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)	11655 for (i = strlen (obuf) + prefix_length; i < 6; i++)

9777 oappend (" ");	11656 oappend (" ");

9778 oappend (" ");	11657 oappend (" ");

9779 (*info->fprintf_func) (info->stream, "%s", obuf);	11658 (*info->fprintf_func) (info->stream, "%s", obuf);

9780	11659

9781 /* The enter and bound instructions are printed with operands in the same	11660 /* The enter and bound instructions are printed with operands in the same

9782 order as the intel book; everything else is printed in reverse order. */	11661 order as the intel book; everything else is printed in reverse order. */

9783 if (intel_syntax \|\| two_source_ops)	11662 if (intel_syntax \|\| two_source_ops)

9784 {	11663 {

9785 bfd_vma riprel;	11664 bfd_vma riprel;

9786	11665

9787 for (i = 0; i < MAX_OPERANDS; ++i)	11666 for (i = 0; i < MAX_OPERANDS; ++i)

9788 op_txt[i] = op_out[i];	11667 » op_txt[i] = op_out[i];

9789	11668

9790 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)	11669 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)

9791 {	11670 {

9792 op_ad = op_index[i];	11671 » op_ad = op_index[i];

9793 op_index[i] = op_index[MAX_OPERANDS - 1 - i];	11672 » op_index[i] = op_index[MAX_OPERANDS - 1 - i];

9794 op_index[MAX_OPERANDS - 1 - i] = op_ad;	11673 » op_index[MAX_OPERANDS - 1 - i] = op_ad;

9795 riprel = op_riprel[i];	11674 riprel = op_riprel[i];

9796 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];	11675 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];

9797 op_riprel[MAX_OPERANDS - 1 - i] = riprel;	11676 op_riprel[MAX_OPERANDS - 1 - i] = riprel;

9798 }	11677 }

9799 }	11678 }

9800 else	11679 else

9801 {	11680 {

9802 for (i = 0; i < MAX_OPERANDS; ++i)	11681 for (i = 0; i < MAX_OPERANDS; ++i)

9803 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];	11682 » op_txt[MAX_OPERANDS - 1 - i] = op_out[i];

9804 }	11683 }

9805	11684

9806 needcomma = 0;	11685 needcomma = 0;

9807 for (i = 0; i < MAX_OPERANDS; ++i)	11686 for (i = 0; i < MAX_OPERANDS; ++i)

9808 if (*op_txt[i])	11687 if (*op_txt[i])

9809 {	11688 {

9810 if (needcomma)	11689 if (needcomma)

9811 (*info->fprintf_func) (info->stream, ",");	11690 (*info->fprintf_func) (info->stream, ",");

9812 if (op_index[i] != -1 && !op_riprel[i])	11691 if (op_index[i] != -1 && !op_riprel[i])

9813 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);	11692 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);

(...skipping 186 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
10000 { "fsub", { ST, STi } },	11879 { "fsub", { ST, STi } },

10001 { "fsubr", { ST, STi } },	11880 { "fsubr", { ST, STi } },

10002 { "fdiv", { ST, STi } },	11881 { "fdiv", { ST, STi } },

10003 { "fdivr", { ST, STi } },	11882 { "fdivr", { ST, STi } },

10004 },	11883 },

10005 /* d9 */	11884 /* d9 */

10006 {	11885 {

10007 { "fld", { STi } },	11886 { "fld", { STi } },

10008 { "fxch", { STi } },	11887 { "fxch", { STi } },

10009 { FGRPd9_2 },	11888 { FGRPd9_2 },

10010 { "(bad)",» { XX } },	11889 { Bad_Opcode },

10011 { FGRPd9_4 },	11890 { FGRPd9_4 },

10012 { FGRPd9_5 },	11891 { FGRPd9_5 },

10013 { FGRPd9_6 },	11892 { FGRPd9_6 },

10014 { FGRPd9_7 },	11893 { FGRPd9_7 },

10015 },	11894 },

10016 /* da */	11895 /* da */

10017 {	11896 {

10018 { "fcmovb", { ST, STi } },	11897 { "fcmovb", { ST, STi } },

10019 { "fcmove", { ST, STi } },	11898 { "fcmove", { ST, STi } },

10020 { "fcmovbe",{ ST, STi } },	11899 { "fcmovbe",{ ST, STi } },

10021 { "fcmovu", { ST, STi } },	11900 { "fcmovu", { ST, STi } },

10022 { "(bad)",» { XX } },	11901 { Bad_Opcode },

10023 { FGRPda_5 },	11902 { FGRPda_5 },

10024 { "(bad)",» { XX } },	11903 { Bad_Opcode },

10025 { "(bad)",» { XX } },	11904 { Bad_Opcode },

10026 },	11905 },

10027 /* db */	11906 /* db */

10028 {	11907 {

10029 { "fcmovnb",{ ST, STi } },	11908 { "fcmovnb",{ ST, STi } },

10030 { "fcmovne",{ ST, STi } },	11909 { "fcmovne",{ ST, STi } },

10031 { "fcmovnbe",{ ST, STi } },	11910 { "fcmovnbe",{ ST, STi } },

10032 { "fcmovnu",{ ST, STi } },	11911 { "fcmovnu",{ ST, STi } },

10033 { FGRPdb_4 },	11912 { FGRPdb_4 },

10034 { "fucomi", { ST, STi } },	11913 { "fucomi", { ST, STi } },

10035 { "fcomi", { ST, STi } },	11914 { "fcomi", { ST, STi } },

10036 { "(bad)",» { XX } },	11915 { Bad_Opcode },

10037 },	11916 },

10038 /* dc */	11917 /* dc */

10039 {	11918 {

10040 { "fadd", { STi, ST } },	11919 { "fadd", { STi, ST } },

10041 { "fmul", { STi, ST } },	11920 { "fmul", { STi, ST } },

10042 { "(bad)",» { XX } },	11921 { Bad_Opcode },

10043 { "(bad)",» { XX } },	11922 { Bad_Opcode },

10044 { "fsub!M", { STi, ST } },	11923 { "fsub!M", { STi, ST } },

10045 { "fsubM", { STi, ST } },	11924 { "fsubM", { STi, ST } },

10046 { "fdiv!M", { STi, ST } },	11925 { "fdiv!M", { STi, ST } },

10047 { "fdivM", { STi, ST } },	11926 { "fdivM", { STi, ST } },

10048 },	11927 },

10049 /* dd */	11928 /* dd */

10050 {	11929 {

10051 { "ffree", { STi } },	11930 { "ffree", { STi } },

10052 { "(bad)",» { XX } },	11931 { Bad_Opcode },

10053 { "fst", { STi } },	11932 { "fst", { STi } },

10054 { "fstp", { STi } },	11933 { "fstp", { STi } },

10055 { "fucom", { STi } },	11934 { "fucom", { STi } },

10056 { "fucomp", { STi } },	11935 { "fucomp", { STi } },

10057 { "(bad)",» { XX } },	11936 { Bad_Opcode },

10058 { "(bad)",» { XX } },	11937 { Bad_Opcode },

10059 },	11938 },

10060 /* de */	11939 /* de */

10061 {	11940 {

10062 { "faddp", { STi, ST } },	11941 { "faddp", { STi, ST } },

10063 { "fmulp", { STi, ST } },	11942 { "fmulp", { STi, ST } },

10064 { "(bad)",» { XX } },	11943 { Bad_Opcode },

10065 { FGRPde_3 },	11944 { FGRPde_3 },

10066 { "fsub!Mp", { STi, ST } },	11945 { "fsub!Mp", { STi, ST } },

10067 { "fsubMp", { STi, ST } },	11946 { "fsubMp", { STi, ST } },

10068 { "fdiv!Mp", { STi, ST } },	11947 { "fdiv!Mp", { STi, ST } },

10069 { "fdivMp", { STi, ST } },	11948 { "fdivMp", { STi, ST } },

10070 },	11949 },

10071 /* df */	11950 /* df */

10072 {	11951 {

10073 { "ffreep", { STi } },	11952 { "ffreep", { STi } },

10074 { "(bad)",» { XX } },	11953 { Bad_Opcode },

10075 { "(bad)",» { XX } },	11954 { Bad_Opcode },

10076 { "(bad)",» { XX } },	11955 { Bad_Opcode },

10077 { FGRPdf_4 },	11956 { FGRPdf_4 },

10078 { "fucomip", { ST, STi } },	11957 { "fucomip", { ST, STi } },

10079 { "fcomip", { ST, STi } },	11958 { "fcomip", { ST, STi } },

10080 { "(bad)",» { XX } },	11959 { Bad_Opcode },

10081 },	11960 },

10082 };	11961 };

10083	11962

10084 static char *fgrps[][8] = {	11963 static char *fgrps[][8] = {

10085 /* d9_2 0 */	11964 /* d9_2 0 */

10086 {	11965 {

10087 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",	11966 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",

10088 },	11967 },

10089	11968

10090 /* d9_4 1 */	11969 /* d9_4 1 */

(...skipping 165 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
10256 break;	12135 break;

10257 case '}':	12136 case '}':

10258 break;	12137 break;

10259 case 'A':	12138 case 'A':

10260 if (intel_syntax)	12139 if (intel_syntax)

10261 break;	12140 break;

10262 if (modrm.mod != 3 \|\| (sizeflag & SUFFIX_ALWAYS))	12141 if (modrm.mod != 3 \|\| (sizeflag & SUFFIX_ALWAYS))

10263 *obufp++ = 'b';	12142 *obufp++ = 'b';

10264 break;	12143 break;

10265 case 'B':	12144 case 'B':

10266 » if (intel_syntax)	12145 » if (l == 0 && len == 1)

10267 » break;	12146 » {

10268 » if (sizeflag & SUFFIX_ALWAYS)	12147 case_B:

10269 » *obufp++ = 'b';	12148 » if (intel_syntax)

	12149 » » break;

	12150 » if (sizeflag & SUFFIX_ALWAYS)

	12151 » » *obufp++ = 'b';

	12152 » }

	12153 » else

	12154 » {

	12155 » if (l != 1

	12156 » » \|\| len != 2

	12157 » » \|\| last[0] != 'L')

	12158 » » {

	12159 » » SAVE_LAST (*p);

	12160 » » break;

	12161 » » }

	12162

	12163 » if (address_mode == mode_64bit

	12164 » » && !(prefixes & PREFIX_ADDR))

	12165 » » {

	12166 » » *obufp++ = 'a';

	12167 » » *obufp++ = 'b';

	12168 » » *obufp++ = 's';

	12169 » » }

	12170

	12171 » goto case_B;

	12172 » }

10270 break;	12173 break;

10271 case 'C':	12174 case 'C':

10272 if (intel_syntax && !alt)	12175 if (intel_syntax && !alt)

10273 break;	12176 break;

10274 if ((prefixes & PREFIX_DATA) \|\| (sizeflag & SUFFIX_ALWAYS))	12177 if ((prefixes & PREFIX_DATA) \|\| (sizeflag & SUFFIX_ALWAYS))

10275 {	12178 {

10276 if (sizeflag & DFLAG)	12179 if (sizeflag & DFLAG)

10277 *obufp++ = intel_syntax ? 'd' : 'l';	12180 *obufp++ = intel_syntax ? 'd' : 'l';

10278 else	12181 else

10279 *obufp++ = intel_syntax ? 'w' : 's';	12182 *obufp++ = intel_syntax ? 'w' : 's';

10280 used_prefixes \|= (prefixes & PREFIX_DATA);	12183 used_prefixes \|= (prefixes & PREFIX_DATA);

10281 }	12184 }

10282 break;	12185 break;

10283 case 'D':	12186 case 'D':

10284 if (intel_syntax \|\| !(sizeflag & SUFFIX_ALWAYS))	12187 if (intel_syntax \|\| !(sizeflag & SUFFIX_ALWAYS))

10285 break;	12188 break;

10286 USED_REX (REX_W);	12189 USED_REX (REX_W);

10287 if (modrm.mod == 3)	12190 if (modrm.mod == 3)

10288 {	12191 {

10289 if (rex & REX_W)	12192 if (rex & REX_W)

10290 *obufp++ = 'q';	12193 *obufp++ = 'q';

10291 else if (sizeflag & DFLAG)

10292 *obufp++ = intel_syntax ? 'd' : 'l';

10293 else	12194 else

10294 » » *obufp++ = 'w';	12195 » » {

10295 » used_prefixes \|= (prefixes & PREFIX_DATA);	12196 » » if (sizeflag & DFLAG)

	12197 » » *obufp++ = intel_syntax ? 'd' : 'l';

	12198 » » else

	12199 » » *obufp++ = 'w';

	12200 » » used_prefixes \|= (prefixes & PREFIX_DATA);

	12201 » » }

10296 }	12202 }

10297 else	12203 else

10298 *obufp++ = 'w';	12204 *obufp++ = 'w';

10299 break;	12205 break;

10300 case 'E': /* For jcxz/jecxz */	12206 case 'E': /* For jcxz/jecxz */

10301 if (address_mode == mode_64bit)	12207 if (address_mode == mode_64bit)

10302 {	12208 {

10303 if (sizeflag & AFLAG)	12209 if (sizeflag & AFLAG)

10304 *obufp++ = 'r';	12210 *obufp++ = 'r';

10305 else	12211 else

(...skipping 90 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
10396 if (rex & REX_W)	12302 if (rex & REX_W)

10397 *obufp++ = 'o';	12303 *obufp++ = 'o';

10398 else if (intel_syntax && (sizeflag & DFLAG))	12304 else if (intel_syntax && (sizeflag & DFLAG))

10399 *obufp++ = 'q';	12305 *obufp++ = 'q';

10400 else	12306 else

10401 *obufp++ = 'd';	12307 *obufp++ = 'd';

10402 if (!(rex & REX_W))	12308 if (!(rex & REX_W))

10403 used_prefixes \|= (prefixes & PREFIX_DATA);	12309 used_prefixes \|= (prefixes & PREFIX_DATA);

10404 break;	12310 break;

10405 case 'T':	12311 case 'T':

10406 » if (intel_syntax)	12312 » if (!intel_syntax

10407 » break;	12313 » && address_mode == mode_64bit

10408 » if (address_mode == mode_64bit && (sizeflag & DFLAG))	12314 » && ((sizeflag & DFLAG) \|\| (rex & REX_W)))

10409 {	12315 {

10410 *obufp++ = 'q';	12316 *obufp++ = 'q';

10411 break;	12317 break;

10412 }	12318 }

10413 /* Fall through. */	12319 /* Fall through. */

10414 case 'P':	12320 case 'P':

10415 if (intel_syntax)	12321 if (intel_syntax)

10416 » break;	12322 » {

	12323 » if ((rex & REX_W) == 0

	12324 » » && (prefixes & PREFIX_DATA))

	12325 » » {

	12326 » » if ((sizeflag & DFLAG) == 0)

	12327 » » *obufp++ = 'w';

	12328 » » used_prefixes \|= (prefixes & PREFIX_DATA);

	12329 » » }

	12330 » break;

	12331 » }

10417 if ((prefixes & PREFIX_DATA)	12332 if ((prefixes & PREFIX_DATA)

10418 \|\| (rex & REX_W)	12333 \|\| (rex & REX_W)

10419 \|\| (sizeflag & SUFFIX_ALWAYS))	12334 \|\| (sizeflag & SUFFIX_ALWAYS))

10420 {	12335 {

10421 USED_REX (REX_W);	12336 USED_REX (REX_W);

10422 if (rex & REX_W)	12337 if (rex & REX_W)

10423 *obufp++ = 'q';	12338 *obufp++ = 'q';

10424 else	12339 else

10425 {	12340 {

10426 if (sizeflag & DFLAG)	12341 if (sizeflag & DFLAG)

10427 *obufp++ = 'l';	12342 *obufp++ = 'l';

10428 else	12343 else

10429 *obufp++ = 'w';	12344 *obufp++ = 'w';

	12345 used_prefixes \|= (prefixes & PREFIX_DATA);

10430 }	12346 }

10431 used_prefixes \|= (prefixes & PREFIX_DATA);

10432 }	12347 }

10433 break;	12348 break;

10434 case 'U':	12349 case 'U':

10435 if (intel_syntax)	12350 if (intel_syntax)

10436 break;	12351 break;

10437 » if (address_mode == mode_64bit && (sizeflag & DFLAG))	12352 » if (address_mode == mode_64bit

	12353 » && ((sizeflag & DFLAG) \|\| (rex & REX_W)))

10438 {	12354 {

10439 if (modrm.mod != 3 \|\| (sizeflag & SUFFIX_ALWAYS))	12355 if (modrm.mod != 3 \|\| (sizeflag & SUFFIX_ALWAYS))

10440 *obufp++ = 'q';	12356 *obufp++ = 'q';

10441 break;	12357 break;

10442 }	12358 }

10443 /* Fall through. */	12359 /* Fall through. */

10444 goto case_Q;	12360 goto case_Q;

10445 case 'Q':	12361 case 'Q':

10446 if (l == 0 && len == 1)	12362 if (l == 0 && len == 1)

10447 {	12363 {

10448 case_Q:	12364 case_Q:

10449 if (intel_syntax && !alt)	12365 if (intel_syntax && !alt)

10450 break;	12366 break;

10451 USED_REX (REX_W);	12367 USED_REX (REX_W);

10452 if (modrm.mod != 3 \|\| (sizeflag & SUFFIX_ALWAYS))	12368 if (modrm.mod != 3 \|\| (sizeflag & SUFFIX_ALWAYS))

10453 {	12369 {

10454 if (rex & REX_W)	12370 if (rex & REX_W)

10455 *obufp++ = 'q';	12371 *obufp++ = 'q';

10456 else	12372 else

10457 {	12373 {

10458 if (sizeflag & DFLAG)	12374 if (sizeflag & DFLAG)

10459 *obufp++ = intel_syntax ? 'd' : 'l';	12375 *obufp++ = intel_syntax ? 'd' : 'l';

10460 else	12376 else

10461 *obufp++ = 'w';	12377 *obufp++ = 'w';

	12378 used_prefixes \|= (prefixes & PREFIX_DATA);

10462 }	12379 }

10463 used_prefixes \|= (prefixes & PREFIX_DATA);

10464 }	12380 }

10465 }	12381 }

10466 else	12382 else

10467 {	12383 {

10468 if (l != 1 \|\| len != 2 \|\| last[0] != 'L')	12384 if (l != 1 \|\| len != 2 \|\| last[0] != 'L')

10469 {	12385 {

10470 SAVE_LAST (*p);	12386 SAVE_LAST (*p);

10471 break;	12387 break;

10472 }	12388 }

10473 if (intel_syntax	12389 if (intel_syntax

(...skipping 21 matching lines...) Expand all Loading...
10495 }	12411 }

10496 else	12412 else

10497 *obufp++ = 'w';	12413 *obufp++ = 'w';

10498 if (intel_syntax && !p[1]	12414 if (intel_syntax && !p[1]

10499 && ((rex & REX_W) \|\| (sizeflag & DFLAG)))	12415 && ((rex & REX_W) \|\| (sizeflag & DFLAG)))

10500 *obufp++ = 'e';	12416 *obufp++ = 'e';

10501 if (!(rex & REX_W))	12417 if (!(rex & REX_W))

10502 used_prefixes \|= (prefixes & PREFIX_DATA);	12418 used_prefixes \|= (prefixes & PREFIX_DATA);

10503 break;	12419 break;

10504 case 'V':	12420 case 'V':

10505 » if (intel_syntax)	12421 » if (l == 0 && len == 1)

10506 » break;

10507 » if (address_mode == mode_64bit && (sizeflag & DFLAG))

10508 {	12422 {

10509 » if (sizeflag & SUFFIX_ALWAYS)	12423 » if (intel_syntax)

10510 » » *obufp++ = 'q';	12424 » » break;

10511 » break;	12425 » if (address_mode == mode_64bit

	12426 » » && ((sizeflag & DFLAG) \|\| (rex & REX_W)))

	12427 » » {

	12428 » » if (sizeflag & SUFFIX_ALWAYS)

	12429 » » *obufp++ = 'q';

	12430 » » break;

	12431 » » }

	12432 » }

	12433 » else

	12434 » {

	12435 » if (l != 1

	12436 » » \|\| len != 2

	12437 » » \|\| last[0] != 'L')

	12438 » » {

	12439 » » SAVE_LAST (*p);

	12440 » » break;

	12441 » » }

	12442

	12443 » if (rex & REX_W)

	12444 » » {

	12445 » » *obufp++ = 'a';

	12446 » » *obufp++ = 'b';

	12447 » » *obufp++ = 's';

	12448 » » }

10512 }	12449 }

10513 /* Fall through. */	12450 /* Fall through. */

	12451 goto case_S;

10514 case 'S':	12452 case 'S':

10515 » if (intel_syntax)	12453 » if (l == 0 && len == 1)

10516 » break;

10517 » if (sizeflag & SUFFIX_ALWAYS)

10518 {	12454 {

10519 » if (rex & REX_W)	12455 case_S:

10520 » » *obufp++ = 'q';	12456 » if (intel_syntax)

10521 » else	12457 » » break;

	12458 » if (sizeflag & SUFFIX_ALWAYS)

10522 {	12459 {

10523 » » if (sizeflag & DFLAG)	12460 » » if (rex & REX_W)

10524 » » *obufp++ = 'l';	12461 » » *obufp++ = 'q';

10525 else	12462 else

10526 » » *obufp++ = 'w';	12463 » » {

10527 » » used_prefixes \|= (prefixes & PREFIX_DATA);	12464 » » if (sizeflag & DFLAG)

	12465 » » » *obufp++ = 'l';

	12466 » » else

	12467 » » » *obufp++ = 'w';

	12468 » » used_prefixes \|= (prefixes & PREFIX_DATA);

	12469 » » }

10528 }	12470 }

10529 }	12471 }

	12472 else

	12473 {

	12474 if (l != 1

	12475 \|\| len != 2

	12476 \|\| last[0] != 'L')

	12477 {

	12478 SAVE_LAST (*p);

	12479 break;

	12480 }

	12481

	12482 if (address_mode == mode_64bit

	12483 && !(prefixes & PREFIX_ADDR))

	12484 {

	12485 *obufp++ = 'a';

	12486 *obufp++ = 'b';

	12487 *obufp++ = 's';

	12488 }

	12489

	12490 goto case_S;

	12491 }

10530 break;	12492 break;

10531 case 'X':	12493 case 'X':

10532 if (l != 0 \|\| len != 1)	12494 if (l != 0 \|\| len != 1)

10533 {	12495 {

10534 SAVE_LAST (*p);	12496 SAVE_LAST (*p);

10535 break;	12497 break;

10536 }	12498 }

10537 if (need_vex && vex.prefix)	12499 if (need_vex && vex.prefix)

10538 {	12500 {

10539 if (vex.prefix == DATA_PREFIX_OPCODE)	12501 if (vex.prefix == DATA_PREFIX_OPCODE)

10540 *obufp++ = 'd';	12502 *obufp++ = 'd';

10541 else	12503 else

10542 *obufp++ = 's';	12504 *obufp++ = 's';

10543 }	12505 }

10544 else if (prefixes & PREFIX_DATA)

10545 *obufp++ = 'd';

10546 else	12506 else

10547 » *obufp++ = 's';	12507 » {

10548 » used_prefixes \|= (prefixes & PREFIX_DATA);	12508 » if (prefixes & PREFIX_DATA)

	12509 » » *obufp++ = 'd';

	12510 » else

	12511 » » *obufp++ = 's';

	12512 » used_prefixes \|= (prefixes & PREFIX_DATA);

	12513 » }

10549 break;	12514 break;

10550 case 'Y':	12515 case 'Y':

10551 if (l == 0 && len == 1)	12516 if (l == 0 && len == 1)

10552 {	12517 {

10553 if (intel_syntax \|\| !(sizeflag & SUFFIX_ALWAYS))	12518 if (intel_syntax \|\| !(sizeflag & SUFFIX_ALWAYS))

10554 break;	12519 break;

10555 if (rex & REX_W)	12520 if (rex & REX_W)

10556 {	12521 {

10557 USED_REX (REX_W);	12522 USED_REX (REX_W);

10558 *obufp++ = 'q';	12523 *obufp++ = 'q';

(...skipping 39 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
10598 }	12563 }

10599 else if (sizeflag & DFLAG)	12564 else if (sizeflag & DFLAG)

10600 *obufp++ = 'w';	12565 *obufp++ = 'w';

10601 else	12566 else

10602 *obufp++ = 'b';	12567 *obufp++ = 'b';

10603 if (!(rex & REX_W))	12568 if (!(rex & REX_W))

10604 used_prefixes \|= (prefixes & PREFIX_DATA);	12569 used_prefixes \|= (prefixes & PREFIX_DATA);

10605 }	12570 }

10606 else	12571 else

10607 {	12572 {

10608 » if (l != 1 \|\| len != 2 \|\| last[0] != 'X')	12573 » if (l != 1

	12574 » » \|\| len != 2

	12575 » » \|\| (last[0] != 'X'

	12576 » » && last[0] != 'L'))

10609 {	12577 {

10610 SAVE_LAST (*p);	12578 SAVE_LAST (*p);

10611 break;	12579 break;

10612 }	12580 }

10613 if (!need_vex)	12581 if (!need_vex)

10614 abort ();	12582 abort ();

10615 » *obufp++ = vex.w ? 'd': 's';	12583 » if (last[0] == 'X')

	12584 » » *obufp++ = vex.w ? 'd': 's';

	12585 » else

	12586 » » *obufp++ = vex.w ? 'q': 'd';

10616 }	12587 }

10617 break;	12588 break;

10618 }	12589 }

10619 alt = 0;	12590 alt = 0;

10620 }	12591 }

10621 *obufp = 0;	12592 *obufp = 0;

10622 mnemonicendp = obufp;	12593 mnemonicendp = obufp;

10623 return 0;	12594 return 0;

10624 }	12595 }

10625	12596

(...skipping 155 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
10781 case b_mode:	12752 case b_mode:

10782 case b_swap_mode:	12753 case b_swap_mode:

10783 case dqb_mode:	12754 case dqb_mode:

10784 oappend ("BYTE PTR ");	12755 oappend ("BYTE PTR ");

10785 break;	12756 break;

10786 case w_mode:	12757 case w_mode:

10787 case dqw_mode:	12758 case dqw_mode:

10788 oappend ("WORD PTR ");	12759 oappend ("WORD PTR ");

10789 break;	12760 break;

10790 case stack_v_mode:	12761 case stack_v_mode:

10791 if (address_mode == mode_64bit && (sizeflag & DFLAG))	12762 if (address_mode == mode_64bit && ((sizeflag & DFLAG) \|\| (rex & REX_W)))

10792 {	12763 {

10793 oappend ("QWORD PTR ");	12764 oappend ("QWORD PTR ");

10794 used_prefixes \|= (prefixes & PREFIX_DATA);

10795 break;	12765 break;

10796 }	12766 }

10797 /* FALLTHRU */	12767 /* FALLTHRU */

10798 case v_mode:	12768 case v_mode:

10799 case v_swap_mode:	12769 case v_swap_mode:

10800 case dq_mode:	12770 case dq_mode:

10801 USED_REX (REX_W);	12771 USED_REX (REX_W);

10802 if (rex & REX_W)	12772 if (rex & REX_W)

10803 oappend ("QWORD PTR ");	12773 oappend ("QWORD PTR ");

10804 else if ((sizeflag & DFLAG) \|\| bytemode == dq_mode)

10805 oappend ("DWORD PTR ");

10806 else	12774 else

10807 » oappend ("WORD PTR ");	12775 » {

10808 used_prefixes \|= (prefixes & PREFIX_DATA);	12776 » if ((sizeflag & DFLAG) \|\| bytemode == dq_mode)

	12777 » oappend ("DWORD PTR ");

	12778 » else

	12779 » oappend ("WORD PTR ");

	12780 » used_prefixes \|= (prefixes & PREFIX_DATA);

	12781 » }

10809 break;	12782 break;

10810 case z_mode:	12783 case z_mode:

10811 if ((rex & REX_W) \|\| (sizeflag & DFLAG))	12784 if ((rex & REX_W) \|\| (sizeflag & DFLAG))

10812 *obufp++ = 'D';	12785 *obufp++ = 'D';

10813 oappend ("WORD PTR ");	12786 oappend ("WORD PTR ");

10814 if (!(rex & REX_W))	12787 if (!(rex & REX_W))

10815 used_prefixes \|= (prefixes & PREFIX_DATA);	12788 used_prefixes \|= (prefixes & PREFIX_DATA);

10816 break;	12789 break;

10817 case a_mode:	12790 case a_mode:

10818 if (sizeflag & DFLAG)	12791 if (sizeflag & DFLAG)

10819 oappend ("QWORD PTR ");	12792 oappend ("QWORD PTR ");

10820 else	12793 else

10821 oappend ("DWORD PTR ");	12794 oappend ("DWORD PTR ");

10822 used_prefixes \|= (prefixes & PREFIX_DATA);	12795 used_prefixes \|= (prefixes & PREFIX_DATA);

10823 break;	12796 break;

10824 case d_mode:	12797 case d_mode:

	12798 case d_scalar_mode:

	12799 case d_scalar_swap_mode:

10825 case d_swap_mode:	12800 case d_swap_mode:

10826 case dqd_mode:	12801 case dqd_mode:

10827 oappend ("DWORD PTR ");	12802 oappend ("DWORD PTR ");

10828 break;	12803 break;

10829 case q_mode:	12804 case q_mode:

	12805 case q_scalar_mode:

	12806 case q_scalar_swap_mode:

10830 case q_swap_mode:	12807 case q_swap_mode:

10831 oappend ("QWORD PTR ");	12808 oappend ("QWORD PTR ");

10832 break;	12809 break;

10833 case m_mode:	12810 case m_mode:

10834 if (address_mode == mode_64bit)	12811 if (address_mode == mode_64bit)

10835 oappend ("QWORD PTR ");	12812 oappend ("QWORD PTR ");

10836 else	12813 else

10837 oappend ("DWORD PTR ");	12814 oappend ("DWORD PTR ");

10838 break;	12815 break;

10839 case f_mode:	12816 case f_mode:

(...skipping 37 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
10877 case 128:	12854 case 128:

10878 oappend ("QWORD PTR ");	12855 oappend ("QWORD PTR ");

10879 break;	12856 break;

10880 case 256:	12857 case 256:

10881 oappend ("XMMWORD PTR ");	12858 oappend ("XMMWORD PTR ");

10882 break;	12859 break;

10883 default:	12860 default:

10884 abort ();	12861 abort ();

10885 }	12862 }

10886 break;	12863 break;

	12864 case xmm_mb_mode:

	12865 if (!need_vex)

	12866 abort ();

	12867

	12868 switch (vex.length)

	12869 {

	12870 case 128:

	12871 case 256:

	12872 oappend ("BYTE PTR ");

	12873 break;

	12874 default:

	12875 abort ();

	12876 }

	12877 break;

	12878 case xmm_mw_mode:

	12879 if (!need_vex)

	12880 abort ();

	12881

	12882 switch (vex.length)

	12883 {

	12884 case 128:

	12885 case 256:

	12886 oappend ("WORD PTR ");

	12887 break;

	12888 default:

	12889 abort ();

	12890 }

	12891 break;

	12892 case xmm_md_mode:

	12893 if (!need_vex)

	12894 abort ();

	12895

	12896 switch (vex.length)

	12897 {

	12898 case 128:

	12899 case 256:

	12900 oappend ("DWORD PTR ");

	12901 break;

	12902 default:

	12903 abort ();

	12904 }

	12905 break;

	12906 case xmm_mq_mode:

	12907 if (!need_vex)

	12908 abort ();

	12909

	12910 switch (vex.length)

	12911 {

	12912 case 128:

	12913 case 256:

	12914 oappend ("QWORD PTR ");

	12915 break;

	12916 default:

	12917 abort ();

	12918 }

	12919 break;

	12920 case xmmdw_mode:

	12921 if (!need_vex)

	12922 abort ();

	12923

	12924 switch (vex.length)

	12925 {

	12926 case 128:

	12927 oappend ("WORD PTR ");

	12928 break;

	12929 case 256:

	12930 oappend ("DWORD PTR ");

	12931 break;

	12932 default:

	12933 abort ();

	12934 }

	12935 break;

	12936 case xmmqd_mode:

	12937 if (!need_vex)

	12938 abort ();

	12939

	12940 switch (vex.length)

	12941 {

	12942 case 128:

	12943 oappend ("DWORD PTR ");

	12944 break;

	12945 case 256:

	12946 oappend ("QWORD PTR ");

	12947 break;

	12948 default:

	12949 abort ();

	12950 }

	12951 break;

10887 case ymmq_mode:	12952 case ymmq_mode:

10888 if (!need_vex)	12953 if (!need_vex)

10889 abort ();	12954 abort ();

10890	12955

10891 switch (vex.length)	12956 switch (vex.length)

10892 {	12957 {

10893 case 128:	12958 case 128:

10894 oappend ("QWORD PTR ");	12959 oappend ("QWORD PTR ");

10895 break;	12960 break;

10896 case 256:	12961 case 256:

10897 oappend ("YMMWORD PTR ");	12962 oappend ("YMMWORD PTR ");

10898 break;	12963 break;

10899 default:	12964 default:

10900 abort ();	12965 abort ();

10901 }	12966 }

10902 break;	12967 break;

	12968 case ymmxmm_mode:

	12969 if (!need_vex)

	12970 abort ();

	12971

	12972 switch (vex.length)

	12973 {

	12974 case 128:

	12975 case 256:

	12976 oappend ("XMMWORD PTR ");

	12977 break;

	12978 default:

	12979 abort ();

	12980 }

	12981 break;

10903 case o_mode:	12982 case o_mode:

10904 oappend ("OWORD PTR ");	12983 oappend ("OWORD PTR ");

10905 break;	12984 break;

10906 case vex_w_dq_mode:	12985 case vex_w_dq_mode:

	12986 case vex_scalar_w_dq_mode:

	12987 case vex_vsib_d_w_dq_mode:

	12988 case vex_vsib_q_w_dq_mode:

10907 if (!need_vex)	12989 if (!need_vex)

10908 abort ();	12990 abort ();

10909	12991

10910 if (vex.w)	12992 if (vex.w)

10911 oappend ("QWORD PTR ");	12993 oappend ("QWORD PTR ");

10912 else	12994 else

10913 oappend ("DWORD PTR ");	12995 oappend ("DWORD PTR ");

10914 break;	12996 break;

10915 default:	12997 default:

10916 break;	12998 break;

(...skipping 30 matching lines...) Expand all Loading...
10947 case d_mode:	13029 case d_mode:

10948 names = names32;	13030 names = names32;

10949 break;	13031 break;

10950 case q_mode:	13032 case q_mode:

10951 names = names64;	13033 names = names64;

10952 break;	13034 break;

10953 case m_mode:	13035 case m_mode:

10954 names = address_mode == mode_64bit ? names64 : names32;	13036 names = address_mode == mode_64bit ? names64 : names32;

10955 break;	13037 break;

10956 case stack_v_mode:	13038 case stack_v_mode:

10957 if (address_mode == mode_64bit && (sizeflag & DFLAG))	13039 if (address_mode == mode_64bit && ((sizeflag & DFLAG) \|\| (rex & REX_W)))

10958 {	13040 {

10959 names = names64;	13041 names = names64;

10960 used_prefixes \|= (prefixes & PREFIX_DATA);

10961 break;	13042 break;

10962 }	13043 }

10963 bytemode = v_mode;	13044 bytemode = v_mode;

10964 /* FALLTHRU */	13045 /* FALLTHRU */

10965 case v_mode:	13046 case v_mode:

10966 case v_swap_mode:	13047 case v_swap_mode:

10967 case dq_mode:	13048 case dq_mode:

10968 case dqb_mode:	13049 case dqb_mode:

10969 case dqd_mode:	13050 case dqd_mode:

10970 case dqw_mode:	13051 case dqw_mode:

10971 USED_REX (REX_W);	13052 USED_REX (REX_W);

10972 if (rex & REX_W)	13053 if (rex & REX_W)

10973 names = names64;	13054 names = names64;

10974 else if ((sizeflag & DFLAG)

10975 \|\| (bytemode != v_mode

10976 && bytemode != v_swap_mode))

10977 names = names32;

10978 else	13055 else

10979 » names = names16;	13056 » {

10980 used_prefixes \|= (prefixes & PREFIX_DATA);	13057 » if ((sizeflag & DFLAG)

	13058 » \|\| (bytemode != v_mode

	13059 » » && bytemode != v_swap_mode))

	13060 » names = names32;

	13061 » else

	13062 » names = names16;

	13063 » used_prefixes \|= (prefixes & PREFIX_DATA);

	13064 » }

10981 break;	13065 break;

10982 case 0:	13066 case 0:

10983 return;	13067 return;

10984 default:	13068 default:

10985 oappend (INTERNAL_DISASSEMBLER_ERROR);	13069 oappend (INTERNAL_DISASSEMBLER_ERROR);

10986 return;	13070 return;

10987 }	13071 }

10988 oappend (names[reg]);	13072 oappend (names[reg]);

10989 }	13073 }

10990	13074

(...skipping 11 matching lines...) Expand all Loading...
11002	13086

11003 if ((sizeflag & AFLAG) \|\| address_mode == mode_64bit)	13087 if ((sizeflag & AFLAG) \|\| address_mode == mode_64bit)

11004 {	13088 {

11005 /* 32/64 bit address mode */	13089 /* 32/64 bit address mode */

11006 int havedisp;	13090 int havedisp;

11007 int havesib;	13091 int havesib;

11008 int havebase;	13092 int havebase;

11009 int haveindex;	13093 int haveindex;

11010 int needindex;	13094 int needindex;

11011 int base, rbase;	13095 int base, rbase;

11012 int index = 0;	13096 int vindex = 0;

11013 int scale = 0;	13097 int scale = 0;

	13098 const char **indexes64 = names64;

	13099 const char **indexes32 = names32;

11014	13100

11015 havesib = 0;	13101 havesib = 0;

11016 havebase = 1;	13102 havebase = 1;

11017 haveindex = 0;	13103 haveindex = 0;

11018 base = modrm.rm;	13104 base = modrm.rm;

11019	13105

11020 if (base == 4)	13106 if (base == 4)

11021 {	13107 {

11022 havesib = 1;	13108 havesib = 1;

11023 » FETCH_DATA (the_info, codep + 1);	13109 » vindex = sib.index;

11024 » index = (*codep >> 3) & 7;

11025 » scale = (*codep >> 6) & 3;

11026 » base = *codep & 7;

11027 USED_REX (REX_X);	13110 USED_REX (REX_X);

11028 if (rex & REX_X)	13111 if (rex & REX_X)

11029 » index += 8;	13112 » vindex += 8;

11030 » haveindex = index != 4;	13113 » switch (bytemode)

	13114 » {

	13115 » case vex_vsib_d_w_dq_mode:

	13116 » case vex_vsib_q_w_dq_mode:

	13117 » if (!need_vex)

	13118 » » abort ();

	13119

	13120 » haveindex = 1;

	13121 » switch (vex.length)

	13122 » » {

	13123 » » case 128:

	13124 » » indexes64 = indexes32 = names_xmm;

	13125 » » break;

	13126 » » case 256:

	13127 » » if (!vex.w \|\| bytemode == vex_vsib_q_w_dq_mode)

	13128 » » indexes64 = indexes32 = names_ymm;

	13129 » » else

	13130 » » indexes64 = indexes32 = names_xmm;

	13131 » » break;

	13132 » » default:

	13133 » » abort ();

	13134 » » }

	13135 » break;

	13136 » default:

	13137 » haveindex = vindex != 4;

	13138 » break;

	13139 » }

	13140 » scale = sib.scale;

	13141 » base = sib.base;

11031 codep++;	13142 codep++;

11032 }	13143 }

11033 rbase = base + add;	13144 rbase = base + add;

11034	13145

11035 switch (modrm.mod)	13146 switch (modrm.mod)

11036 {	13147 {

11037 case 0:	13148 case 0:

11038 if (base == 5)	13149 if (base == 5)

11039 {	13150 {

11040 havebase = 0;	13151 havebase = 0;

(...skipping 63 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
11104 \|\| (havebase && base != ESP_REG_NUM))	13215 \|\| (havebase && base != ESP_REG_NUM))

11105 {	13216 {

11106 if (!intel_syntax \|\| havebase)	13217 if (!intel_syntax \|\| havebase)

11107 {	13218 {

11108 *obufp++ = separator_char;	13219 *obufp++ = separator_char;

11109 *obufp = '\0';	13220 *obufp = '\0';

11110 }	13221 }

11111 if (haveindex)	13222 if (haveindex)

11112 oappend (address_mode == mode_64bit	13223 oappend (address_mode == mode_64bit

11113 && (sizeflag & AFLAG)	13224 && (sizeflag & AFLAG)

11114 » » » ? names64[index] : names32[index]);	13225 » » » ? indexes64[vindex] : indexes32[vindex]);

11115 else	13226 else

11116 oappend (address_mode == mode_64bit	13227 oappend (address_mode == mode_64bit

11117 && (sizeflag & AFLAG)	13228 && (sizeflag & AFLAG)

11118 ? index64 : index32);	13229 ? index64 : index32);

11119	13230

11120 *obufp++ = scale_char;	13231 *obufp++ = scale_char;

11121 *obufp = '\0';	13232 *obufp = '\0';

11122 sprintf (scratchbuf, "%d", 1 << scale);	13233 sprintf (scratchbuf, "%d", 1 << scale);

11123 oappend (scratchbuf);	13234 oappend (scratchbuf);

11124 }	13235 }

11125 }	13236 }

11126 if (intel_syntax	13237 if (intel_syntax

11127 && (disp \|\| modrm.mod != 0 \|\| base == 5))	13238 && (disp \|\| modrm.mod != 0 \|\| base == 5))

11128 {	13239 {

11129 if (!havedisp \|\| (bfd_signed_vma) disp >= 0)	13240 if (!havedisp \|\| (bfd_signed_vma) disp >= 0)

11130 {	13241 {

11131 *obufp++ = '+';	13242 *obufp++ = '+';

11132 *obufp = '\0';	13243 *obufp = '\0';

11133 }	13244 }

11134 » else if (modrm.mod != 1)	13245 » else if (modrm.mod != 1 && disp != -disp)

11135 {	13246 {

11136 *obufp++ = '-';	13247 *obufp++ = '-';

11137 *obufp = '\0';	13248 *obufp = '\0';

11138 disp = - (bfd_signed_vma) disp;	13249 disp = - (bfd_signed_vma) disp;

11139 }	13250 }

11140	13251

11141 if (havedisp)	13252 if (havedisp)

11142 print_displacement (scratchbuf, disp);	13253 print_displacement (scratchbuf, disp);

11143 else	13254 else

11144 print_operand_value (scratchbuf, 1, disp);	13255 print_operand_value (scratchbuf, 1, disp);

(...skipping 14 matching lines...) Expand all Loading...
11159 {	13270 {

11160 oappend (names_seg[ds_reg - es_reg]);	13271 oappend (names_seg[ds_reg - es_reg]);

11161 oappend (":");	13272 oappend (":");

11162 }	13273 }

11163 print_operand_value (scratchbuf, 1, disp);	13274 print_operand_value (scratchbuf, 1, disp);

11164 oappend (scratchbuf);	13275 oappend (scratchbuf);

11165 }	13276 }

11166 }	13277 }

11167 }	13278 }

11168 else	13279 else

11169 { /* 16 bit address mode */	13280 {

	13281 /* 16 bit address mode */

	13282 used_prefixes \|= prefixes & PREFIX_ADDR;

11170 switch (modrm.mod)	13283 switch (modrm.mod)

11171 {	13284 {

11172 case 0:	13285 case 0:

11173 if (modrm.rm == 6)	13286 if (modrm.rm == 6)

11174 {	13287 {

11175 disp = get16 ();	13288 disp = get16 ();

11176 if ((disp & 0x8000) != 0)	13289 if ((disp & 0x8000) != 0)

11177 disp -= 0x10000;	13290 disp -= 0x10000;

11178 }	13291 }

11179 break;	13292 break;

(...skipping 54 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
11234 oappend (names_seg[ds_reg - es_reg]);	13347 oappend (names_seg[ds_reg - es_reg]);

11235 oappend (":");	13348 oappend (":");

11236 }	13349 }

11237 print_operand_value (scratchbuf, 1, disp & 0xffff);	13350 print_operand_value (scratchbuf, 1, disp & 0xffff);

11238 oappend (scratchbuf);	13351 oappend (scratchbuf);

11239 }	13352 }

11240 }	13353 }

11241 }	13354 }

11242	13355

11243 static void	13356 static void

11244 OP_E_extended (int bytemode, int sizeflag)	13357 OP_E (int bytemode, int sizeflag)

11245 {	13358 {

11246 /* Skip mod/rm byte. */	13359 /* Skip mod/rm byte. */

11247 MODRM_CHECK;	13360 MODRM_CHECK;

11248 codep++;	13361 codep++;

11249	13362

11250 if (modrm.mod == 3)	13363 if (modrm.mod == 3)

11251 OP_E_register (bytemode, sizeflag);	13364 OP_E_register (bytemode, sizeflag);

11252 else	13365 else

11253 OP_E_memory (bytemode, sizeflag);	13366 OP_E_memory (bytemode, sizeflag);

11254 }	13367 }

11255	13368

11256 static void	13369 static void

11257 OP_E (int bytemode, int sizeflag)

11258 {

11259 OP_E_extended (bytemode, sizeflag);

11260 }

11261

11262

11263 static void

11264 OP_G (int bytemode, int sizeflag)	13370 OP_G (int bytemode, int sizeflag)

11265 {	13371 {

11266 int add = 0;	13372 int add = 0;

11267 USED_REX (REX_R);	13373 USED_REX (REX_R);

11268 if (rex & REX_R)	13374 if (rex & REX_R)

11269 add += 8;	13375 add += 8;

11270 switch (bytemode)	13376 switch (bytemode)

11271 {	13377 {

11272 case b_mode:	13378 case b_mode:

11273 USED_REX (0);	13379 USED_REX (0);

(...skipping 12 matching lines...) Expand all Loading...
11286 oappend (names64[modrm.reg + add]);	13392 oappend (names64[modrm.reg + add]);

11287 break;	13393 break;

11288 case v_mode:	13394 case v_mode:

11289 case dq_mode:	13395 case dq_mode:

11290 case dqb_mode:	13396 case dqb_mode:

11291 case dqd_mode:	13397 case dqd_mode:

11292 case dqw_mode:	13398 case dqw_mode:

11293 USED_REX (REX_W);	13399 USED_REX (REX_W);

11294 if (rex & REX_W)	13400 if (rex & REX_W)

11295 oappend (names64[modrm.reg + add]);	13401 oappend (names64[modrm.reg + add]);

11296 else if ((sizeflag & DFLAG) \|\| bytemode != v_mode)

11297 oappend (names32[modrm.reg + add]);

11298 else	13402 else

11299 » oappend (names16[modrm.reg + add]);	13403 » {

11300 used_prefixes \|= (prefixes & PREFIX_DATA);	13404 » if ((sizeflag & DFLAG) \|\| bytemode != v_mode)

	13405 » oappend (names32[modrm.reg + add]);

	13406 » else

	13407 » oappend (names16[modrm.reg + add]);

	13408 » used_prefixes \|= (prefixes & PREFIX_DATA);

	13409 » }

11301 break;	13410 break;

11302 case m_mode:	13411 case m_mode:

11303 if (address_mode == mode_64bit)	13412 if (address_mode == mode_64bit)

11304 oappend (names64[modrm.reg + add]);	13413 oappend (names64[modrm.reg + add]);

11305 else	13414 else

11306 oappend (names32[modrm.reg + add]);	13415 oappend (names32[modrm.reg + add]);

11307 break;	13416 break;

11308 default:	13417 default:

11309 oappend (INTERNAL_DISASSEMBLER_ERROR);	13418 oappend (INTERNAL_DISASSEMBLER_ERROR);

11310 break;	13419 break;

(...skipping 80 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
11391 op_address[op_ad] = op & 0xffffffff;	13500 op_address[op_ad] = op & 0xffffffff;

11392 op_riprel[op_ad] = riprel & 0xffffffff;	13501 op_riprel[op_ad] = riprel & 0xffffffff;

11393 }	13502 }

11394 }	13503 }

11395	13504

11396 static void	13505 static void

11397 OP_REG (int code, int sizeflag)	13506 OP_REG (int code, int sizeflag)

11398 {	13507 {

11399 const char *s;	13508 const char *s;

11400 int add;	13509 int add;

	13510

	13511 switch (code)

	13512 {

	13513 case es_reg: case ss_reg: case cs_reg:

	13514 case ds_reg: case fs_reg: case gs_reg:

	13515 oappend (names_seg[code - es_reg]);

	13516 return;

	13517 }

	13518

11401 USED_REX (REX_B);	13519 USED_REX (REX_B);

11402 if (rex & REX_B)	13520 if (rex & REX_B)

11403 add = 8;	13521 add = 8;

11404 else	13522 else

11405 add = 0;	13523 add = 0;

11406	13524

11407 switch (code)	13525 switch (code)

11408 {	13526 {

11409 case ax_reg: case cx_reg: case dx_reg: case bx_reg:	13527 case ax_reg: case cx_reg: case dx_reg: case bx_reg:

11410 case sp_reg: case bp_reg: case si_reg: case di_reg:	13528 case sp_reg: case bp_reg: case si_reg: case di_reg:

11411 s = names16[code - ax_reg + add];	13529 s = names16[code - ax_reg + add];

11412 break;	13530 break;

11413 case es_reg: case ss_reg: case cs_reg:

11414 case ds_reg: case fs_reg: case gs_reg:

11415 s = names_seg[code - es_reg + add];

11416 break;

11417 case al_reg: case ah_reg: case cl_reg: case ch_reg:	13531 case al_reg: case ah_reg: case cl_reg: case ch_reg:

11418 case dl_reg: case dh_reg: case bl_reg: case bh_reg:	13532 case dl_reg: case dh_reg: case bl_reg: case bh_reg:

11419 USED_REX (0);	13533 USED_REX (0);

11420 if (rex)	13534 if (rex)

11421 s = names8rex[code - al_reg + add];	13535 s = names8rex[code - al_reg + add];

11422 else	13536 else

11423 s = names8[code - al_reg];	13537 s = names8[code - al_reg];

11424 break;	13538 break;

11425 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:	13539 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:

11426 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:	13540 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:

11427 if (address_mode == mode_64bit && (sizeflag & DFLAG))	13541 if (address_mode == mode_64bit

	13542 » && ((sizeflag & DFLAG) \|\| (rex & REX_W)))

11428 {	13543 {

11429 s = names64[code - rAX_reg + add];	13544 s = names64[code - rAX_reg + add];

11430 break;	13545 break;

11431 }	13546 }

11432 code += eAX_reg - rAX_reg;	13547 code += eAX_reg - rAX_reg;

11433 /* Fall through. */	13548 /* Fall through. */

11434 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:	13549 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:

11435 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:	13550 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:

11436 USED_REX (REX_W);	13551 USED_REX (REX_W);

11437 if (rex & REX_W)	13552 if (rex & REX_W)

11438 s = names64[code - eAX_reg + add];	13553 s = names64[code - eAX_reg + add];

11439 else if (sizeflag & DFLAG)

11440 s = names32[code - eAX_reg + add];

11441 else	13554 else

11442 » s = names16[code - eAX_reg + add];	13555 » {

11443 used_prefixes \|= (prefixes & PREFIX_DATA);	13556 » if (sizeflag & DFLAG)

	13557 » s = names32[code - eAX_reg + add];

	13558 » else

	13559 » s = names16[code - eAX_reg + add];

	13560 » used_prefixes \|= (prefixes & PREFIX_DATA);

	13561 » }

11444 break;	13562 break;

11445 default:	13563 default:

11446 s = INTERNAL_DISASSEMBLER_ERROR;	13564 s = INTERNAL_DISASSEMBLER_ERROR;

11447 break;	13565 break;

11448 }	13566 }

11449 oappend (s);	13567 oappend (s);

11450 }	13568 }

11451	13569

11452 static void	13570 static void

11453 OP_IMREG (int code, int sizeflag)	13571 OP_IMREG (int code, int sizeflag)

(...skipping 22 matching lines...) Expand all Loading...
11476 if (rex)	13594 if (rex)

11477 s = names8rex[code - al_reg];	13595 s = names8rex[code - al_reg];

11478 else	13596 else

11479 s = names8[code - al_reg];	13597 s = names8[code - al_reg];

11480 break;	13598 break;

11481 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:	13599 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:

11482 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:	13600 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:

11483 USED_REX (REX_W);	13601 USED_REX (REX_W);

11484 if (rex & REX_W)	13602 if (rex & REX_W)

11485 s = names64[code - eAX_reg];	13603 s = names64[code - eAX_reg];

11486 else if (sizeflag & DFLAG)

11487 s = names32[code - eAX_reg];

11488 else	13604 else

11489 » s = names16[code - eAX_reg];	13605 » {

11490 used_prefixes \|= (prefixes & PREFIX_DATA);	13606 » if (sizeflag & DFLAG)

	13607 » s = names32[code - eAX_reg];

	13608 » else

	13609 » s = names16[code - eAX_reg];

	13610 » used_prefixes \|= (prefixes & PREFIX_DATA);

	13611 » }

11491 break;	13612 break;

11492 case z_mode_ax_reg:	13613 case z_mode_ax_reg:

11493 if ((rex & REX_W) \|\| (sizeflag & DFLAG))	13614 if ((rex & REX_W) \|\| (sizeflag & DFLAG))

11494 s = *names32;	13615 s = *names32;

11495 else	13616 else

11496 s = *names16;	13617 s = *names16;

11497 if (!(rex & REX_W))	13618 if (!(rex & REX_W))

11498 used_prefixes \|= (prefixes & PREFIX_DATA);	13619 used_prefixes \|= (prefixes & PREFIX_DATA);

11499 break;	13620 break;

11500 default:	13621 default:

(...skipping 20 matching lines...) Expand all Loading...
11521 if (address_mode == mode_64bit)	13642 if (address_mode == mode_64bit)

11522 {	13643 {

11523 op = get32s ();	13644 op = get32s ();

11524 break;	13645 break;

11525 }	13646 }

11526 /* Fall through. */	13647 /* Fall through. */

11527 case v_mode:	13648 case v_mode:

11528 USED_REX (REX_W);	13649 USED_REX (REX_W);

11529 if (rex & REX_W)	13650 if (rex & REX_W)

11530 op = get32s ();	13651 op = get32s ();

11531 else if (sizeflag & DFLAG)

11532 {

11533 op = get32 ();

11534 mask = 0xffffffff;

11535 }

11536 else	13652 else

11537 {	13653 {

11538 » op = get16 ();	13654 » if (sizeflag & DFLAG)

11539 » mask = 0xfffff;	13655 » {

	13656 » op = get32 ();

	13657 » mask = 0xffffffff;

	13658 » }

	13659 » else

	13660 » {

	13661 » op = get16 ();

	13662 » mask = 0xfffff;

	13663 » }

	13664 » used_prefixes \|= (prefixes & PREFIX_DATA);

11540 }	13665 }

11541 used_prefixes \|= (prefixes & PREFIX_DATA);

11542 break;	13666 break;

11543 case w_mode:	13667 case w_mode:

11544 mask = 0xfffff;	13668 mask = 0xfffff;

11545 op = get16 ();	13669 op = get16 ();

11546 break;	13670 break;

11547 case const_1_mode:	13671 case const_1_mode:

11548 if (intel_syntax)	13672 if (intel_syntax)

11549 oappend ("1");	13673 » oappend ("1");

11550 return;	13674 return;

11551 default:	13675 default:

11552 oappend (INTERNAL_DISASSEMBLER_ERROR);	13676 oappend (INTERNAL_DISASSEMBLER_ERROR);

11553 return;	13677 return;

11554 }	13678 }

11555	13679

11556 op &= mask;	13680 op &= mask;

11557 scratchbuf[0] = '$';	13681 scratchbuf[0] = '$';

11558 print_operand_value (scratchbuf + 1, 1, op);	13682 print_operand_value (scratchbuf + 1, 1, op);

11559 oappend (scratchbuf + intel_syntax);	13683 oappend (scratchbuf + intel_syntax);

(...skipping 16 matching lines...) Expand all Loading...
11576 {	13700 {

11577 case b_mode:	13701 case b_mode:

11578 FETCH_DATA (the_info, codep + 1);	13702 FETCH_DATA (the_info, codep + 1);

11579 op = *codep++;	13703 op = *codep++;

11580 mask = 0xff;	13704 mask = 0xff;

11581 break;	13705 break;

11582 case v_mode:	13706 case v_mode:

11583 USED_REX (REX_W);	13707 USED_REX (REX_W);

11584 if (rex & REX_W)	13708 if (rex & REX_W)

11585 op = get64 ();	13709 op = get64 ();

11586 else if (sizeflag & DFLAG)

11587 {

11588 op = get32 ();

11589 mask = 0xffffffff;

11590 }

11591 else	13710 else

11592 {	13711 {

11593 » op = get16 ();	13712 » if (sizeflag & DFLAG)

11594 » mask = 0xfffff;	13713 » {

	13714 » op = get32 ();

	13715 » mask = 0xffffffff;

	13716 » }

	13717 » else

	13718 » {

	13719 » op = get16 ();

	13720 » mask = 0xfffff;

	13721 » }

	13722 » used_prefixes \|= (prefixes & PREFIX_DATA);

11595 }	13723 }

11596 used_prefixes \|= (prefixes & PREFIX_DATA);

11597 break;	13724 break;

11598 case w_mode:	13725 case w_mode:

11599 mask = 0xfffff;	13726 mask = 0xfffff;

11600 op = get16 ();	13727 op = get16 ();

11601 break;	13728 break;

11602 default:	13729 default:

11603 oappend (INTERNAL_DISASSEMBLER_ERROR);	13730 oappend (INTERNAL_DISASSEMBLER_ERROR);

11604 return;	13731 return;

11605 }	13732 }

11606	13733

11607 op &= mask;	13734 op &= mask;

11608 scratchbuf[0] = '$';	13735 scratchbuf[0] = '$';

11609 print_operand_value (scratchbuf + 1, 1, op);	13736 print_operand_value (scratchbuf + 1, 1, op);

11610 oappend (scratchbuf + intel_syntax);	13737 oappend (scratchbuf + intel_syntax);

11611 scratchbuf[0] = '\0';	13738 scratchbuf[0] = '\0';

11612 }	13739 }

11613	13740

11614 static void	13741 static void

11615 OP_sI (int bytemode, int sizeflag)	13742 OP_sI (int bytemode, int sizeflag)

11616 {	13743 {

11617 bfd_signed_vma op;	13744 bfd_signed_vma op;

11618 bfd_signed_vma mask = -1;

11619	13745

11620 switch (bytemode)	13746 switch (bytemode)

11621 {	13747 {

11622 case b_mode:	13748 case b_mode:

	13749 case b_T_mode:

11623 FETCH_DATA (the_info, codep + 1);	13750 FETCH_DATA (the_info, codep + 1);

11624 op = *codep++;	13751 op = *codep++;

11625 if ((op & 0x80) != 0)	13752 if ((op & 0x80) != 0)

11626 op -= 0x100;	13753 op -= 0x100;

11627 mask = 0xffffffff;	13754 if (bytemode == b_T_mode)

11628 break;

11629 case v_mode:

11630 USED_REX (REX_W);

11631 if (rex & REX_W)

11632 » op = get32s ();

11633 else if (sizeflag & DFLAG)

11634 {	13755 {

11635 » op = get32s ();	13756 » if (address_mode != mode_64bit

11636 » mask = 0xffffffff;	13757 » \|\| !((sizeflag & DFLAG) \|\| (rex & REX_W)))

	13758 » {

	13759 » /* The operand-size prefix is overridden by a REX prefix. */

	13760 » if ((sizeflag & DFLAG) \|\| (rex & REX_W))

	13761 » » op &= 0xffffffff;

	13762 » else

	13763 » » op &= 0xffff;

	13764 » }

11637 }	13765 }

11638 else	13766 else

11639 {	13767 {

11640 » mask = 0xffffffff;	13768 » if (!(rex & REX_W))

11641 » op = get16 ();	13769 » {

11642 » if ((op & 0x8000) != 0)	13770 » if (sizeflag & DFLAG)

11643 » op -= 0x10000;	13771 » » op &= 0xffffffff;

	13772 » else

	13773 » » op &= 0xffff;

	13774 » }

11644 }	13775 }

11645 used_prefixes \|= (prefixes & PREFIX_DATA);

11646 break;	13776 break;

11647 case w_mode:	13777 case v_mode:

11648 op = get16 ();	13778 /* The operand-size prefix is overridden by a REX prefix. */

11649 mask = 0xffffffff;	13779 if ((sizeflag & DFLAG) \|\| (rex & REX_W))

11650 if ((op & 0x8000) != 0)	13780 » op = get32s ();

11651 » op -= 0x10000;	13781 else

	13782 » op = get16 ();

11652 break;	13783 break;

11653 default:	13784 default:

11654 oappend (INTERNAL_DISASSEMBLER_ERROR);	13785 oappend (INTERNAL_DISASSEMBLER_ERROR);

11655 return;	13786 return;

11656 }	13787 }

11657	13788

11658 scratchbuf[0] = '$';	13789 scratchbuf[0] = '$';

11659 print_operand_value (scratchbuf + 1, 1, op);	13790 print_operand_value (scratchbuf + 1, 1, op);

11660 oappend (scratchbuf + intel_syntax);	13791 oappend (scratchbuf + intel_syntax);

11661 }	13792 }

11662	13793

11663 static void	13794 static void

11664 OP_J (int bytemode, int sizeflag)	13795 OP_J (int bytemode, int sizeflag)

11665 {	13796 {

11666 bfd_vma disp;	13797 bfd_vma disp;

11667 bfd_vma mask = -1;	13798 bfd_vma mask = -1;

11668 bfd_vma segment = 0;	13799 bfd_vma segment = 0;

11669	13800

11670 switch (bytemode)	13801 switch (bytemode)

11671 {	13802 {

11672 case b_mode:	13803 case b_mode:

11673 FETCH_DATA (the_info, codep + 1);	13804 FETCH_DATA (the_info, codep + 1);

11674 disp = *codep++;	13805 disp = *codep++;

11675 if ((disp & 0x80) != 0)	13806 if ((disp & 0x80) != 0)

11676 disp -= 0x100;	13807 disp -= 0x100;

11677 break;	13808 break;

11678 case v_mode:	13809 case v_mode:

	13810 USED_REX (REX_W);

11679 if ((sizeflag & DFLAG) \|\| (rex & REX_W))	13811 if ((sizeflag & DFLAG) \|\| (rex & REX_W))

11680 disp = get32s ();	13812 disp = get32s ();

11681 else	13813 else

11682 {	13814 {

11683 disp = get16 ();	13815 disp = get16 ();

11684 if ((disp & 0x8000) != 0)	13816 if ((disp & 0x8000) != 0)

11685 disp -= 0x10000;	13817 disp -= 0x10000;

11686 /* In 16bit mode, address is wrapped around at 64k within	13818 /* In 16bit mode, address is wrapped around at 64k within

11687 the same segment. Otherwise, a data16 prefix on a jump	13819 the same segment. Otherwise, a data16 prefix on a jump

11688 instruction means that the pc is masked to 16 bits after	13820 instruction means that the pc is masked to 16 bits after

11689 the displacement is added! */	13821 the displacement is added! */

11690 mask = 0xffff;	13822 mask = 0xffff;

11691 if ((prefixes & PREFIX_DATA) == 0)	13823 if ((prefixes & PREFIX_DATA) == 0)

11692 segment = ((start_pc + codep - start_codep)	13824 segment = ((start_pc + codep - start_codep)

11693 & ~((bfd_vma) 0xffff));	13825 & ~((bfd_vma) 0xffff));

11694 }	13826 }

11695 used_prefixes \|= (prefixes & PREFIX_DATA);	13827 if (!(rex & REX_W))

	13828 » used_prefixes \|= (prefixes & PREFIX_DATA);

11696 break;	13829 break;

11697 default:	13830 default:

11698 oappend (INTERNAL_DISASSEMBLER_ERROR);	13831 oappend (INTERNAL_DISASSEMBLER_ERROR);

11699 return;	13832 return;

11700 }	13833 }

11701 disp = ((start_pc + codep - start_codep + disp) & mask) \| segment;	13834 disp = ((start_pc + (codep - start_codep) + disp) & mask) \| segment;

11702 set_op (disp, 0);	13835 set_op (disp, 0);

11703 print_operand_value (scratchbuf, 1, disp);	13836 print_operand_value (scratchbuf, 1, disp);

11704 oappend (scratchbuf);	13837 oappend (scratchbuf);

11705 }	13838 }

11706	13839

11707 static void	13840 static void

11708 OP_SEG (int bytemode, int sizeflag)	13841 OP_SEG (int bytemode, int sizeflag)

11709 {	13842 {

11710 if (bytemode == w_mode)	13843 if (bytemode == w_mode)

11711 oappend (names_seg[modrm.reg]);	13844 oappend (names_seg[modrm.reg]);

(...skipping 164 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
11876 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)	14009 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)

11877 {	14010 {

11878 int add;	14011 int add;

11879 if (rex & REX_R)	14012 if (rex & REX_R)

11880 {	14013 {

11881 USED_REX (REX_R);	14014 USED_REX (REX_R);

11882 add = 8;	14015 add = 8;

11883 }	14016 }

11884 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))	14017 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))

11885 {	14018 {

11886 lock_prefix = NULL;	14019 all_prefixes[last_lock_prefix] = 0;

11887 used_prefixes \|= PREFIX_LOCK;	14020 used_prefixes \|= PREFIX_LOCK;

11888 add = 8;	14021 add = 8;

11889 }	14022 }

11890 else	14023 else

11891 add = 0;	14024 add = 0;

11892 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);	14025 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);

11893 oappend (scratchbuf + intel_syntax);	14026 oappend (scratchbuf + intel_syntax);

11894 }	14027 }

11895	14028

11896 static void	14029 static void

(...skipping 24 matching lines...) Expand all Loading...
11921 {	14054 {

11922 if (modrm.mod == 3)	14055 if (modrm.mod == 3)

11923 OP_E (bytemode, sizeflag);	14056 OP_E (bytemode, sizeflag);

11924 else	14057 else

11925 BadOp ();	14058 BadOp ();

11926 }	14059 }

11927	14060

11928 static void	14061 static void

11929 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)	14062 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)

11930 {	14063 {

	14064 int reg = modrm.reg;

	14065 const char **names;

	14066

11931 used_prefixes \|= (prefixes & PREFIX_DATA);	14067 used_prefixes \|= (prefixes & PREFIX_DATA);

11932 if (prefixes & PREFIX_DATA)	14068 if (prefixes & PREFIX_DATA)

11933 {	14069 {

11934 int add;	14070 names = names_xmm;

11935 USED_REX (REX_R);	14071 USED_REX (REX_R);

11936 if (rex & REX_R)	14072 if (rex & REX_R)

11937 » add = 8;	14073 » reg += 8;

11938 else

11939 » add = 0;

11940 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);

11941 }	14074 }

11942 else	14075 else

11943 sprintf (scratchbuf, "%%mm%d", modrm.reg);	14076 names = names_mm;

11944 oappend (scratchbuf + intel_syntax);	14077 oappend (names[reg]);

11945 }	14078 }

11946	14079

11947 static void	14080 static void

11948 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)	14081 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)

11949 {	14082 {

11950 int add;	14083 int reg = modrm.reg;

	14084 const char **names;

	14085

11951 USED_REX (REX_R);	14086 USED_REX (REX_R);

11952 if (rex & REX_R)	14087 if (rex & REX_R)

11953 add = 8;	14088 reg += 8;

11954 else	14089 if (need_vex

11955 add = 0;	14090 && bytemode != xmm_mode

11956 if (need_vex && bytemode != xmm_mode)	14091 && bytemode != scalar_mode)

11957 {	14092 {

11958 switch (vex.length)	14093 switch (vex.length)

11959 {	14094 {

11960 case 128:	14095 case 128:

11961 » sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);	14096 » names = names_xmm;

11962 break;	14097 break;

11963 case 256:	14098 case 256:

11964 » sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);	14099 » if (vex.w \|\| bytemode != vex_vsib_q_w_dq_mode)

	14100 » names = names_ymm;

	14101 » else

	14102 » names = names_xmm;

11965 break;	14103 break;

11966 default:	14104 default:

11967 abort ();	14105 abort ();

11968 }	14106 }

11969 }	14107 }

11970 else	14108 else

11971 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);	14109 names = names_xmm;

11972 oappend (scratchbuf + intel_syntax);	14110 oappend (names[reg]);

11973 }	14111 }

11974	14112

11975 static void	14113 static void

11976 OP_EM (int bytemode, int sizeflag)	14114 OP_EM (int bytemode, int sizeflag)

11977 {	14115 {

	14116 int reg;

	14117 const char **names;

	14118

11978 if (modrm.mod != 3)	14119 if (modrm.mod != 3)

11979 {	14120 {

11980 if (intel_syntax	14121 if (intel_syntax

11981 && (bytemode == v_mode \|\| bytemode == v_swap_mode))	14122 && (bytemode == v_mode \|\| bytemode == v_swap_mode))

11982 {	14123 {

11983 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;	14124 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;

11984 used_prefixes \|= (prefixes & PREFIX_DATA);	14125 used_prefixes \|= (prefixes & PREFIX_DATA);

11985 » }	14126 » }

11986 OP_E (bytemode, sizeflag);	14127 OP_E (bytemode, sizeflag);

11987 return;	14128 return;

11988 }	14129 }

11989	14130

11990 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)	14131 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)

11991 swap_operand ();	14132 swap_operand ();

11992	14133

11993 /* Skip mod/rm byte. */	14134 /* Skip mod/rm byte. */

11994 MODRM_CHECK;	14135 MODRM_CHECK;

11995 codep++;	14136 codep++;

11996 used_prefixes \|= (prefixes & PREFIX_DATA);	14137 used_prefixes \|= (prefixes & PREFIX_DATA);

	14138 reg = modrm.rm;

11997 if (prefixes & PREFIX_DATA)	14139 if (prefixes & PREFIX_DATA)

11998 {	14140 {

11999 int add;	14141 names = names_xmm;

12000

12001 USED_REX (REX_B);	14142 USED_REX (REX_B);

12002 if (rex & REX_B)	14143 if (rex & REX_B)

12003 » add = 8;	14144 » reg += 8;

12004 else

12005 » add = 0;

12006 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);

12007 }	14145 }

12008 else	14146 else

12009 sprintf (scratchbuf, "%%mm%d", modrm.rm);	14147 names = names_mm;

12010 oappend (scratchbuf + intel_syntax);	14148 oappend (names[reg]);

12011 }	14149 }

12012	14150

12013 /* cvt* are the only instructions in sse2 which have	14151 /* cvt* are the only instructions in sse2 which have

12014 both SSE and MMX operands and also have 0x66 prefix	14152 both SSE and MMX operands and also have 0x66 prefix

12015 in their opcode. 0x66 was originally used to differentiate	14153 in their opcode. 0x66 was originally used to differentiate

12016 between SSE and MMX instruction(operands). So we have to handle the	14154 between SSE and MMX instruction(operands). So we have to handle the

12017 cvt* separately using OP_EMC and OP_MXC */	14155 cvt* separately using OP_EMC and OP_MXC */

12018 static void	14156 static void

12019 OP_EMC (int bytemode, int sizeflag)	14157 OP_EMC (int bytemode, int sizeflag)

12020 {	14158 {

12021 if (modrm.mod != 3)	14159 if (modrm.mod != 3)

12022 {	14160 {

12023 if (intel_syntax && bytemode == v_mode)	14161 if (intel_syntax && bytemode == v_mode)

12024 {	14162 {

12025 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;	14163 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;

12026 used_prefixes \|= (prefixes & PREFIX_DATA);	14164 used_prefixes \|= (prefixes & PREFIX_DATA);

12027 » }	14165 » }

12028 OP_E (bytemode, sizeflag);	14166 OP_E (bytemode, sizeflag);

12029 return;	14167 return;

12030 }	14168 }

12031	14169

12032 /* Skip mod/rm byte. */	14170 /* Skip mod/rm byte. */

12033 MODRM_CHECK;	14171 MODRM_CHECK;

12034 codep++;	14172 codep++;

12035 used_prefixes \|= (prefixes & PREFIX_DATA);	14173 used_prefixes \|= (prefixes & PREFIX_DATA);

12036 sprintf (scratchbuf, "%%mm%d", modrm.rm);	14174 oappend (names_mm[modrm.rm]);

12037 oappend (scratchbuf + intel_syntax);

12038 }	14175 }

12039	14176

12040 static void	14177 static void

12041 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)	14178 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)

12042 {	14179 {

12043 used_prefixes \|= (prefixes & PREFIX_DATA);	14180 used_prefixes \|= (prefixes & PREFIX_DATA);

12044 sprintf (scratchbuf, "%%mm%d", modrm.reg);	14181 oappend (names_mm[modrm.reg]);

12045 oappend (scratchbuf + intel_syntax);

12046 }	14182 }

12047	14183

12048 static void	14184 static void

12049 OP_EX (int bytemode, int sizeflag)	14185 OP_EX (int bytemode, int sizeflag)

12050 {	14186 {

12051 int add;	14187 int reg;

	14188 const char **names;

12052	14189

12053 /* Skip mod/rm byte. */	14190 /* Skip mod/rm byte. */

12054 MODRM_CHECK;	14191 MODRM_CHECK;

12055 codep++;	14192 codep++;

12056	14193

12057 if (modrm.mod != 3)	14194 if (modrm.mod != 3)

12058 {	14195 {

12059 OP_E_memory (bytemode, sizeflag);	14196 OP_E_memory (bytemode, sizeflag);

12060 return;	14197 return;

12061 }	14198 }

12062	14199

	14200 reg = modrm.rm;

12063 USED_REX (REX_B);	14201 USED_REX (REX_B);

12064 if (rex & REX_B)	14202 if (rex & REX_B)

12065 add = 8;	14203 reg += 8;

12066 else

12067 add = 0;

12068	14204

12069 if ((sizeflag & SUFFIX_ALWAYS)	14205 if ((sizeflag & SUFFIX_ALWAYS)

12070 && (bytemode == x_swap_mode	14206 && (bytemode == x_swap_mode

12071 \|\| bytemode == d_swap_mode	14207 \|\| bytemode == d_swap_mode

12072 » \|\| bytemode == q_swap_mode))	14208 » \|\| bytemode == d_scalar_swap_mode

	14209 » \|\| bytemode == q_swap_mode

	14210 » \|\| bytemode == q_scalar_swap_mode))

12073 swap_operand ();	14211 swap_operand ();

12074	14212

12075 if (need_vex	14213 if (need_vex

12076 && bytemode != xmm_mode	14214 && bytemode != xmm_mode

12077 && bytemode != xmmq_mode)	14215 && bytemode != xmmdw_mode

	14216 && bytemode != xmmqd_mode

	14217 && bytemode != xmm_mb_mode

	14218 && bytemode != xmm_mw_mode

	14219 && bytemode != xmm_md_mode

	14220 && bytemode != xmm_mq_mode

	14221 && bytemode != xmmq_mode

	14222 && bytemode != d_scalar_mode

	14223 && bytemode != d_scalar_swap_mode

	14224 && bytemode != q_scalar_mode

	14225 && bytemode != q_scalar_swap_mode

	14226 && bytemode != vex_scalar_w_dq_mode)

12078 {	14227 {

12079 switch (vex.length)	14228 switch (vex.length)

12080 {	14229 {

12081 case 128:	14230 case 128:

12082 » sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);	14231 » names = names_xmm;

12083 break;	14232 break;

12084 case 256:	14233 case 256:

12085 » sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);	14234 » names = names_ymm;

12086 break;	14235 break;

12087 default:	14236 default:

12088 abort ();	14237 abort ();

12089 }	14238 }

12090 }	14239 }

12091 else	14240 else

12092 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);	14241 names = names_xmm;

12093 oappend (scratchbuf + intel_syntax);	14242 oappend (names[reg]);

12094 }	14243 }

12095	14244

12096 static void	14245 static void

12097 OP_MS (int bytemode, int sizeflag)	14246 OP_MS (int bytemode, int sizeflag)

12098 {	14247 {

12099 if (modrm.mod == 3)	14248 if (modrm.mod == 3)

12100 OP_EM (bytemode, sizeflag);	14249 OP_EM (bytemode, sizeflag);

12101 else	14250 else

12102 BadOp ();	14251 BadOp ();

12103 }	14252 }

(...skipping 211 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
12315 const char **op1_names;	14464 const char **op1_names;

12316 const char **names = (address_mode == mode_64bit	14465 const char **names = (address_mode == mode_64bit

12317 ? names64 : names32);	14466 ? names64 : names32);

12318	14467

12319 if (!(prefixes & PREFIX_ADDR))	14468 if (!(prefixes & PREFIX_ADDR))

12320 op1_names = (address_mode == mode_16bit	14469 op1_names = (address_mode == mode_16bit

12321 ? names16 : names);	14470 ? names16 : names);

12322 else	14471 else

12323 {	14472 {

12324 /* Remove "addr16/addr32". */	14473 /* Remove "addr16/addr32". */

12325 » addr_prefix = NULL;	14474 » all_prefixes[last_addr_prefix] = 0;

12326 op1_names = (address_mode != mode_32bit	14475 op1_names = (address_mode != mode_32bit

12327 ? names32 : names16);	14476 ? names32 : names16);

12328 used_prefixes \|= PREFIX_ADDR;	14477 used_prefixes \|= PREFIX_ADDR;

12329 }	14478 }

12330 strcpy (op_out[0], op1_names[0]);	14479 strcpy (op_out[0], op1_names[0]);

12331 strcpy (op_out[1], names[1]);	14480 strcpy (op_out[1], names[1]);

12332 strcpy (op_out[2], names[2]);	14481 strcpy (op_out[2], names[2]);

12333 two_source_ops = 1;	14482 two_source_ops = 1;

12334 }	14483 }

12335 /* Skip mod/rm byte. */	14484 /* Skip mod/rm byte. */

12336 MODRM_CHECK;	14485 MODRM_CHECK;

12337 codep++;	14486 codep++;

12338 }	14487 }

12339	14488

12340 static void	14489 static void

12341 BadOp (void)	14490 BadOp (void)

12342 {	14491 {

12343 /* Throw away prefixes and 1st. opcode byte. */	14492 /* Throw away prefixes and 1st. opcode byte. */

12344 codep = insn_codep + 1;	14493 codep = insn_codep + 1;

12345 oappend ("(bad)");	14494 oappend ("(bad)");

12346 }	14495 }

12347	14496

12348 static void	14497 static void

12349 REP_Fixup (int bytemode, int sizeflag)	14498 REP_Fixup (int bytemode, int sizeflag)

12350 {	14499 {

12351 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,	14500 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,

12352 lods and stos. */	14501 lods and stos. */

12353 if (prefixes & PREFIX_REPZ)	14502 if (prefixes & PREFIX_REPZ)

12354 repz_prefix = "rep ";	14503 all_prefixes[last_repz_prefix] = REP_PREFIX;

12355	14504

12356 switch (bytemode)	14505 switch (bytemode)

12357 {	14506 {

12358 case al_reg:	14507 case al_reg:

12359 case eAX_reg:	14508 case eAX_reg:

12360 case indir_dx_reg:	14509 case indir_dx_reg:

12361 OP_IMREG (bytemode, sizeflag);	14510 OP_IMREG (bytemode, sizeflag);

12362 break;	14511 break;

12363 case eDI_reg:	14512 case eDI_reg:

12364 OP_ESreg (bytemode, sizeflag);	14513 OP_ESreg (bytemode, sizeflag);

12365 break;	14514 break;

12366 case eSI_reg:	14515 case eSI_reg:

12367 OP_DSreg (bytemode, sizeflag);	14516 OP_DSreg (bytemode, sizeflag);

12368 break;	14517 break;

12369 default:	14518 default:

12370 abort ();	14519 abort ();

12371 break;	14520 break;

12372 }	14521 }

12373 }	14522 }

12374	14523

	14524 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as

	14525 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.

	14526 */

	14527

	14528 static void

	14529 HLE_Fixup1 (int bytemode, int sizeflag)

	14530 {

	14531 if (modrm.mod != 3

	14532 && (prefixes & PREFIX_LOCK) != 0)

	14533 {

	14534 if (prefixes & PREFIX_REPZ)

	14535 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;

	14536 if (prefixes & PREFIX_REPNZ)

	14537 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;

	14538 }

	14539

	14540 OP_E (bytemode, sizeflag);

	14541 }

	14542

	14543 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as

	14544 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.

	14545 */

	14546

	14547 static void

	14548 HLE_Fixup2 (int bytemode, int sizeflag)

	14549 {

	14550 if (modrm.mod != 3)

	14551 {

	14552 if (prefixes & PREFIX_REPZ)

	14553 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;

	14554 if (prefixes & PREFIX_REPNZ)

	14555 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;

	14556 }

	14557

	14558 OP_E (bytemode, sizeflag);

	14559 }

	14560

	14561 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as

	14562 "xrelease" for memory operand. No check for LOCK prefix. */

	14563

	14564 static void

	14565 HLE_Fixup3 (int bytemode, int sizeflag)

	14566 {

	14567 if (modrm.mod != 3

	14568 && last_repz_prefix > last_repnz_prefix

	14569 && (prefixes & PREFIX_REPZ) != 0)

	14570 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;

	14571

	14572 OP_E (bytemode, sizeflag);

	14573 }

	14574

12375 static void	14575 static void

12376 CMPXCHG8B_Fixup (int bytemode, int sizeflag)	14576 CMPXCHG8B_Fixup (int bytemode, int sizeflag)

12377 {	14577 {

12378 USED_REX (REX_W);	14578 USED_REX (REX_W);

12379 if (rex & REX_W)	14579 if (rex & REX_W)

12380 {	14580 {

12381 /* Change cmpxchg8b to cmpxchg16b. */	14581 /* Change cmpxchg8b to cmpxchg16b. */

12382 char *p = mnemonicendp - 2;	14582 char *p = mnemonicendp - 2;

12383 mnemonicendp = stpcpy (p, "16b");	14583 mnemonicendp = stpcpy (p, "16b");

12384 bytemode = o_mode;	14584 bytemode = o_mode;

12385 }	14585 }

	14586 else if ((prefixes & PREFIX_LOCK) != 0)

	14587 {

	14588 if (prefixes & PREFIX_REPZ)

	14589 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;

	14590 if (prefixes & PREFIX_REPNZ)

	14591 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;

	14592 }

	14593

12386 OP_M (bytemode, sizeflag);	14594 OP_M (bytemode, sizeflag);

12387 }	14595 }

12388	14596

12389 static void	14597 static void

12390 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)	14598 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)

12391 {	14599 {

	14600 const char **names;

	14601

12392 if (need_vex)	14602 if (need_vex)

12393 {	14603 {

12394 switch (vex.length)	14604 switch (vex.length)

12395 {	14605 {

12396 case 128:	14606 case 128:

12397 » sprintf (scratchbuf, "%%xmm%d", reg);	14607 » names = names_xmm;

12398 break;	14608 break;

12399 case 256:	14609 case 256:

12400 » sprintf (scratchbuf, "%%ymm%d", reg);	14610 » names = names_ymm;

12401 break;	14611 break;

12402 default:	14612 default:

12403 abort ();	14613 abort ();

12404 }	14614 }

12405 }	14615 }

12406 else	14616 else

12407 sprintf (scratchbuf, "%%xmm%d", reg);	14617 names = names_xmm;

12408 oappend (scratchbuf + intel_syntax);	14618 oappend (names[reg]);

12409 }	14619 }

12410	14620

12411 static void	14621 static void

12412 CRC32_Fixup (int bytemode, int sizeflag)	14622 CRC32_Fixup (int bytemode, int sizeflag)

12413 {	14623 {

12414 /* Add proper suffix to "crc32". */	14624 /* Add proper suffix to "crc32". */

12415 char *p = mnemonicendp;	14625 char *p = mnemonicendp;

12416	14626

12417 switch (bytemode)	14627 switch (bytemode)

12418 {	14628 {

12419 case b_mode:	14629 case b_mode:

12420 if (intel_syntax)	14630 if (intel_syntax)

12421 goto skip;	14631 goto skip;

12422	14632

12423 *p++ = 'b';	14633 *p++ = 'b';

12424 break;	14634 break;

12425 case v_mode:	14635 case v_mode:

12426 if (intel_syntax)	14636 if (intel_syntax)

12427 goto skip;	14637 goto skip;

12428	14638

12429 USED_REX (REX_W);	14639 USED_REX (REX_W);

12430 if (rex & REX_W)	14640 if (rex & REX_W)

12431 *p++ = 'q';	14641 *p++ = 'q';

12432 else if (sizeflag & DFLAG)

12433 *p++ = 'l';

12434 else	14642 else

12435 » *p++ = 'w';	14643 » {

12436 used_prefixes \|= (prefixes & PREFIX_DATA);	14644 » if (sizeflag & DFLAG)

	14645 » *p++ = 'l';

	14646 » else

	14647 » *p++ = 'w';

	14648 » used_prefixes \|= (prefixes & PREFIX_DATA);

	14649 » }

12437 break;	14650 break;

12438 default:	14651 default:

12439 oappend (INTERNAL_DISASSEMBLER_ERROR);	14652 oappend (INTERNAL_DISASSEMBLER_ERROR);

12440 break;	14653 break;

12441 }	14654 }

12442 mnemonicendp = p;	14655 mnemonicendp = p;

12443 *p = '\0';	14656 *p = '\0';

12444	14657

12445 skip:	14658 skip:

12446 if (modrm.mod == 3)	14659 if (modrm.mod == 3)

(...skipping 22 matching lines...) Expand all Loading...
12469 else if ((prefixes & PREFIX_DATA))	14682 else if ((prefixes & PREFIX_DATA))

12470 oappend (names16[modrm.rm + add]);	14683 oappend (names16[modrm.rm + add]);

12471 else	14684 else

12472 oappend (names32[modrm.rm + add]);	14685 oappend (names32[modrm.rm + add]);

12473 }	14686 }

12474 }	14687 }

12475 else	14688 else

12476 OP_E (bytemode, sizeflag);	14689 OP_E (bytemode, sizeflag);

12477 }	14690 }

12478	14691

	14692 static void

	14693 FXSAVE_Fixup (int bytemode, int sizeflag)

	14694 {

	14695 /* Add proper suffix to "fxsave" and "fxrstor". */

	14696 USED_REX (REX_W);

	14697 if (rex & REX_W)

	14698 {

	14699 char *p = mnemonicendp;

	14700 *p++ = '6';

	14701 *p++ = '4';

	14702 *p = '\0';

	14703 mnemonicendp = p;

	14704 }

	14705 OP_M (bytemode, sizeflag);

	14706 }

	14707

12479 /* Display the destination register operand for instructions with	14708 /* Display the destination register operand for instructions with

12480 VEX. */	14709 VEX. */

12481	14710

12482 static void	14711 static void

12483 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)	14712 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)

12484 {	14713 {

	14714 int reg;

	14715 const char **names;

	14716

12485 if (!need_vex)	14717 if (!need_vex)

12486 abort ();	14718 abort ();

12487	14719

12488 if (!need_vex_reg)	14720 if (!need_vex_reg)

12489 return;	14721 return;

12490	14722

	14723 reg = vex.register_specifier;

	14724 if (bytemode == vex_scalar_mode)

	14725 {

	14726 oappend (names_xmm[reg]);

	14727 return;

	14728 }

	14729

12491 switch (vex.length)	14730 switch (vex.length)

12492 {	14731 {

12493 case 128:	14732 case 128:

12494 switch (bytemode)	14733 switch (bytemode)

12495 {	14734 {

12496 case vex_mode:	14735 case vex_mode:

12497 case vex128_mode:	14736 case vex128_mode:

	14737 case vex_vsib_q_w_dq_mode:

	14738 names = names_xmm;

	14739 break;

	14740 case dq_mode:

	14741 if (vex.w)

	14742 names = names64;

	14743 else

	14744 names = names32;

12498 break;	14745 break;

12499 default:	14746 default:

12500 abort ();	14747 abort ();

12501 return;	14748 return;

12502 }	14749 }

12503

12504 sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);

12505 break;	14750 break;

12506 case 256:	14751 case 256:

12507 switch (bytemode)	14752 switch (bytemode)

12508 {	14753 {

12509 case vex_mode:	14754 case vex_mode:

12510 case vex256_mode:	14755 case vex256_mode:

	14756 names = names_ymm;

	14757 break;

	14758 case vex_vsib_q_w_dq_mode:

	14759 names = vex.w ? names_ymm : names_xmm;

12511 break;	14760 break;

12512 default:	14761 default:

12513 abort ();	14762 abort ();

12514 return;	14763 return;

12515 }	14764 }

12516

12517 sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);

12518 break;	14765 break;

12519 default:	14766 default:

12520 abort ();	14767 abort ();

12521 break;	14768 break;

12522 }	14769 }

12523 oappend (scratchbuf + intel_syntax);	14770 oappend (names[reg]);

12524 }	14771 }

12525	14772

12526 /* Get the VEX immediate byte without moving codep. */	14773 /* Get the VEX immediate byte without moving codep. */

12527	14774

12528 static unsigned char	14775 static unsigned char

12529 get_vex_imm8 (int sizeflag)	14776 get_vex_imm8 (int sizeflag, int opnum)

12530 {	14777 {

12531 int bytes_before_imm = 0;	14778 int bytes_before_imm = 0;

12532	14779

12533 /* Skip mod/rm byte. */

12534 MODRM_CHECK;

12535 codep++;

12536

12537 if (modrm.mod != 3)	14780 if (modrm.mod != 3)

12538 {	14781 {

12539 /* There are SIB/displacement bytes. */	14782 /* There are SIB/displacement bytes. */

12540 if ((sizeflag & AFLAG) \|\| address_mode == mode_64bit)	14783 if ((sizeflag & AFLAG) \|\| address_mode == mode_64bit)

12541 {	14784 {

12542 /* 32/64 bit address mode */	14785 /* 32/64 bit address mode */

12543 int base = modrm.rm;	14786 int base = modrm.rm;

12544	14787

12545 /* Check SIB byte. */	14788 /* Check SIB byte. */

12546 if (base == 4)	14789 if (base == 4)

12547 {	14790 {

12548 FETCH_DATA (the_info, codep + 1);	14791 FETCH_DATA (the_info, codep + 1);

12549 base = *codep & 7;	14792 base = *codep & 7;

12550 » bytes_before_imm++;	14793 » /* When decoding the third source, don't increase

	14794 » » bytes_before_imm as this has already been incremented

	14795 » » by one in OP_E_memory while decoding the second

	14796 » » source operand. */

	14797 » if (opnum == 0)

	14798 » » bytes_before_imm++;

12551 }	14799 }

12552	14800

12553 » switch (modrm.mod)	14801 » /* Don't increase bytes_before_imm when decoding the third source,

	14802 » it has already been incremented by OP_E_memory while decoding

	14803 » the second source operand. */

	14804 » if (opnum == 0)

12554 {	14805 {

12555 » case 0:	14806 » switch (modrm.mod)

12556 » /* When modrm.rm == 5 or modrm.rm == 4 and base in	14807 » » {

12557 » » SIB == 5, there is a 4 byte displacement. */	14808 » » case 0:

12558 » if (base != 5)	14809 » » /* When modrm.rm == 5 or modrm.rm == 4 and base in

12559 » » /* No displacement. */	14810 » » SIB == 5, there is a 4 byte displacement. */

12560 » » break;	14811 » » if (base != 5)

12561 » case 2:	14812 » » /* No displacement. */

12562 » /* 4 byte displacement. */	14813 » » break;

12563 » bytes_before_imm += 4;	14814 » » case 2:

12564 » break;	14815 » » /* 4 byte displacement. */

12565 » case 1:	14816 » » bytes_before_imm += 4;

12566 » /* 1 byte displacement. */	14817 » » break;

12567 » bytes_before_imm++;	14818 » » case 1:

12568 » break;	14819 » » /* 1 byte displacement. */

	14820 » » bytes_before_imm++;

	14821 » » break;

	14822 » » }

12569 }	14823 }

12570 }	14824 }

12571 else	14825 else

12572 » { /* 16 bit address mode */	14826 » {

12573 » switch (modrm.mod)	14827 » /* 16 bit address mode */

	14828 » /* Don't increase bytes_before_imm when decoding the third source,

	14829 » it has already been incremented by OP_E_memory while decoding

	14830 » the second source operand. */

	14831 » if (opnum == 0)

12574 {	14832 {

12575 » case 0:	14833 » switch (modrm.mod)

12576 » /* When modrm.rm == 6, there is a 2 byte displacement. */	14834 » » {

12577 » if (modrm.rm != 6)	14835 » » case 0:

12578 » » /* No displacement. */	14836 » » /* When modrm.rm == 6, there is a 2 byte displacement. */

12579 » » break;	14837 » » if (modrm.rm != 6)

12580 » case 2:	14838 » » /* No displacement. */

12581 » /* 2 byte displacement. */	14839 » » break;

12582 » bytes_before_imm += 2;	14840 » » case 2:

12583 » break;	14841 » » /* 2 byte displacement. */

12584 » case 1:	14842 » » bytes_before_imm += 2;

12585 » /* 1 byte displacement. */	14843 » » break;

12586 » bytes_before_imm++;	14844 » » case 1:

12587 » break;	14845 » » /* 1 byte displacement: when decoding the third source,

	14846 » » don't increase bytes_before_imm as this has already

	14847 » » been incremented by one in OP_E_memory while decoding

	14848 » » the second source operand. */

	14849 » » if (opnum == 0)

	14850 » » bytes_before_imm++;

	14851

	14852 » » break;

	14853 » » }

12588 }	14854 }

12589 }	14855 }

12590 }	14856 }

12591	14857

12592 FETCH_DATA (the_info, codep + bytes_before_imm + 1);	14858 FETCH_DATA (the_info, codep + bytes_before_imm + 1);

12593 return codep [bytes_before_imm];	14859 return codep [bytes_before_imm];

12594 }	14860 }

12595	14861

12596 static void	14862 static void

12597 OP_EX_VexReg (int bytemode, int sizeflag, int reg)	14863 OP_EX_VexReg (int bytemode, int sizeflag, int reg)

12598 {	14864 {

	14865 const char **names;

	14866

12599 if (reg == -1 && modrm.mod != 3)	14867 if (reg == -1 && modrm.mod != 3)

12600 {	14868 {

12601 OP_E_memory (bytemode, sizeflag);	14869 OP_E_memory (bytemode, sizeflag);

12602 return;	14870 return;

12603 }	14871 }

12604 else	14872 else

12605 {	14873 {

12606 if (reg == -1)	14874 if (reg == -1)

12607 {	14875 {

12608 reg = modrm.rm;	14876 reg = modrm.rm;

12609 USED_REX (REX_B);	14877 USED_REX (REX_B);

12610 if (rex & REX_B)	14878 if (rex & REX_B)

12611 reg += 8;	14879 reg += 8;

12612 }	14880 }

12613 else if (reg > 7 && address_mode != mode_64bit)	14881 else if (reg > 7 && address_mode != mode_64bit)

12614 BadOp ();	14882 BadOp ();

12615 }	14883 }

12616	14884

12617 switch (vex.length)	14885 switch (vex.length)

12618 {	14886 {

12619 case 128:	14887 case 128:

12620 sprintf (scratchbuf, "%%xmm%d", reg);	14888 names = names_xmm;

12621 break;	14889 break;

12622 case 256:	14890 case 256:

12623 sprintf (scratchbuf, "%%ymm%d", reg);	14891 names = names_ymm;

12624 break;	14892 break;

12625 default:	14893 default:

12626 abort ();	14894 abort ();

12627 }	14895 }

12628 oappend (scratchbuf + intel_syntax);	14896 oappend (names[reg]);

	14897 }

	14898

	14899 static void

	14900 OP_EX_VexImmW (int bytemode, int sizeflag)

	14901 {

	14902 int reg = -1;

	14903 static unsigned char vex_imm8;

	14904

	14905 if (vex_w_done == 0)

	14906 {

	14907 vex_w_done = 1;

	14908

	14909 /* Skip mod/rm byte. */

	14910 MODRM_CHECK;

	14911 codep++;

	14912

	14913 vex_imm8 = get_vex_imm8 (sizeflag, 0);

	14914

	14915 if (vex.w)

	14916 » reg = vex_imm8 >> 4;

	14917

	14918 OP_EX_VexReg (bytemode, sizeflag, reg);

	14919 }

	14920 else if (vex_w_done == 1)

	14921 {

	14922 vex_w_done = 2;

	14923

	14924 if (!vex.w)

	14925 » reg = vex_imm8 >> 4;

	14926

	14927 OP_EX_VexReg (bytemode, sizeflag, reg);

	14928 }

	14929 else

	14930 {

	14931 /* Output the imm8 directly. */

	14932 scratchbuf[0] = '$';

	14933 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);

	14934 oappend (scratchbuf + intel_syntax);

	14935 scratchbuf[0] = '\0';

	14936 codep++;

	14937 }

	14938 }

	14939

	14940 static void

	14941 OP_Vex_2src (int bytemode, int sizeflag)

	14942 {

	14943 if (modrm.mod == 3)

	14944 {

	14945 int reg = modrm.rm;

	14946 USED_REX (REX_B);

	14947 if (rex & REX_B)

	14948 » reg += 8;

	14949 oappend (names_xmm[reg]);

	14950 }

	14951 else

	14952 {

	14953 if (intel_syntax

	14954 » && (bytemode == v_mode \|\| bytemode == v_swap_mode))

	14955 » {

	14956 » bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;

	14957 » used_prefixes \|= (prefixes & PREFIX_DATA);

	14958 » }

	14959 OP_E (bytemode, sizeflag);

	14960 }

	14961 }

	14962

	14963 static void

	14964 OP_Vex_2src_1 (int bytemode, int sizeflag)

	14965 {

	14966 if (modrm.mod == 3)

	14967 {

	14968 /* Skip mod/rm byte. */

	14969 MODRM_CHECK;

	14970 codep++;

	14971 }

	14972

	14973 if (vex.w)

	14974 oappend (names_xmm[vex.register_specifier]);

	14975 else

	14976 OP_Vex_2src (bytemode, sizeflag);

	14977 }

	14978

	14979 static void

	14980 OP_Vex_2src_2 (int bytemode, int sizeflag)

	14981 {

	14982 if (vex.w)

	14983 OP_Vex_2src (bytemode, sizeflag);

	14984 else

	14985 oappend (names_xmm[vex.register_specifier]);

12629 }	14986 }

12630	14987

12631 static void	14988 static void

12632 OP_EX_VexW (int bytemode, int sizeflag)	14989 OP_EX_VexW (int bytemode, int sizeflag)

12633 {	14990 {

12634 int reg = -1;	14991 int reg = -1;

12635	14992

12636 if (!vex_w_done)	14993 if (!vex_w_done)

12637 {	14994 {

12638 vex_w_done = 1;	14995 vex_w_done = 1;

	14996

	14997 /* Skip mod/rm byte. */

	14998 MODRM_CHECK;

	14999 codep++;

	15000

12639 if (vex.w)	15001 if (vex.w)

12640 » reg = vex.register_specifier;	15002 » reg = get_vex_imm8 (sizeflag, 0) >> 4;

12641 }	15003 }

12642 else	15004 else

12643 {	15005 {

12644 if (!vex.w)	15006 if (!vex.w)

12645 » reg = vex.register_specifier;	15007 » reg = get_vex_imm8 (sizeflag, 1) >> 4;

12646 }	15008 }

12647	15009

12648 OP_EX_VexReg (bytemode, sizeflag, reg);	15010 OP_EX_VexReg (bytemode, sizeflag, reg);

12649 }	15011 }

12650	15012

12651 static void	15013 static void

12652 OP_VEX_FMA (int bytemode, int sizeflag)

12653 {

12654 int reg = get_vex_imm8 (sizeflag) >> 4;

12655

12656 if (reg > 7 && address_mode != mode_64bit)

12657 BadOp ();

12658

12659 switch (vex.length)

12660 {

12661 case 128:

12662 switch (bytemode)

12663 {

12664 case vex_mode:

12665 case vex128_mode:

12666 break;

12667 default:

12668 abort ();

12669 return;

12670 }

12671

12672 sprintf (scratchbuf, "%%xmm%d", reg);

12673 break;

12674 case 256:

12675 switch (bytemode)

12676 {

12677 case vex_mode:

12678 break;

12679 default:

12680 abort ();

12681 return;

12682 }

12683

12684 sprintf (scratchbuf, "%%ymm%d", reg);

12685 break;

12686 default:

12687 abort ();

12688 }

12689 oappend (scratchbuf + intel_syntax);

12690 }

12691

12692 static void

12693 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,	15014 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,

12694 int sizeflag ATTRIBUTE_UNUSED)	15015 int sizeflag ATTRIBUTE_UNUSED)

12695 {	15016 {

12696 /* Skip the immediate byte and check for invalid bits. */	15017 /* Skip the immediate byte and check for invalid bits. */

12697 FETCH_DATA (the_info, codep + 1);	15018 FETCH_DATA (the_info, codep + 1);

12698 if (*codep++ & 0xf)	15019 if (*codep++ & 0xf)

12699 BadOp ();	15020 BadOp ();

12700 }	15021 }

12701	15022

12702 static void	15023 static void

12703 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)	15024 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)

12704 {	15025 {

12705 int reg;	15026 int reg;

	15027 const char **names;

	15028

12706 FETCH_DATA (the_info, codep + 1);	15029 FETCH_DATA (the_info, codep + 1);

12707 reg = *codep++;	15030 reg = *codep++;

12708	15031

12709 if (bytemode != x_mode)	15032 if (bytemode != x_mode)

12710 abort ();	15033 abort ();

12711	15034

12712 if (reg & 0xf)	15035 if (reg & 0xf)

12713 BadOp ();	15036 BadOp ();

12714	15037

12715 reg >>= 4;	15038 reg >>= 4;

12716 if (reg > 7 && address_mode != mode_64bit)	15039 if (reg > 7 && address_mode != mode_64bit)

12717 BadOp ();	15040 BadOp ();

12718	15041

12719 switch (vex.length)	15042 switch (vex.length)

12720 {	15043 {

12721 case 128:	15044 case 128:

12722 sprintf (scratchbuf, "%%xmm%d", reg);	15045 names = names_xmm;

12723 break;	15046 break;

12724 case 256:	15047 case 256:

12725 sprintf (scratchbuf, "%%ymm%d", reg);	15048 names = names_ymm;

12726 break;	15049 break;

12727 default:	15050 default:

12728 abort ();	15051 abort ();

12729 }	15052 }

12730 oappend (scratchbuf + intel_syntax);	15053 oappend (names[reg]);

12731 }	15054 }

12732	15055

12733 static void	15056 static void

12734 OP_XMM_VexW (int bytemode, int sizeflag)	15057 OP_XMM_VexW (int bytemode, int sizeflag)

12735 {	15058 {

12736 /* Turn off the REX.W bit since it is used for swapping operands	15059 /* Turn off the REX.W bit since it is used for swapping operands

12737 now. */	15060 now. */

12738 rex &= ~REX_W;	15061 rex &= ~REX_W;

12739 OP_XMM (bytemode, sizeflag);	15062 OP_XMM (bytemode, sizeflag);

12740 }	15063 }

(...skipping 159 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
12900 {	15223 {

12901 case v_mode:	15224 case v_mode:

12902 if (intel_syntax)	15225 if (intel_syntax)

12903 goto skip;	15226 goto skip;

12904	15227

12905 USED_REX (REX_W);	15228 USED_REX (REX_W);

12906 if (sizeflag & SUFFIX_ALWAYS)	15229 if (sizeflag & SUFFIX_ALWAYS)

12907 {	15230 {

12908 if (rex & REX_W)	15231 if (rex & REX_W)

12909 *p++ = 'q';	15232 *p++ = 'q';

12910 else if (sizeflag & DFLAG)

12911 *p++ = 'l';

12912 else	15233 else

12913 » *p++ = 'w';	15234 » {

	15235 » if (sizeflag & DFLAG)

	15236 » » *p++ = 'l';

	15237 » else

	15238 » » *p++ = 'w';

	15239 » used_prefixes \|= (prefixes & PREFIX_DATA);

	15240 » }

12914 }	15241 }

12915 used_prefixes \|= (prefixes & PREFIX_DATA);

12916 break;	15242 break;

12917 default:	15243 default:

12918 oappend (INTERNAL_DISASSEMBLER_ERROR);	15244 oappend (INTERNAL_DISASSEMBLER_ERROR);

12919 break;	15245 break;

12920 }	15246 }

12921 mnemonicendp = p;	15247 mnemonicendp = p;

12922 *p = '\0';	15248 *p = '\0';

12923	15249

12924 skip:	15250 skip:

12925 OP_M (bytemode, sizeflag);	15251 OP_M (bytemode, sizeflag);

12926 }	15252 }

	15253

	15254 static void

	15255 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)

	15256 {

	15257 int reg;

	15258 const char **names;

	15259

	15260 /* Skip mod/rm byte. */

	15261 MODRM_CHECK;

	15262 codep++;

	15263

	15264 if (vex.w)

	15265 names = names64;

	15266 else

	15267 names = names32;

	15268

	15269 reg = modrm.rm;

	15270 USED_REX (REX_B);

	15271 if (rex & REX_B)

	15272 reg += 8;

	15273

	15274 oappend (names[reg]);

	15275 }

	15276

	15277 static void

	15278 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)

	15279 {

	15280 const char **names;

	15281

	15282 if (vex.w)

	15283 names = names64;

	15284 else

	15285 names = names32;

	15286

	15287 oappend (names[vex.register_specifier]);

	15288 }

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