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1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Redistribution and use in source and binary forms, with or without | 2 // Redistribution and use in source and binary forms, with or without |
3 // modification, are permitted provided that the following conditions are | 3 // modification, are permitted provided that the following conditions are |
4 // met: | 4 // met: |
5 // | 5 // |
6 // * Redistributions of source code must retain the above copyright | 6 // * Redistributions of source code must retain the above copyright |
7 // notice, this list of conditions and the following disclaimer. | 7 // notice, this list of conditions and the following disclaimer. |
8 // * Redistributions in binary form must reproduce the above | 8 // * Redistributions in binary form must reproduce the above |
9 // copyright notice, this list of conditions and the following | 9 // copyright notice, this list of conditions and the following |
10 // disclaimer in the documentation and/or other materials provided | 10 // disclaimer in the documentation and/or other materials provided |
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4048 } | 4048 } |
4049 | 4049 |
4050 | 4050 |
4051 void CodePatcher::EmitCondition(Condition cond) { | 4051 void CodePatcher::EmitCondition(Condition cond) { |
4052 Instr instr = Assembler::instr_at(masm_.pc_); | 4052 Instr instr = Assembler::instr_at(masm_.pc_); |
4053 instr = (instr & ~kCondMask) | cond; | 4053 instr = (instr & ~kCondMask) | cond; |
4054 masm_.emit(instr); | 4054 masm_.emit(instr); |
4055 } | 4055 } |
4056 | 4056 |
4057 | 4057 |
4058 void MacroAssembler::FlooringDiv(Register result, | 4058 void MacroAssembler::TruncatingDiv(Register result, |
4059 Register dividend, | 4059 Register dividend, |
4060 int32_t divisor) { | 4060 int32_t divisor) { |
4061 ASSERT(!dividend.is(result)); | 4061 ASSERT(!dividend.is(result)); |
4062 ASSERT(!dividend.is(ip)); | 4062 ASSERT(!dividend.is(ip)); |
4063 ASSERT(!result.is(ip)); | 4063 ASSERT(!result.is(ip)); |
4064 MultiplierAndShift ms(divisor); | 4064 MultiplierAndShift ms(divisor); |
4065 mov(ip, Operand(ms.multiplier())); | 4065 mov(ip, Operand(ms.multiplier())); |
4066 smull(ip, result, dividend, ip); | 4066 smull(ip, result, dividend, ip); |
4067 if (divisor > 0 && ms.multiplier() < 0) { | 4067 if (divisor > 0 && ms.multiplier() < 0) { |
4068 add(result, result, Operand(dividend)); | 4068 add(result, result, Operand(dividend)); |
4069 } | 4069 } |
4070 if (divisor < 0 && ms.multiplier() > 0) { | 4070 if (divisor < 0 && ms.multiplier() > 0) { |
4071 sub(result, result, Operand(dividend)); | 4071 sub(result, result, Operand(dividend)); |
4072 } | 4072 } |
4073 if (ms.shift() > 0) mov(result, Operand(result, ASR, ms.shift())); | 4073 if (ms.shift() > 0) mov(result, Operand(result, ASR, ms.shift())); |
| 4074 add(result, result, Operand(dividend, LSR, 31)); |
4074 } | 4075 } |
4075 | 4076 |
4076 | 4077 |
4077 } } // namespace v8::internal | 4078 } } // namespace v8::internal |
4078 | 4079 |
4079 #endif // V8_TARGET_ARCH_ARM | 4080 #endif // V8_TARGET_ARCH_ARM |
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