Enables a SIMD test for ARM.

runtime/vm/assembler_arm_test.cc

Index: runtime/vm/assembler_arm_test.cc
===================================================================
--- runtime/vm/assembler_arm_test.cc	(revision 25157)
+++ runtime/vm/assembler_arm_test.cc	(working copy)
@@ -2333,6 +2333,227 @@
 }
 
 
+ASSEMBLER_TEST_GENERATE(Veorq, assembler) {
+  if (CPUFeatures::neon_supported()) {
+    // Q0
+    __ LoadImmediate(R0, 0xaaaaaaab);
+    __ vmovsr(S0, R0);
+    __ vmovsr(S1, R0);
+    __ vmovsr(S2, R0);
+    __ vmovsr(S3, R0);
+
+    // Q1
+    __ LoadImmediate(R0, 0x55555555);
+    __ vmovsr(S4, R0);
+    __ vmovsr(S5, R0);
+    __ vmovsr(S6, R0);
+    __ vmovsr(S7, R0);
+
+    // Q2 = -2 -2 -2 -2
+    __ veorq(Q2, Q1, Q0);
+
+    __ vmovrs(R0, S8);
+    __ vmovrs(R1, S9);
+    __ vmovrs(R2, S10);
+    __ vmovrs(R3, S11);
+
+    __ add(R0, R0, ShifterOperand(R1));
+    __ add(R0, R0, ShifterOperand(R2));
+    __ add(R0, R0, ShifterOperand(R3));
+    __ bx(LR);
+  } else {
+    __ LoadImmediate(R0, -8);
+    __ bx(LR);
+  }
+}
+
+
+ASSEMBLER_TEST_RUN(Veorq, test) {
+  EXPECT(test != NULL);
+  typedef int (*Tst)();
+  EXPECT_EQ(-8, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(Vorrq, assembler) {
+  if (CPUFeatures::neon_supported()) {
+    // Q0
+    __ LoadImmediate(R0, 0xaaaaaaaa);
+    __ vmovsr(S0, R0);
+    __ vmovsr(S1, R0);
+    __ vmovsr(S2, R0);
+    __ vmovsr(S3, R0);
+
+    // Q1
+    __ LoadImmediate(R0, 0x55555555);
+    __ vmovsr(S4, R0);
+    __ vmovsr(S5, R0);
+    __ vmovsr(S6, R0);
+    __ vmovsr(S7, R0);
+
+    // Q2 = -1 -1 -1 -1
+    __ vorrq(Q2, Q1, Q0);
+
+    __ vmovrs(R0, S8);
+    __ vmovrs(R1, S9);
+    __ vmovrs(R2, S10);
+    __ vmovrs(R3, S11);
+
+    __ add(R0, R0, ShifterOperand(R1));
+    __ add(R0, R0, ShifterOperand(R2));
+    __ add(R0, R0, ShifterOperand(R3));
+    __ bx(LR);
+  } else {
+    __ LoadImmediate(R0, -4);
+    __ bx(LR);
+  }
+}
+
+
+ASSEMBLER_TEST_RUN(Vorrq, test) {
+  EXPECT(test != NULL);
+  typedef int (*Tst)();
+  EXPECT_EQ(-4, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(Vmovq, assembler) {
+  if (CPUFeatures::neon_supported()) {
+    // Q0
+    __ LoadSImmediate(S0, 1.0);
+    __ vmovs(S1, S0);
+    __ vmovs(S2, S0);
+    __ vmovs(S3, S0);
+
+    // Q0
+    __ LoadSImmediate(S4, -1.0);
+    __ vmovs(S5, S0);
+    __ vmovs(S6, S0);
+    __ vmovs(S7, S0);
+
+    // Q1 = Q2
+    __ vmovq(Q1, Q0);
+
+    __ vadds(S4, S4, S5);
+    __ vadds(S4, S4, S6);
+    __ vadds(S4, S4, S7);
+    __ vcvtis(S0, S4);
+    __ vmovrs(R0, S0);
+
+    __ bx(LR);
+  } else {
+    __ LoadImmediate(R0, 4);
+    __ bx(LR);
+  }
+}
+
+
+ASSEMBLER_TEST_RUN(Vmovq, test) {
+  EXPECT(test != NULL);
+  typedef int (*Tst)();
+  EXPECT_EQ(4, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(Vdupb, assembler) {
+  if (CPUFeatures::neon_supported()) {
+    __ LoadImmediate(R0, 0x00000000);
+    __ LoadImmediate(R1, 0x00ff0000);
+    __ vmovsr(S4, R0);
+    __ vmovsr(S5, R1);
+
+    // Should copy 0xff to each byte of Q0.
+    __ vdup(kByte, Q0, D2, 6);
+
+    __ vmovrs(R0, S0);
+    __ vmovrs(R1, S1);
+    __ vmovrs(R2, S2);
+    __ vmovrs(R3, S3);
+
+    __ add(R0, R0, ShifterOperand(R1));
+    __ add(R0, R0, ShifterOperand(R2));
+    __ add(R0, R0, ShifterOperand(R3));
+    __ bx(LR);
+  } else {
+    __ LoadImmediate(R0, -4);
+    __ bx(LR);
+  }
+}
+
+
+ASSEMBLER_TEST_RUN(Vdupb, test) {
+  EXPECT(test != NULL);
+  typedef int (*Tst)();
+  EXPECT_EQ(-4, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(Vduph, assembler) {
+  if (CPUFeatures::neon_supported()) {
+    __ LoadImmediate(R0, 0xffff0000);
+    __ LoadImmediate(R1, 0x00000000);
+    __ vmovsr(S4, R0);
+    __ vmovsr(S5, R1);
+
+    // Should copy 0xff to each byte of Q0.
+    __ vdup(kHalfword, Q0, D2, 1);
+
+    __ vmovrs(R0, S0);
+    __ vmovrs(R1, S1);
+    __ vmovrs(R2, S2);
+    __ vmovrs(R3, S3);
+
+    __ add(R0, R0, ShifterOperand(R1));
+    __ add(R0, R0, ShifterOperand(R2));
+    __ add(R0, R0, ShifterOperand(R3));
+    __ bx(LR);
+  } else {
+    __ LoadImmediate(R0, -4);
+    __ bx(LR);
+  }
+}
+
+
+ASSEMBLER_TEST_RUN(Vduph, test) {
+  EXPECT(test != NULL);
+  typedef int (*Tst)();
+  EXPECT_EQ(-4, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
+}
+
+
+ASSEMBLER_TEST_GENERATE(Vdupw, assembler) {
+  if (CPUFeatures::neon_supported()) {
+    __ LoadImmediate(R0, 0x00000000);
+    __ LoadImmediate(R1, 0xffffffff);
+    __ vmovsr(S4, R0);
+    __ vmovsr(S5, R1);
+
+    // Should copy 0xff to each byte of Q0.
+    __ vdup(kWord, Q0, D2, 1);
+
+    __ vmovrs(R0, S0);
+    __ vmovrs(R1, S1);
+    __ vmovrs(R2, S2);
+    __ vmovrs(R3, S3);
+
+    __ add(R0, R0, ShifterOperand(R1));
+    __ add(R0, R0, ShifterOperand(R2));
+    __ add(R0, R0, ShifterOperand(R3));
+    __ bx(LR);
+  } else {
+    __ LoadImmediate(R0, -4);
+    __ bx(LR);
+  }
+}
+
+
+ASSEMBLER_TEST_RUN(Vdupw, test) {
+  EXPECT(test != NULL);
+  typedef int (*Tst)();
+  EXPECT_EQ(-4, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
+}
+
+
 // Called from assembler_test.cc.
 // LR: return address.
 // R0: context.