Enables a SIMD test for ARM.

runtime/vm/assembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/assembler.h"
 #include "vm/simulator.h"
 #include "vm/runtime_entry.h"
@@ skipping 1261 matching lines @@
       ((static_cast<int32_t>(dd) >> 4)*B22) |
       ((static_cast<int32_t>(dn) & 0xf)*B16) |
       ((static_cast<int32_t>(dd) & 0xf)*B12) |
       ((static_cast<int32_t>(dn) >> 4)*B7) |
       ((static_cast<int32_t>(dm) >> 4)*B5) |
       (static_cast<int32_t>(dm) & 0xf);
   Emit(encoding);
 }
 
 
+void Assembler::vmovq(QRegister qd, QRegister qm) {
+  EmitSIMDqqq(B21 | B8 | B4, kByte, qd, qm, qm);
+}
+
+
 void Assembler::vaddqi(OperandSize sz,
                        QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B11, sz, qd, qn, qm);
 }
 
 
 void Assembler::vaddqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B11 | B10 | B8, kSWord, qd, qn, qm);
 }
 
@@ skipping 13 matching lines @@
                        QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B11 | B8 | B4, sz, qd, qn, qm);
 }
 
 
 void Assembler::vmulqs(QRegister qd, QRegister qn, QRegister qm) {
   EmitSIMDqqq(B24 | B11 | B10 | B8 | B4, kSWord, qd, qn, qm);
 }
 
 
+void Assembler::veorq(QRegister qd, QRegister qn, QRegister qm) {
+  EmitSIMDqqq(B24 | B8 | B4, kByte, qd, qn, qm);
+}
+
+
+void Assembler::vorrq(QRegister qd, QRegister qn, QRegister qm) {
+  EmitSIMDqqq(B21 | B8 | B4, kByte, qd, qn, qm);
+}
+
+
+void Assembler::vdup(OperandSize sz, QRegister qd, DRegister dm, int idx) {
+  ASSERT((sz != kDWord) && (sz != kSWord) && (sz != kWordPair));
+  int code = 0;
+
+  switch (sz) {
+    case kByte:
+    case kUnsignedByte: {
+      ASSERT((idx >= 0) && (idx < 8));
+      code = 1 | (idx << 1);
+      break;
+    }
+    case kHalfword:
+    case kUnsignedHalfword: {
+      ASSERT((idx >= 0) && (idx < 4));
+      code = 2 | (idx << 2);
+      break;
+    }
+    case kWord:
+    case kUnsignedWord: {
+      ASSERT((idx >= 0) && (idx < 2));
+      code = 4 | (idx << 3);
+      break;
+    }
+    default: {
+      break;
+    }
+  }
+
+  EmitSIMDddd(B24 | B23 | B11 | B10 | B6, kWordPair,
+              static_cast<DRegister>(qd * 2),
+              static_cast<DRegister>(code & 0xf),
+              dm);
+}
+
+
 void Assembler::vtbl(DRegister dd, DRegister dn, int len, DRegister dm) {
   ASSERT((len >= 1) && (len <= 4));
   EmitSIMDddd(B24 | B23 | B11 | ((len - 1) * B8), kWordPair, dd, dn, dm);
 }
 
 
 void Assembler::svc(uint32_t imm24, Condition cond) {
   ASSERT(cond != kNoCondition);
   ASSERT(imm24 < (1 << 24));
   int32_t encoding = (cond << kConditionShift) | B27 | B26 | B25 | B24 | imm24;
@@ skipping 1048 matching lines @@
 
 const char* Assembler::FpuRegisterName(FpuRegister reg) {
   ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
   return fpu_reg_names[reg];
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM