Enables a SIMD test for ARM.

runtime/vm/flow_graph_compiler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM.
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/flow_graph_compiler.h"
 
 #include "lib/error.h"
@@ skipping 1696 matching lines @@
       __ LoadFromOffset(kWord, destination.reg(), FP, source_offset);
     } else {
       ASSERT(destination.IsStackSlot());
       const intptr_t source_offset = source.ToStackSlotOffset();
       const intptr_t dest_offset = destination.ToStackSlotOffset();
       __ LoadFromOffset(kWord, TMP, FP, source_offset);
       __ StoreToOffset(kWord, TMP, FP, dest_offset);
     }
   } else if (source.IsFpuRegister()) {
     if (destination.IsFpuRegister()) {
-      DRegister dst = EvenDRegisterOf(destination.fpu_reg());
-      DRegister src = EvenDRegisterOf(source.fpu_reg());
-      __ vmovd(dst, src);
+      __ vmovq(destination.fpu_reg(), source.fpu_reg());
     } else {
       if (destination.IsDoubleStackSlot()) {
         const intptr_t dest_offset = destination.ToStackSlotOffset();
         DRegister src = EvenDRegisterOf(source.fpu_reg());
         __ StoreDToOffset(src, FP, dest_offset);
       } else {
         ASSERT(destination.IsQuadStackSlot());
-        UNIMPLEMENTED();
+        const intptr_t dest_offset = destination.ToStackSlotOffset();
+        DRegister dsrc0 = EvenDRegisterOf(source.fpu_reg());
+        DRegister dsrc1 = OddDRegisterOf(source.fpu_reg());
+        // TODO(zra): Write and use {Load,Store}Q{From,To}Offset(), which can
+        // use a single vld1/vst1 instruction.
+        __ StoreDToOffset(dsrc0, FP, dest_offset);
+        __ StoreDToOffset(dsrc1, FP, dest_offset + 2*kWordSize);
       }
     }
   } else if (source.IsDoubleStackSlot()) {
     if (destination.IsFpuRegister()) {
       const intptr_t dest_offset = source.ToStackSlotOffset();
       DRegister dst = EvenDRegisterOf(destination.fpu_reg());
       __ LoadDFromOffset(dst, FP, dest_offset);
     } else {
       ASSERT(destination.IsDoubleStackSlot());
       const intptr_t source_offset = source.ToStackSlotOffset();
       const intptr_t dest_offset = destination.ToStackSlotOffset();
       __ LoadDFromOffset(DTMP, FP, source_offset);
       __ StoreDToOffset(DTMP, FP, dest_offset);
     }
   } else if (source.IsQuadStackSlot()) {
-    UNIMPLEMENTED();
+    if (destination.IsFpuRegister()) {
+      const intptr_t dest_offset = source.ToStackSlotOffset();
+      DRegister dst0 = EvenDRegisterOf(destination.fpu_reg());
+      DRegister dst1 = OddDRegisterOf(destination.fpu_reg());
+      __ LoadDFromOffset(dst0, FP, dest_offset);
+      __ LoadDFromOffset(dst1, FP, dest_offset + 2*kWordSize);
+    } else {
+      ASSERT(destination.IsQuadStackSlot());
+      const intptr_t source_offset = source.ToStackSlotOffset();
+      const intptr_t dest_offset = destination.ToStackSlotOffset();
+      DRegister dtmp0 = DTMP;
+      DRegister dtmp1 = OddDRegisterOf(QTMP);
+      __ LoadDFromOffset(dtmp0, FP, source_offset);
+      __ LoadDFromOffset(dtmp1, FP, source_offset + 2*kWordSize);
+      __ StoreDToOffset(dtmp0, FP, dest_offset);
+      __ StoreDToOffset(dtmp1, FP, dest_offset + 2*kWordSize);
+    }
   } else {
     ASSERT(source.IsConstant());
     if (destination.IsRegister()) {
       const Object& constant = source.constant();
       __ LoadObject(destination.reg(), constant);
     } else {
       ASSERT(destination.IsStackSlot());
       const intptr_t dest_offset = destination.ToStackSlotOffset();
       __ LoadObject(TMP, source.constant());
       __ StoreToOffset(kWord, TMP, FP, dest_offset);
@@ skipping 146 matching lines @@
   DRegister dreg = EvenDRegisterOf(reg);
   __ vldrd(dreg, Address(SP, kDoubleSize, Address::PostIndex));
 }
 
 
 #undef __
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM