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1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include <limits.h> // For LONG_MIN, LONG_MAX. | 5 #include <limits.h> // For LONG_MIN, LONG_MAX. |
6 | 6 |
7 #if V8_TARGET_ARCH_ARM | 7 #if V8_TARGET_ARCH_ARM |
8 | 8 |
9 #include "src/base/bits.h" | 9 #include "src/base/bits.h" |
10 #include "src/base/division-by-constant.h" | 10 #include "src/base/division-by-constant.h" |
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348 if (!CpuFeatures::IsSupported(ARMv7) || predictable_code_size()) { | 348 if (!CpuFeatures::IsSupported(ARMv7) || predictable_code_size()) { |
349 int mask = (1 << (width + lsb)) - 1 - ((1 << lsb) - 1); | 349 int mask = (1 << (width + lsb)) - 1 - ((1 << lsb) - 1); |
350 bic(dst, src, Operand(mask)); | 350 bic(dst, src, Operand(mask)); |
351 } else { | 351 } else { |
352 Move(dst, src, cond); | 352 Move(dst, src, cond); |
353 bfc(dst, lsb, width, cond); | 353 bfc(dst, lsb, width, cond); |
354 } | 354 } |
355 } | 355 } |
356 | 356 |
357 | 357 |
358 void MacroAssembler::Usat(Register dst, int satpos, const Operand& src, | |
359 Condition cond) { | |
360 if (!CpuFeatures::IsSupported(ARMv7) || predictable_code_size()) { | |
361 DCHECK(!dst.is(pc) && !src.rm().is(pc)); | |
362 DCHECK((satpos >= 0) && (satpos <= 31)); | |
363 | |
364 // These asserts are required to ensure compatibility with the ARMv7 | |
365 // implementation. | |
366 DCHECK((src.shift_op() == ASR) || (src.shift_op() == LSL)); | |
367 DCHECK(src.rs().is(no_reg)); | |
368 | |
369 Label done; | |
370 int satval = (1 << satpos) - 1; | |
371 | |
372 if (cond != al) { | |
373 b(NegateCondition(cond), &done); // Skip saturate if !condition. | |
374 } | |
375 if (!(src.is_reg() && dst.is(src.rm()))) { | |
376 mov(dst, src); | |
377 } | |
378 tst(dst, Operand(~satval)); | |
379 b(eq, &done); | |
380 mov(dst, Operand::Zero(), LeaveCC, mi); // 0 if negative. | |
381 mov(dst, Operand(satval), LeaveCC, pl); // satval if positive. | |
382 bind(&done); | |
383 } else { | |
384 usat(dst, satpos, src, cond); | |
385 } | |
386 } | |
387 | |
388 | |
389 void MacroAssembler::Load(Register dst, | 358 void MacroAssembler::Load(Register dst, |
390 const MemOperand& src, | 359 const MemOperand& src, |
391 Representation r) { | 360 Representation r) { |
392 DCHECK(!r.IsDouble()); | 361 DCHECK(!r.IsDouble()); |
393 if (r.IsInteger8()) { | 362 if (r.IsInteger8()) { |
394 ldrsb(dst, src); | 363 ldrsb(dst, src); |
395 } else if (r.IsUInteger8()) { | 364 } else if (r.IsUInteger8()) { |
396 ldrb(dst, src); | 365 ldrb(dst, src); |
397 } else if (r.IsInteger16()) { | 366 } else if (r.IsInteger16()) { |
398 ldrsh(dst, src); | 367 ldrsh(dst, src); |
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3738 | 3707 |
3739 // Since both black and grey have a 1 in the first position and white does | 3708 // Since both black and grey have a 1 in the first position and white does |
3740 // not have a 1 there we only need to check one bit. | 3709 // not have a 1 there we only need to check one bit. |
3741 ldr(load_scratch, MemOperand(bitmap_scratch, MemoryChunk::kHeaderSize)); | 3710 ldr(load_scratch, MemOperand(bitmap_scratch, MemoryChunk::kHeaderSize)); |
3742 tst(mask_scratch, load_scratch); | 3711 tst(mask_scratch, load_scratch); |
3743 b(eq, value_is_white); | 3712 b(eq, value_is_white); |
3744 } | 3713 } |
3745 | 3714 |
3746 | 3715 |
3747 void MacroAssembler::ClampUint8(Register output_reg, Register input_reg) { | 3716 void MacroAssembler::ClampUint8(Register output_reg, Register input_reg) { |
3748 Usat(output_reg, 8, Operand(input_reg)); | 3717 usat(output_reg, 8, Operand(input_reg)); |
3749 } | 3718 } |
3750 | 3719 |
3751 | 3720 |
3752 void MacroAssembler::ClampDoubleToUint8(Register result_reg, | 3721 void MacroAssembler::ClampDoubleToUint8(Register result_reg, |
3753 DwVfpRegister input_reg, | 3722 DwVfpRegister input_reg, |
3754 LowDwVfpRegister double_scratch) { | 3723 LowDwVfpRegister double_scratch) { |
3755 Label done; | 3724 Label done; |
3756 | 3725 |
3757 // Handle inputs >= 255 (including +infinity). | 3726 // Handle inputs >= 255 (including +infinity). |
3758 Vmov(double_scratch, 255.0, result_reg); | 3727 Vmov(double_scratch, 255.0, result_reg); |
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4042 } | 4011 } |
4043 } | 4012 } |
4044 if (mag.shift > 0) mov(result, Operand(result, ASR, mag.shift)); | 4013 if (mag.shift > 0) mov(result, Operand(result, ASR, mag.shift)); |
4045 add(result, result, Operand(dividend, LSR, 31)); | 4014 add(result, result, Operand(dividend, LSR, 31)); |
4046 } | 4015 } |
4047 | 4016 |
4048 } // namespace internal | 4017 } // namespace internal |
4049 } // namespace v8 | 4018 } // namespace v8 |
4050 | 4019 |
4051 #endif // V8_TARGET_ARCH_ARM | 4020 #endif // V8_TARGET_ARCH_ARM |
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