OLD | NEW |
1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
(...skipping 1720 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1731 } | 1731 } |
1732 | 1732 |
1733 | 1733 |
1734 // Saturating instructions. | 1734 // Saturating instructions. |
1735 | 1735 |
1736 // Unsigned saturate. | 1736 // Unsigned saturate. |
1737 void Assembler::usat(Register dst, | 1737 void Assembler::usat(Register dst, |
1738 int satpos, | 1738 int satpos, |
1739 const Operand& src, | 1739 const Operand& src, |
1740 Condition cond) { | 1740 Condition cond) { |
1741 // v6 and above. | |
1742 DCHECK(CpuFeatures::IsSupported(ARMv7)); | |
1743 DCHECK(!dst.is(pc) && !src.rm_.is(pc)); | 1741 DCHECK(!dst.is(pc) && !src.rm_.is(pc)); |
1744 DCHECK((satpos >= 0) && (satpos <= 31)); | 1742 DCHECK((satpos >= 0) && (satpos <= 31)); |
1745 DCHECK((src.shift_op_ == ASR) || (src.shift_op_ == LSL)); | 1743 DCHECK((src.shift_op_ == ASR) || (src.shift_op_ == LSL)); |
1746 DCHECK(src.rs_.is(no_reg)); | 1744 DCHECK(src.rs_.is(no_reg)); |
1747 | 1745 |
1748 int sh = 0; | 1746 int sh = 0; |
1749 if (src.shift_op_ == ASR) { | 1747 if (src.shift_op_ == ASR) { |
1750 sh = 1; | 1748 sh = 1; |
1751 } | 1749 } |
1752 | 1750 |
(...skipping 2511 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
4264 DCHECK(is_uint12(offset)); | 4262 DCHECK(is_uint12(offset)); |
4265 instr_at_put(pc, SetLdrRegisterImmediateOffset(instr, offset)); | 4263 instr_at_put(pc, SetLdrRegisterImmediateOffset(instr, offset)); |
4266 } | 4264 } |
4267 } | 4265 } |
4268 | 4266 |
4269 | 4267 |
4270 } // namespace internal | 4268 } // namespace internal |
4271 } // namespace v8 | 4269 } // namespace v8 |
4272 | 4270 |
4273 #endif // V8_TARGET_ARCH_ARM | 4271 #endif // V8_TARGET_ARCH_ARM |
OLD | NEW |