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Issue 1974263002: [turbofan] ARM: Support shifted indexes in loads and stores (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 4 years, 7 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/compiler/code-generator.h" 5 #include "src/compiler/code-generator.h"
6 6
7 #include "src/arm/macro-assembler-arm.h" 7 #include "src/arm/macro-assembler-arm.h"
8 #include "src/ast/scopes.h" 8 #include "src/ast/scopes.h"
9 #include "src/compiler/code-generator-impl.h" 9 #include "src/compiler/code-generator-impl.h"
10 #include "src/compiler/gap-resolver.h" 10 #include "src/compiler/gap-resolver.h"
(...skipping 107 matching lines...) Expand 10 before | Expand all | Expand 10 after
118 } 118 }
119 119
120 MemOperand InputOffset(size_t* first_index) { 120 MemOperand InputOffset(size_t* first_index) {
121 const size_t index = *first_index; 121 const size_t index = *first_index;
122 switch (AddressingModeField::decode(instr_->opcode())) { 122 switch (AddressingModeField::decode(instr_->opcode())) {
123 case kMode_None: 123 case kMode_None:
124 case kMode_Operand2_I: 124 case kMode_Operand2_I:
125 case kMode_Operand2_R: 125 case kMode_Operand2_R:
126 case kMode_Operand2_R_ASR_I: 126 case kMode_Operand2_R_ASR_I:
127 case kMode_Operand2_R_ASR_R: 127 case kMode_Operand2_R_ASR_R:
128 case kMode_Operand2_R_LSL_I:
129 case kMode_Operand2_R_LSL_R: 128 case kMode_Operand2_R_LSL_R:
130 case kMode_Operand2_R_LSR_I: 129 case kMode_Operand2_R_LSR_I:
131 case kMode_Operand2_R_LSR_R: 130 case kMode_Operand2_R_LSR_R:
132 case kMode_Operand2_R_ROR_I: 131 case kMode_Operand2_R_ROR_I:
133 case kMode_Operand2_R_ROR_R: 132 case kMode_Operand2_R_ROR_R:
134 break; 133 break;
134 case kMode_Operand2_R_LSL_I:
135 *first_index += 3;
136 return MemOperand(InputRegister(index + 0), InputRegister(index + 1),
137 LSL, InputInt32(index + 2));
135 case kMode_Offset_RI: 138 case kMode_Offset_RI:
136 *first_index += 2; 139 *first_index += 2;
137 return MemOperand(InputRegister(index + 0), InputInt32(index + 1)); 140 return MemOperand(InputRegister(index + 0), InputInt32(index + 1));
138 case kMode_Offset_RR: 141 case kMode_Offset_RR:
139 *first_index += 2; 142 *first_index += 2;
140 return MemOperand(InputRegister(index + 0), InputRegister(index + 1)); 143 return MemOperand(InputRegister(index + 0), InputRegister(index + 1));
141 } 144 }
142 UNREACHABLE(); 145 UNREACHABLE();
143 return MemOperand(r0); 146 return MemOperand(r0);
144 } 147 }
(...skipping 965 matching lines...) Expand 10 before | Expand all | Expand 10 after
1110 DCHECK_EQ(LeaveCC, i.OutputSBit()); 1113 DCHECK_EQ(LeaveCC, i.OutputSBit());
1111 break; 1114 break;
1112 case kArmLdrb: 1115 case kArmLdrb:
1113 __ ldrb(i.OutputRegister(), i.InputOffset()); 1116 __ ldrb(i.OutputRegister(), i.InputOffset());
1114 DCHECK_EQ(LeaveCC, i.OutputSBit()); 1117 DCHECK_EQ(LeaveCC, i.OutputSBit());
1115 break; 1118 break;
1116 case kArmLdrsb: 1119 case kArmLdrsb:
1117 __ ldrsb(i.OutputRegister(), i.InputOffset()); 1120 __ ldrsb(i.OutputRegister(), i.InputOffset());
1118 DCHECK_EQ(LeaveCC, i.OutputSBit()); 1121 DCHECK_EQ(LeaveCC, i.OutputSBit());
1119 break; 1122 break;
1120 case kArmStrb: { 1123 case kArmStrb:
1121 size_t index = 0; 1124 __ strb(i.InputRegister(0), i.InputOffset(1));
1122 MemOperand operand = i.InputOffset(&index);
1123 __ strb(i.InputRegister(index), operand);
1124 DCHECK_EQ(LeaveCC, i.OutputSBit()); 1125 DCHECK_EQ(LeaveCC, i.OutputSBit());
1125 break; 1126 break;
1126 }
1127 case kArmLdrh: 1127 case kArmLdrh:
1128 __ ldrh(i.OutputRegister(), i.InputOffset()); 1128 __ ldrh(i.OutputRegister(), i.InputOffset());
1129 break; 1129 break;
1130 case kArmLdrsh: 1130 case kArmLdrsh:
1131 __ ldrsh(i.OutputRegister(), i.InputOffset()); 1131 __ ldrsh(i.OutputRegister(), i.InputOffset());
1132 break; 1132 break;
1133 case kArmStrh: { 1133 case kArmStrh:
1134 size_t index = 0; 1134 __ strh(i.InputRegister(0), i.InputOffset(1));
1135 MemOperand operand = i.InputOffset(&index);
1136 __ strh(i.InputRegister(index), operand);
1137 DCHECK_EQ(LeaveCC, i.OutputSBit()); 1135 DCHECK_EQ(LeaveCC, i.OutputSBit());
1138 break; 1136 break;
1139 }
1140 case kArmLdr: 1137 case kArmLdr:
1141 __ ldr(i.OutputRegister(), i.InputOffset()); 1138 __ ldr(i.OutputRegister(), i.InputOffset());
1142 break; 1139 break;
1143 case kArmStr: { 1140 case kArmStr:
1144 size_t index = 0; 1141 __ str(i.InputRegister(0), i.InputOffset(1));
1145 MemOperand operand = i.InputOffset(&index);
1146 __ str(i.InputRegister(index), operand);
1147 DCHECK_EQ(LeaveCC, i.OutputSBit()); 1142 DCHECK_EQ(LeaveCC, i.OutputSBit());
1148 break; 1143 break;
1149 }
1150 case kArmVldrF32: { 1144 case kArmVldrF32: {
1151 __ vldr(i.OutputFloat32Register(), i.InputOffset()); 1145 __ vldr(i.OutputFloat32Register(), i.InputOffset());
1152 DCHECK_EQ(LeaveCC, i.OutputSBit()); 1146 DCHECK_EQ(LeaveCC, i.OutputSBit());
1153 break; 1147 break;
1154 } 1148 }
1155 case kArmVstrF32: { 1149 case kArmVstrF32:
1156 size_t index = 0; 1150 __ vstr(i.InputFloat32Register(0), i.InputOffset(1));
1157 MemOperand operand = i.InputOffset(&index);
1158 __ vstr(i.InputFloat32Register(index), operand);
1159 DCHECK_EQ(LeaveCC, i.OutputSBit()); 1151 DCHECK_EQ(LeaveCC, i.OutputSBit());
1160 break; 1152 break;
1161 }
1162 case kArmVldrF64: 1153 case kArmVldrF64:
1163 __ vldr(i.OutputFloat64Register(), i.InputOffset()); 1154 __ vldr(i.OutputFloat64Register(), i.InputOffset());
1164 DCHECK_EQ(LeaveCC, i.OutputSBit()); 1155 DCHECK_EQ(LeaveCC, i.OutputSBit());
1165 break; 1156 break;
1166 case kArmVstrF64: { 1157 case kArmVstrF64:
1167 size_t index = 0; 1158 __ vstr(i.InputFloat64Register(0), i.InputOffset(1));
1168 MemOperand operand = i.InputOffset(&index);
1169 __ vstr(i.InputFloat64Register(index), operand);
1170 DCHECK_EQ(LeaveCC, i.OutputSBit()); 1159 DCHECK_EQ(LeaveCC, i.OutputSBit());
1171 break; 1160 break;
1172 }
1173 case kArmFloat32Max: { 1161 case kArmFloat32Max: {
1174 CpuFeatureScope scope(masm(), ARMv8); 1162 CpuFeatureScope scope(masm(), ARMv8);
1175 // (b < a) ? a : b 1163 // (b < a) ? a : b
1176 SwVfpRegister a = i.InputFloat32Register(0); 1164 SwVfpRegister a = i.InputFloat32Register(0);
1177 SwVfpRegister b = i.InputFloat32Register(1); 1165 SwVfpRegister b = i.InputFloat32Register(1);
1178 SwVfpRegister result = i.OutputFloat32Register(0); 1166 SwVfpRegister result = i.OutputFloat32Register(0);
1179 __ VFPCompareAndSetFlags(a, b); 1167 __ VFPCompareAndSetFlags(a, b);
1180 __ vsel(gt, result, a, b); 1168 __ vsel(gt, result, a, b);
1181 break; 1169 break;
1182 } 1170 }
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1695 padding_size -= v8::internal::Assembler::kInstrSize; 1683 padding_size -= v8::internal::Assembler::kInstrSize;
1696 } 1684 }
1697 } 1685 }
1698 } 1686 }
1699 1687
1700 #undef __ 1688 #undef __
1701 1689
1702 } // namespace compiler 1690 } // namespace compiler
1703 } // namespace internal 1691 } // namespace internal
1704 } // namespace v8 1692 } // namespace v8
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