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Side by Side Diff: src/x64/assembler-x64.cc

Issue 196893003: Introduce addp, idivp, imulp and subp for x64 port (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 9 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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103 // Create a code patcher. 103 // Create a code patcher.
104 CodePatcher patcher(pc_, code_size); 104 CodePatcher patcher(pc_, code_size);
105 105
106 // Add a label for checking the size of the code used for returning. 106 // Add a label for checking the size of the code used for returning.
107 #ifdef DEBUG 107 #ifdef DEBUG
108 Label check_codesize; 108 Label check_codesize;
109 patcher.masm()->bind(&check_codesize); 109 patcher.masm()->bind(&check_codesize);
110 #endif 110 #endif
111 111
112 // Patch the code. 112 // Patch the code.
113 patcher.masm()->movp(kScratchRegister, target, Assembler::RelocInfoNone()); 113 patcher.masm()->movp(kScratchRegister, reinterpret_cast<void*>(target),
114 Assembler::RelocInfoNone());
114 patcher.masm()->call(kScratchRegister); 115 patcher.masm()->call(kScratchRegister);
115 116
116 // Check that the size of the code generated is as expected. 117 // Check that the size of the code generated is as expected.
117 ASSERT_EQ(Assembler::kCallSequenceLength, 118 ASSERT_EQ(Assembler::kCallSequenceLength,
118 patcher.masm()->SizeOfCodeGeneratedSince(&check_codesize)); 119 patcher.masm()->SizeOfCodeGeneratedSince(&check_codesize));
119 120
120 // Add the requested number of int3 instructions after the call. 121 // Add the requested number of int3 instructions after the call.
121 for (int i = 0; i < guard_bytes; i++) { 122 for (int i = 0; i < guard_bytes; i++) {
122 patcher.masm()->int3(); 123 patcher.masm()->int3();
123 } 124 }
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1001 emit(0); 1002 emit(0);
1002 } 1003 }
1003 1004
1004 1005
1005 void Assembler::hlt() { 1006 void Assembler::hlt() {
1006 EnsureSpace ensure_space(this); 1007 EnsureSpace ensure_space(this);
1007 emit(0xF4); 1008 emit(0xF4);
1008 } 1009 }
1009 1010
1010 1011
1011 void Assembler::idivq(Register src) { 1012 void Assembler::emit_idiv(Register src, int size) {
1012 EnsureSpace ensure_space(this); 1013 EnsureSpace ensure_space(this);
1013 emit_rex_64(src); 1014 emit_rex(src, size);
1014 emit(0xF7); 1015 emit(0xF7);
1015 emit_modrm(0x7, src); 1016 emit_modrm(0x7, src);
1016 } 1017 }
1017 1018
1018 1019
1019 void Assembler::idivl(Register src) { 1020 void Assembler::emit_imul(Register src, int size) {
1020 EnsureSpace ensure_space(this); 1021 EnsureSpace ensure_space(this);
1021 emit_optional_rex_32(src); 1022 emit_rex(src, size);
1022 emit(0xF7);
1023 emit_modrm(0x7, src);
1024 }
1025
1026
1027 void Assembler::imul(Register src) {
1028 EnsureSpace ensure_space(this);
1029 emit_rex_64(src);
1030 emit(0xF7); 1023 emit(0xF7);
1031 emit_modrm(0x5, src); 1024 emit_modrm(0x5, src);
1032 } 1025 }
1033 1026
1034 1027
1035 void Assembler::imul(Register dst, Register src) { 1028 void Assembler::emit_imul(Register dst, Register src, int size) {
1036 EnsureSpace ensure_space(this); 1029 EnsureSpace ensure_space(this);
1037 emit_rex_64(dst, src); 1030 emit_rex(dst, src, size);
1038 emit(0x0F); 1031 emit(0x0F);
1039 emit(0xAF); 1032 emit(0xAF);
1040 emit_modrm(dst, src); 1033 emit_modrm(dst, src);
1041 } 1034 }
1042 1035
1043 1036
1044 void Assembler::imul(Register dst, const Operand& src) { 1037 void Assembler::emit_imul(Register dst, const Operand& src, int size) {
1045 EnsureSpace ensure_space(this); 1038 EnsureSpace ensure_space(this);
1046 emit_rex_64(dst, src); 1039 emit_rex(dst, src, size);
1047 emit(0x0F); 1040 emit(0x0F);
1048 emit(0xAF); 1041 emit(0xAF);
1049 emit_operand(dst, src); 1042 emit_operand(dst, src);
1050 } 1043 }
1051 1044
1052 1045
1053 void Assembler::imul(Register dst, Register src, Immediate imm) { 1046 void Assembler::emit_imul(Register dst, Register src, Immediate imm, int size) {
1054 EnsureSpace ensure_space(this); 1047 EnsureSpace ensure_space(this);
1055 emit_rex_64(dst, src); 1048 emit_rex(dst, src, size);
1056 if (is_int8(imm.value_)) { 1049 if (is_int8(imm.value_)) {
1057 emit(0x6B); 1050 emit(0x6B);
1058 emit_modrm(dst, src); 1051 emit_modrm(dst, src);
1059 emit(imm.value_);
1060 } else {
1061 emit(0x69);
1062 emit_modrm(dst, src);
1063 emitl(imm.value_);
1064 }
1065 }
1066
1067
1068 void Assembler::imull(Register src) {
1069 EnsureSpace ensure_space(this);
1070 emit_optional_rex_32(src);
1071 emit(0xF7);
1072 emit_modrm(0x5, src);
1073 }
1074
1075
1076 void Assembler::imull(Register dst, Register src) {
1077 EnsureSpace ensure_space(this);
1078 emit_optional_rex_32(dst, src);
1079 emit(0x0F);
1080 emit(0xAF);
1081 emit_modrm(dst, src);
1082 }
1083
1084
1085 void Assembler::imull(Register dst, const Operand& src) {
1086 EnsureSpace ensure_space(this);
1087 emit_optional_rex_32(dst, src);
1088 emit(0x0F);
1089 emit(0xAF);
1090 emit_operand(dst, src);
1091 }
1092
1093
1094 void Assembler::imull(Register dst, Register src, Immediate imm) {
1095 EnsureSpace ensure_space(this);
1096 emit_optional_rex_32(dst, src);
1097 if (is_int8(imm.value_)) {
1098 emit(0x6B);
1099 emit_modrm(dst, src);
1100 emit(imm.value_); 1052 emit(imm.value_);
1101 } else { 1053 } else {
1102 emit(0x69); 1054 emit(0x69);
1103 emit_modrm(dst, src); 1055 emit_modrm(dst, src);
1104 emitl(imm.value_); 1056 emitl(imm.value_);
1105 } 1057 }
1106 } 1058 }
1107 1059
1108 1060
1109 void Assembler::incq(Register dst) { 1061 void Assembler::incq(Register dst) {
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3227 3179
3228 3180
3229 bool RelocInfo::IsInConstantPool() { 3181 bool RelocInfo::IsInConstantPool() {
3230 return false; 3182 return false;
3231 } 3183 }
3232 3184
3233 3185
3234 } } // namespace v8::internal 3186 } } // namespace v8::internal
3235 3187
3236 #endif // V8_TARGET_ARCH_X64 3188 #endif // V8_TARGET_ARCH_X64
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