runtime/vm/disassembler_arm.cc - Issue 19678020: Implements ARM SIMD comparison instructions.

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Unified Diff: runtime/vm/disassembler_arm.cc

Issue 19678020: Implements ARM SIMD comparison instructions. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/

Patch Set: Created 7 years, 5 months ago

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Index: runtime/vm/disassembler_arm.cc

===================================================================

--- runtime/vm/disassembler_arm.cc (revision 25188)

+++ runtime/vm/disassembler_arm.cc (working copy)

@@ -1326,6 +1326,9 @@

(instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 2)) {

Format(instr, "veorq 'qd, 'qn, 'qm");

} else if ((instr->Bits(8, 4) == 1) && (instr->Bit(4) == 1) &&

+ (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 0)) {

+ Format(instr, "vornq 'qd, 'qn, 'qm");

+ } else if ((instr->Bits(8, 4) == 1) && (instr->Bit(4) == 1) &&

(instr->Bits(20, 2) == 2) && (instr->Bits(23, 2) == 0)) {

if (instr->QmField() == instr->QnField()) {

Format(instr, "vmovq 'qd, 'qm");

@@ -1345,6 +1348,30 @@

} else {

Unknown(instr);

}

+ } else if ((instr->Bits(8, 4) == 8) && (instr->Bit(4) == 1) &&

+ (instr->Bits(23, 2) == 2)) {

+ Format(instr, "vceqq'sz 'qd, 'qn, 'qm");

+ } else if ((instr->Bits(8, 4) == 14) && (instr->Bit(4) == 0) &&

+ (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 0)) {

+ Format(instr, "vceqqs 'qd, 'qn, 'qm");

+ } else if ((instr->Bits(8, 4) == 3) && (instr->Bit(4) == 1) &&

+ (instr->Bits(23, 2) == 0)) {

+ Format(instr, "vcgeq'sz 'qd, 'qn, 'qm");

+ } else if ((instr->Bits(8, 4) == 3) && (instr->Bit(4) == 1) &&

+ (instr->Bits(23, 2) == 2)) {

+ Format(instr, "vcugeq'sz 'qd, 'qn, 'qm");

+ } else if ((instr->Bits(8, 4) == 14) && (instr->Bit(4) == 0) &&

+ (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 2)) {

+ Format(instr, "vcgeqs 'qd, 'qn, 'qm");

+ } else if ((instr->Bits(8, 4) == 3) && (instr->Bit(4) == 0) &&

+ (instr->Bits(23, 2) == 0)) {

+ Format(instr, "vcgtq'sz 'qd, 'qn, 'qm");

+ } else if ((instr->Bits(8, 4) == 3) && (instr->Bit(4) == 0) &&

+ (instr->Bits(23, 2) == 2)) {

+ Format(instr, "vcugtq'sz 'qd, 'qn, 'qm");

+ } else if ((instr->Bits(8, 4) == 14) && (instr->Bit(4) == 0) &&

+ (instr->Bits(20, 2) == 2) && (instr->Bits(23, 2) == 2)) {

+ Format(instr, "vcgtqs 'qd, 'qn, 'qm");

} else {

Unknown(instr);

}

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