Implements ARM SIMD comparison instructions.

runtime/vm/disassembler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/disassembler.h"
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM.
 #if defined(TARGET_ARCH_ARM)
 #include "platform/assert.h"
 
@@ skipping 1308 matching lines @@
     } else if ((instr->Bits(8, 4) == 9) && (instr->Bit(4) == 1) &&
                (instr->Bits(23, 2) == 0)) {
       Format(instr, "vmulq'sz 'qd, 'qn, 'qm");
     } else if ((instr->Bits(8, 4) == 13) && (instr->Bit(4) == 1) &&
                (instr->Bits(23, 2) == 2) && (instr->Bit(21) == 0)) {
       Format(instr, "vmulqs 'qd, 'qn, 'qm");
     } else if ((instr->Bits(8, 4) == 1) && (instr->Bit(4) == 1) &&
                (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 2)) {
       Format(instr, "veorq 'qd, 'qn, 'qm");
     } else if ((instr->Bits(8, 4) == 1) && (instr->Bit(4) == 1) &&
+               (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 0)) {
+      Format(instr, "vornq 'qd, 'qn, 'qm");
+    } else if ((instr->Bits(8, 4) == 1) && (instr->Bit(4) == 1) &&
                (instr->Bits(20, 2) == 2) && (instr->Bits(23, 2) == 0)) {
       if (instr->QmField() == instr->QnField()) {
         Format(instr, "vmovq 'qd, 'qm");
       } else {
         Format(instr, "vorrq 'qd, 'qm");
       }
     } else if ((instr->Bits(8, 4) == 12) && (instr->Bit(4) == 0) &&
                (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) &&
                (instr->Bit(7) == 0)) {
       int32_t imm4 = instr->Bits(16, 4);
       if (imm4 & 1) {
         Format(instr, "vdupb 'qd, 'dm['imm4_vdup]");
       } else if (imm4 & 2) {
         Format(instr, "vduph 'qd, 'dm['imm4_vdup]");
       } else if (imm4 & 4) {
         Format(instr, "vdupw 'qd, 'dm['imm4_vdup]");
       } else {
         Unknown(instr);
       }
+    } else if ((instr->Bits(8, 4) == 8) && (instr->Bit(4) == 1) &&
+               (instr->Bits(23, 2) == 2)) {
+      Format(instr, "vceqq'sz 'qd, 'qn, 'qm");
+    } else if ((instr->Bits(8, 4) == 14) && (instr->Bit(4) == 0) &&
+               (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 0)) {
+      Format(instr, "vceqqs 'qd, 'qn, 'qm");
+    } else if ((instr->Bits(8, 4) == 3) && (instr->Bit(4) == 1) &&
+               (instr->Bits(23, 2) == 0)) {
+      Format(instr, "vcgeq'sz 'qd, 'qn, 'qm");
+    } else if ((instr->Bits(8, 4) == 3) && (instr->Bit(4) == 1) &&
+               (instr->Bits(23, 2) == 2)) {
+      Format(instr, "vcugeq'sz 'qd, 'qn, 'qm");
+    } else if ((instr->Bits(8, 4) == 14) && (instr->Bit(4) == 0) &&
+               (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 2)) {
+      Format(instr, "vcgeqs 'qd, 'qn, 'qm");
+    } else if ((instr->Bits(8, 4) == 3) && (instr->Bit(4) == 0) &&
+               (instr->Bits(23, 2) == 0)) {
+      Format(instr, "vcgtq'sz 'qd, 'qn, 'qm");
+    } else if ((instr->Bits(8, 4) == 3) && (instr->Bit(4) == 0) &&
+               (instr->Bits(23, 2) == 2)) {
+      Format(instr, "vcugtq'sz 'qd, 'qn, 'qm");
+    } else if ((instr->Bits(8, 4) == 14) && (instr->Bit(4) == 0) &&
+               (instr->Bits(20, 2) == 2) && (instr->Bits(23, 2) == 2)) {
+      Format(instr, "vcgtqs 'qd, 'qn, 'qm");
     } else {
       Unknown(instr);
     }
   } else {
     if ((instr->Bits(23, 2) == 3) && (instr->Bits(20, 2) == 3) &&
         (instr->Bits(10, 2) == 2) && (instr->Bit(4) == 0)) {
       Format(instr, "vtbl 'dd, 'dtbllist, 'dm");
     } else {
       Unknown(instr);
     }
@@ skipping 96 matching lines @@
                                   human_buffer,
                                   sizeof(human_buffer),
                                   pc);
     pc += instruction_length;
   }
 }
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM