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Issue 19678020: Implements ARM SIMD comparison instructions. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 7 years, 5 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/globals.h" 5 #include "vm/globals.h"
6 #if defined(TARGET_ARCH_ARM) 6 #if defined(TARGET_ARCH_ARM)
7 7
8 #include "vm/assembler.h" 8 #include "vm/assembler.h"
9 #include "vm/os.h" 9 #include "vm/os.h"
10 #include "vm/unit_test.h" 10 #include "vm/unit_test.h"
(...skipping 2357 matching lines...) Expand 10 before | Expand all | Expand 10 after
2368 } 2368 }
2369 2369
2370 2370
2371 ASSEMBLER_TEST_RUN(Veorq, test) { 2371 ASSEMBLER_TEST_RUN(Veorq, test) {
2372 EXPECT(test != NULL); 2372 EXPECT(test != NULL);
2373 typedef int (*Tst)(); 2373 typedef int (*Tst)();
2374 EXPECT_EQ(-8, EXECUTE_TEST_CODE_INT32(Tst, test->entry())); 2374 EXPECT_EQ(-8, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
2375 } 2375 }
2376 2376
2377 2377
2378 ASSEMBLER_TEST_GENERATE(Vornq, assembler) {
2379 if (CPUFeatures::neon_supported()) {
2380 // Q0
2381 __ LoadImmediate(R0, 0xfffffff0);
2382 __ vmovsr(S0, R0);
2383 __ vmovsr(S1, R0);
2384 __ vmovsr(S2, R0);
2385 __ vmovsr(S3, R0);
2386
2387 // Q1
2388 __ LoadImmediate(R0, 0);
2389 __ vmovsr(S4, R0);
2390 __ vmovsr(S5, R0);
2391 __ vmovsr(S6, R0);
2392 __ vmovsr(S7, R0);
2393
2394 // Q2 = 15 15 15 15
2395 __ vornq(Q2, Q1, Q0);
2396
2397 __ vmovrs(R0, S8);
2398 __ vmovrs(R1, S9);
2399 __ vmovrs(R2, S10);
2400 __ vmovrs(R3, S11);
2401
2402 __ add(R0, R0, ShifterOperand(R1));
2403 __ add(R0, R0, ShifterOperand(R2));
2404 __ add(R0, R0, ShifterOperand(R3));
2405 __ bx(LR);
2406 } else {
2407 __ LoadImmediate(R0, 60);
2408 __ bx(LR);
2409 }
2410 }
2411
2412
2413 ASSEMBLER_TEST_RUN(Vornq, test) {
2414 EXPECT(test != NULL);
2415 typedef int (*Tst)();
2416 EXPECT_EQ(60, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
2417 }
2418
2419
2378 ASSEMBLER_TEST_GENERATE(Vorrq, assembler) { 2420 ASSEMBLER_TEST_GENERATE(Vorrq, assembler) {
2379 if (CPUFeatures::neon_supported()) { 2421 if (CPUFeatures::neon_supported()) {
2380 // Q0 2422 // Q0
2381 __ LoadImmediate(R0, 0xaaaaaaaa); 2423 __ LoadImmediate(R0, 0xaaaaaaaa);
2382 __ vmovsr(S0, R0); 2424 __ vmovsr(S0, R0);
2383 __ vmovsr(S1, R0); 2425 __ vmovsr(S1, R0);
2384 __ vmovsr(S2, R0); 2426 __ vmovsr(S2, R0);
2385 __ vmovsr(S3, R0); 2427 __ vmovsr(S3, R0);
2386 2428
2387 // Q1 2429 // Q1
(...skipping 159 matching lines...) Expand 10 before | Expand all | Expand 10 after
2547 } 2589 }
2548 2590
2549 2591
2550 ASSEMBLER_TEST_RUN(Vdupw, test) { 2592 ASSEMBLER_TEST_RUN(Vdupw, test) {
2551 EXPECT(test != NULL); 2593 EXPECT(test != NULL);
2552 typedef int (*Tst)(); 2594 typedef int (*Tst)();
2553 EXPECT_EQ(-4, EXECUTE_TEST_CODE_INT32(Tst, test->entry())); 2595 EXPECT_EQ(-4, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
2554 } 2596 }
2555 2597
2556 2598
2599 ASSEMBLER_TEST_GENERATE(Vceqqi32, assembler) {
2600 if (CPUFeatures::neon_supported()) {
2601 __ mov(R0, ShifterOperand(1));
2602 __ vmovsr(S0, R0);
2603 __ mov(R0, ShifterOperand(2));
2604 __ vmovsr(S1, R0);
2605 __ mov(R0, ShifterOperand(3));
2606 __ vmovsr(S2, R0);
2607 __ mov(R0, ShifterOperand(4));
2608 __ vmovsr(S3, R0);
2609 __ mov(R0, ShifterOperand(1));
2610 __ vmovsr(S4, R0);
2611 __ mov(R0, ShifterOperand(20));
2612 __ vmovsr(S5, R0);
2613 __ mov(R0, ShifterOperand(3));
2614 __ vmovsr(S6, R0);
2615 __ mov(R0, ShifterOperand(40));
2616 __ vmovsr(S7, R0);
2617
2618 __ vceqqi(kWord, Q2, Q1, Q0);
2619
2620 __ vmovrs(R0, S8);
2621 __ vmovrs(R1, S9);
2622 __ vmovrs(R2, S10);
2623 __ vmovrs(R3, S11);
2624
2625 __ add(R0, R0, ShifterOperand(R1));
2626 __ add(R0, R0, ShifterOperand(R2));
2627 __ add(R0, R0, ShifterOperand(R3));
2628 __ bx(LR);
2629 } else {
2630 __ LoadImmediate(R0, -2);
2631 __ bx(LR);
2632 }
2633 }
2634
2635
2636 ASSEMBLER_TEST_RUN(Vceqqi32, test) {
2637 EXPECT(test != NULL);
2638 typedef int (*Tst)();
2639 EXPECT_EQ(-2, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
2640 }
2641
2642
2643 ASSEMBLER_TEST_GENERATE(Vceqqs, assembler) {
2644 if (CPUFeatures::neon_supported()) {
2645 __ LoadSImmediate(S0, 1.0);
2646 __ LoadSImmediate(S1, 2.0);
2647 __ LoadSImmediate(S2, 3.0);
2648 __ LoadSImmediate(S3, 4.0);
2649 __ LoadSImmediate(S4, 1.0);
2650 __ LoadSImmediate(S5, 4.0);
2651 __ LoadSImmediate(S6, 3.0);
2652 __ LoadSImmediate(S7, 8.0);
2653
2654 __ vceqqs(Q2, Q1, Q0);
2655
2656 __ vmovrs(R0, S8);
2657 __ vmovrs(R1, S9);
2658 __ vmovrs(R2, S10);
2659 __ vmovrs(R3, S11);
2660
2661 __ add(R0, R0, ShifterOperand(R1));
2662 __ add(R0, R0, ShifterOperand(R2));
2663 __ add(R0, R0, ShifterOperand(R3));
2664 __ bx(LR);
2665 } else {
2666 __ LoadImmediate(R0, -2);
2667 __ bx(LR);
2668 }
2669 }
2670
2671
2672 ASSEMBLER_TEST_RUN(Vceqqs, test) {
2673 EXPECT(test != NULL);
2674 typedef int (*Tst)();
2675 EXPECT_EQ(-2, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
2676 }
2677
2678
2679 ASSEMBLER_TEST_GENERATE(Vcgeqi32, assembler) {
2680 if (CPUFeatures::neon_supported()) {
2681 __ mov(R0, ShifterOperand(1));
2682 __ vmovsr(S0, R0);
2683 __ mov(R0, ShifterOperand(2));
2684 __ vmovsr(S1, R0);
2685 __ mov(R0, ShifterOperand(3));
2686 __ vmovsr(S2, R0);
2687 __ mov(R0, ShifterOperand(4));
2688 __ vmovsr(S3, R0);
2689 __ mov(R0, ShifterOperand(1));
2690 __ vmovsr(S4, R0);
2691 __ mov(R0, ShifterOperand(1));
2692 __ vmovsr(S5, R0);
2693 __ mov(R0, ShifterOperand(3));
2694 __ vmovsr(S6, R0);
2695 __ mov(R0, ShifterOperand(1));
2696 __ vmovsr(S7, R0);
2697
2698 __ vcgeqi(kWord, Q2, Q1, Q0);
2699
2700 __ vmovrs(R0, S8);
2701 __ vmovrs(R1, S9);
2702 __ vmovrs(R2, S10);
2703 __ vmovrs(R3, S11);
2704
2705 __ add(R0, R0, ShifterOperand(R1));
2706 __ add(R0, R0, ShifterOperand(R2));
2707 __ add(R0, R0, ShifterOperand(R3));
2708 __ bx(LR);
2709 } else {
2710 __ LoadImmediate(R0, -2);
2711 __ bx(LR);
2712 }
2713 }
2714
2715
2716 ASSEMBLER_TEST_RUN(Vcgeqi32, test) {
2717 EXPECT(test != NULL);
2718 typedef int (*Tst)();
2719 EXPECT_EQ(-2, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
2720 }
2721
2722
2723 ASSEMBLER_TEST_GENERATE(Vcugeqi32, assembler) {
2724 if (CPUFeatures::neon_supported()) {
2725 __ mov(R0, ShifterOperand(1));
2726 __ vmovsr(S0, R0);
2727 __ mov(R0, ShifterOperand(2));
2728 __ vmovsr(S1, R0);
2729 __ mov(R0, ShifterOperand(3));
2730 __ vmovsr(S2, R0);
2731 __ mov(R0, ShifterOperand(4));
2732 __ vmovsr(S3, R0);
2733 __ LoadImmediate(R0, -1);
2734 __ vmovsr(S4, R0);
2735 __ mov(R0, ShifterOperand(1));
2736 __ vmovsr(S5, R0);
2737 __ LoadImmediate(R0, -3);
2738 __ vmovsr(S6, R0);
2739 __ mov(R0, ShifterOperand(1));
2740 __ vmovsr(S7, R0);
2741
2742 __ vcugeqi(kWord, Q2, Q1, Q0);
2743
2744 __ vmovrs(R0, S8);
2745 __ vmovrs(R1, S9);
2746 __ vmovrs(R2, S10);
2747 __ vmovrs(R3, S11);
2748
2749 __ add(R0, R0, ShifterOperand(R1));
2750 __ add(R0, R0, ShifterOperand(R2));
2751 __ add(R0, R0, ShifterOperand(R3));
2752 __ bx(LR);
2753 } else {
2754 __ LoadImmediate(R0, -2);
2755 __ bx(LR);
2756 }
2757 }
2758
2759
2760 ASSEMBLER_TEST_RUN(Vcugeqi32, test) {
2761 EXPECT(test != NULL);
2762 typedef int (*Tst)();
2763 EXPECT_EQ(-2, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
2764 }
2765
2766
2767 ASSEMBLER_TEST_GENERATE(Vcgeqs, assembler) {
2768 if (CPUFeatures::neon_supported()) {
2769 __ LoadSImmediate(S0, 1.0);
2770 __ LoadSImmediate(S1, 2.0);
2771 __ LoadSImmediate(S2, 3.0);
2772 __ LoadSImmediate(S3, 4.0);
2773 __ LoadSImmediate(S4, 1.0);
2774 __ LoadSImmediate(S5, 1.0);
2775 __ LoadSImmediate(S6, 3.0);
2776 __ LoadSImmediate(S7, 1.0);
2777
2778 __ vcgeqs(Q2, Q1, Q0);
2779
2780 __ vmovrs(R0, S8);
2781 __ vmovrs(R1, S9);
2782 __ vmovrs(R2, S10);
2783 __ vmovrs(R3, S11);
2784
2785 __ add(R0, R0, ShifterOperand(R1));
2786 __ add(R0, R0, ShifterOperand(R2));
2787 __ add(R0, R0, ShifterOperand(R3));
2788 __ bx(LR);
2789 } else {
2790 __ LoadImmediate(R0, -2);
2791 __ bx(LR);
2792 }
2793 }
2794
2795
2796 ASSEMBLER_TEST_RUN(Vcgeqs, test) {
2797 EXPECT(test != NULL);
2798 typedef int (*Tst)();
2799 EXPECT_EQ(-2, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
2800 }
2801
2802
2803 ASSEMBLER_TEST_GENERATE(Vcgtqi32, assembler) {
2804 if (CPUFeatures::neon_supported()) {
2805 __ mov(R0, ShifterOperand(1));
2806 __ vmovsr(S0, R0);
2807 __ mov(R0, ShifterOperand(2));
2808 __ vmovsr(S1, R0);
2809 __ mov(R0, ShifterOperand(3));
2810 __ vmovsr(S2, R0);
2811 __ mov(R0, ShifterOperand(4));
2812 __ vmovsr(S3, R0);
2813 __ mov(R0, ShifterOperand(2));
2814 __ vmovsr(S4, R0);
2815 __ mov(R0, ShifterOperand(1));
2816 __ vmovsr(S5, R0);
2817 __ mov(R0, ShifterOperand(4));
2818 __ vmovsr(S6, R0);
2819 __ mov(R0, ShifterOperand(1));
2820 __ vmovsr(S7, R0);
2821
2822 __ vcgtqi(kWord, Q2, Q1, Q0);
2823
2824 __ vmovrs(R0, S8);
2825 __ vmovrs(R1, S9);
2826 __ vmovrs(R2, S10);
2827 __ vmovrs(R3, S11);
2828
2829 __ add(R0, R0, ShifterOperand(R1));
2830 __ add(R0, R0, ShifterOperand(R2));
2831 __ add(R0, R0, ShifterOperand(R3));
2832 __ bx(LR);
2833 } else {
2834 __ LoadImmediate(R0, -2);
2835 __ bx(LR);
2836 }
2837 }
2838
2839
2840 ASSEMBLER_TEST_RUN(Vcgtqi32, test) {
2841 EXPECT(test != NULL);
2842 typedef int (*Tst)();
2843 EXPECT_EQ(-2, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
2844 }
2845
2846
2847 ASSEMBLER_TEST_GENERATE(Vcugtqi32, assembler) {
2848 if (CPUFeatures::neon_supported()) {
2849 __ mov(R0, ShifterOperand(1));
2850 __ vmovsr(S0, R0);
2851 __ mov(R0, ShifterOperand(2));
2852 __ vmovsr(S1, R0);
2853 __ mov(R0, ShifterOperand(3));
2854 __ vmovsr(S2, R0);
2855 __ mov(R0, ShifterOperand(4));
2856 __ vmovsr(S3, R0);
2857 __ LoadImmediate(R0, -1);
2858 __ vmovsr(S4, R0);
2859 __ mov(R0, ShifterOperand(1));
2860 __ vmovsr(S5, R0);
2861 __ LoadImmediate(R0, -3);
2862 __ vmovsr(S6, R0);
2863 __ mov(R0, ShifterOperand(1));
2864 __ vmovsr(S7, R0);
2865
2866 __ vcugtqi(kWord, Q2, Q1, Q0);
2867
2868 __ vmovrs(R0, S8);
2869 __ vmovrs(R1, S9);
2870 __ vmovrs(R2, S10);
2871 __ vmovrs(R3, S11);
2872
2873 __ add(R0, R0, ShifterOperand(R1));
2874 __ add(R0, R0, ShifterOperand(R2));
2875 __ add(R0, R0, ShifterOperand(R3));
2876 __ bx(LR);
2877 } else {
2878 __ LoadImmediate(R0, -2);
2879 __ bx(LR);
2880 }
2881 }
2882
2883
2884 ASSEMBLER_TEST_RUN(Vcugtqi32, test) {
2885 EXPECT(test != NULL);
2886 typedef int (*Tst)();
2887 EXPECT_EQ(-2, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
2888 }
2889
2890
2891 ASSEMBLER_TEST_GENERATE(Vcgtqs, assembler) {
2892 if (CPUFeatures::neon_supported()) {
2893 __ LoadSImmediate(S0, 1.0);
2894 __ LoadSImmediate(S1, 2.0);
2895 __ LoadSImmediate(S2, 3.0);
2896 __ LoadSImmediate(S3, 4.0);
2897 __ LoadSImmediate(S4, 2.0);
2898 __ LoadSImmediate(S5, 1.0);
2899 __ LoadSImmediate(S6, 4.0);
2900 __ LoadSImmediate(S7, 1.0);
2901
2902 __ vcgtqs(Q2, Q1, Q0);
2903
2904 __ vmovrs(R0, S8);
2905 __ vmovrs(R1, S9);
2906 __ vmovrs(R2, S10);
2907 __ vmovrs(R3, S11);
2908
2909 __ add(R0, R0, ShifterOperand(R1));
2910 __ add(R0, R0, ShifterOperand(R2));
2911 __ add(R0, R0, ShifterOperand(R3));
2912 __ bx(LR);
2913 } else {
2914 __ LoadImmediate(R0, -2);
2915 __ bx(LR);
2916 }
2917 }
2918
2919
2920 ASSEMBLER_TEST_RUN(Vcgtqs, test) {
2921 EXPECT(test != NULL);
2922 typedef int (*Tst)();
2923 EXPECT_EQ(-2, EXECUTE_TEST_CODE_INT32(Tst, test->entry()));
2924 }
2925
2926
2557 // Called from assembler_test.cc. 2927 // Called from assembler_test.cc.
2558 // LR: return address. 2928 // LR: return address.
2559 // R0: context. 2929 // R0: context.
2560 // R1: value. 2930 // R1: value.
2561 // R2: growable array. 2931 // R2: growable array.
2562 ASSEMBLER_TEST_GENERATE(StoreIntoObject, assembler) { 2932 ASSEMBLER_TEST_GENERATE(StoreIntoObject, assembler) {
2563 __ PushList((1 << CTX) | (1 << LR)); 2933 __ PushList((1 << CTX) | (1 << LR));
2564 __ mov(CTX, ShifterOperand(R0)); 2934 __ mov(CTX, ShifterOperand(R0));
2565 __ StoreIntoObject(R2, 2935 __ StoreIntoObject(R2,
2566 FieldAddress(R2, GrowableObjectArray::data_offset()), 2936 FieldAddress(R2, GrowableObjectArray::data_offset()),
2567 R1); 2937 R1);
2568 __ PopList((1 << CTX) | (1 << LR)); 2938 __ PopList((1 << CTX) | (1 << LR));
2569 __ Ret(); 2939 __ Ret();
2570 } 2940 }
2571 2941
2572 } // namespace dart 2942 } // namespace dart
2573 2943
2574 #endif // defined TARGET_ARCH_ARM 2944 #endif // defined TARGET_ARCH_ARM
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