Subzero: Update for LLVM 3.9 (trunk).

src/IceTargetLoweringARM32.cpp

 //===- subzero/src/IceTargetLoweringARM32.cpp - ARM32 lowering ------------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 824 matching lines @@
 
 void TargetARM32::findMaxStackOutArgsSize() {
   // MinNeededOutArgsBytes should be updated if the Target ever creates a
   // high-level InstCall that requires more stack bytes.
   constexpr size_t MinNeededOutArgsBytes = 0;
   MaxOutArgsSizeBytes = MinNeededOutArgsBytes;
   for (CfgNode *Node : Func->getNodes()) {
     Context.init(Node);
     while (!Context.atEnd()) {
       PostIncrLoweringContext PostIncrement(Context);
-      Inst *CurInstr = Context.getCur();
+      Inst *CurInstr = iteratorToInst(Context.getCur());
       if (auto *Call = llvm::dyn_cast<InstCall>(CurInstr)) {
         SizeT OutArgsSizeBytes = getCallStackArgumentsSizeBytes(Call);
         MaxOutArgsSizeBytes = std::max(MaxOutArgsSizeBytes, OutArgsSizeBytes);
       }
     }
   }
 }
 
 void TargetARM32::createGotPtr() {
   if (SandboxingType != ST_Nonsfi) {
@@ skipping 70 matching lines @@
       break;
     }
   }
 
   if (DefGotPtr == nullptr || DefGotPtr->isDeleted()) {
     return;
   }
 
   // The got addr needs to be materialized at the same point where DefGotPtr
   // lives.
-  Context.setInsertPoint(DefGotPtr);
+  Context.setInsertPoint(instToIterator(DefGotPtr));
   assert(DefGotPtr->getSrcSize() == 1);
   auto *T = llvm::cast<Variable>(DefGotPtr->getSrc(0));
   loadNamedConstantRelocatablePIC(Ctx->getGlobalString(GlobalOffsetTable), T,
                                   [this, T](Variable *PC) { _add(T, PC, T); });
   _mov(GotPtr, T);
   DefGotPtr->setDeleted();
 }
 
 void TargetARM32::loadNamedConstantRelocatablePIC(
     GlobalString Name, Variable *Register,
@@ skipping 1085 matching lines @@
   // It may help to be more coordinated about assign stack slot numbers and may
   // help to assign smaller offsets to higher-weight variables so that they
   // don't depend on this legalization.
   for (CfgNode *Node : Func->getNodes()) {
     Context.init(Node);
     // One legalizer per basic block, otherwise we would share the Temporary
     // Base Register between basic blocks.
     PostLoweringLegalizer Legalizer(this);
     while (!Context.atEnd()) {
       PostIncrLoweringContext PostIncrement(Context);
-      Inst *CurInstr = Context.getCur();
+      Inst *CurInstr = iteratorToInst(Context.getCur());
 
       // Check if the previous TempBaseReg is clobbered, and reset if needed.
       Legalizer.resetTempBaseIfClobberedBy(CurInstr);
 
       if (auto *MovInstr = llvm::dyn_cast<InstARM32Mov>(CurInstr)) {
         Legalizer.legalizeMov(MovInstr);
       } else if (auto *LdrInstr = llvm::dyn_cast<InstARM32Ldr>(CurInstr)) {
         if (OperandARM32Mem *LegalMem = Legalizer.legalizeMemOperand(
                 llvm::cast<OperandARM32Mem>(LdrInstr->getSrc(0)))) {
           Sandboxer(this)
@@ skipping 3690 matching lines @@
     return OperandARM32Mem::create(Func, Ty, BaseVar, OffsetR, ShiftKind,
                                    OffsetRegShamt);
   }
 
   return OperandARM32Mem::create(
       Func, Ty, BaseVar,
       llvm::cast<ConstantInteger32>(Ctx->getConstantInt32(OffsetImm)));
 }
 
 void TargetARM32::doAddressOptLoad() {
-  Inst *Instr = Context.getCur();
+  Inst *Instr = iteratorToInst(Context.getCur());
   assert(llvm::isa<InstLoad>(Instr));
   Variable *Dest = Instr->getDest();
   Operand *Addr = Instr->getSrc(0);
   if (OperandARM32Mem *Mem =
           formAddressingMode(Dest->getType(), Func, Instr, Addr)) {
     Instr->setDeleted();
     Context.insert<InstLoad>(Dest, Mem);
   }
 }
 
@@ skipping 141 matching lines @@
     Variable *ValueLo = legalizeToReg(loOperand(Value));
     _str(ValueHi, llvm::cast<OperandARM32Mem>(hiOperand(NewAddr)));
     _str(ValueLo, llvm::cast<OperandARM32Mem>(loOperand(NewAddr)));
   } else {
     Variable *ValueR = legalizeToReg(Value);
     _str(ValueR, NewAddr);
   }
 }
 
 void TargetARM32::doAddressOptStore() {
-  Inst *Instr = Context.getCur();
+  Inst *Instr = iteratorToInst(Context.getCur());
   assert(llvm::isa<InstStore>(Instr));
   Operand *Src = Instr->getSrc(0);
   Operand *Addr = Instr->getSrc(1);
   if (OperandARM32Mem *Mem =
           formAddressingMode(Src->getType(), Func, Instr, Addr)) {
     Instr->setDeleted();
     Context.insert<InstStore>(Src, Mem);
   }
 }
 
@@ skipping 1220 matching lines @@
   // However, for compatibility with current NaCl LLVM, don't claim that.
   Str << ".eabi_attribute 14, 3   @ Tag_ABI_PCS_R9_use: Not used\n";
 }
 
 SmallBitVector TargetARM32::TypeToRegisterSet[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::TypeToRegisterSetUnfiltered[RegARM32::RCARM32_NUM];
 SmallBitVector TargetARM32::RegisterAliases[RegARM32::Reg_NUM];
 
 } // end of namespace ARM32
 } // end of namespace Ice