Experimental parser: merge r19949

src/a64/simulator-a64.h

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 168 matching lines @@
     ASSERT(size <= kSizeInBytes);
     T result;
     memset(&result, 0, sizeof(result));
     memcpy(&result, value_, size);
     return result;
   }
 
  protected:
   uint8_t value_[kSizeInBytes];
 };
-typedef SimRegisterBase<kXRegSizeInBytes> SimRegister;      // r0-r31
-typedef SimRegisterBase<kDRegSizeInBytes> SimFPRegister;    // v0-v31
+typedef SimRegisterBase<kXRegSize> SimRegister;      // r0-r31
+typedef SimRegisterBase<kDRegSize> SimFPRegister;    // v0-v31
 
 
 class Simulator : public DecoderVisitor {
  public:
   explicit Simulator(Decoder<DispatchingDecoderVisitor>* decoder,
                      Isolate* isolate = NULL,
                      FILE* stream = stderr);
   Simulator();
   ~Simulator();
 
@@ skipping 150 matching lines @@
   // Declare all Visitor functions.
   #define DECLARE(A)  void Visit##A(Instruction* instr);
   VISITOR_LIST(DECLARE)
   #undef DECLARE
 
   // Register accessors.
 
   // Return 'size' bits of the value of an integer register, as the specified
   // type. The value is zero-extended to fill the result.
   //
-  // The only supported values of 'size' are kXRegSize and kWRegSize.
+  // The only supported values of 'size' are kXRegSizeInBits and
+  // kWRegSizeInBits.
   template<typename T>
   T reg(unsigned size, unsigned code,
         Reg31Mode r31mode = Reg31IsZeroRegister) const {
     unsigned size_in_bytes = size / 8;
     ASSERT(size_in_bytes <= sizeof(T));
-    ASSERT((size == kXRegSize) || (size == kWRegSize));
+    ASSERT((size == kXRegSizeInBits) || (size == kWRegSizeInBits));
     ASSERT(code < kNumberOfRegisters);
 
     if ((code == 31) && (r31mode == Reg31IsZeroRegister)) {
       T result;
       memset(&result, 0, sizeof(result));
       return result;
     }
     return registers_[code].Get<T>(size_in_bytes);
   }
 
@@ skipping 15 matching lines @@
   }
 
   int64_t reg(unsigned size, unsigned code,
               Reg31Mode r31mode = Reg31IsZeroRegister) const {
     return reg<int64_t>(size, code, r31mode);
   }
 
   // Write 'size' bits of 'value' into an integer register. The value is
   // zero-extended. This behaviour matches AArch64 register writes.
   //
-  // The only supported values of 'size' are kXRegSize and kWRegSize.
+  // The only supported values of 'size' are kXRegSizeInBits and
+  // kWRegSizeInBits.
   template<typename T>
   void set_reg(unsigned size, unsigned code, T value,
                Reg31Mode r31mode = Reg31IsZeroRegister) {
     unsigned size_in_bytes = size / 8;
     ASSERT(size_in_bytes <= sizeof(T));
-    ASSERT((size == kXRegSize) || (size == kWRegSize));
+    ASSERT((size == kXRegSizeInBits) || (size == kWRegSizeInBits));
     ASSERT(code < kNumberOfRegisters);
 
     if ((code == 31) && (r31mode == Reg31IsZeroRegister)) {
       return;
     }
     return registers_[code].Set(value, size_in_bytes);
   }
 
   // Like set_reg(), but infer the access size from the template type.
   template<typename T>
   void set_reg(unsigned code, T value,
                Reg31Mode r31mode = Reg31IsZeroRegister) {
     set_reg(sizeof(value) * 8, code, value, r31mode);
   }
 
   // Common specialized accessors for the set_reg() template.
   void set_wreg(unsigned code, int32_t value,
                 Reg31Mode r31mode = Reg31IsZeroRegister) {
-    set_reg(kWRegSize, code, value, r31mode);
+    set_reg(kWRegSizeInBits, code, value, r31mode);
   }
 
   void set_xreg(unsigned code, int64_t value,
                 Reg31Mode r31mode = Reg31IsZeroRegister) {
-    set_reg(kXRegSize, code, value, r31mode);
+    set_reg(kXRegSizeInBits, code, value, r31mode);
   }
 
   // Commonly-used special cases.
   template<typename T>
   void set_lr(T value) {
     ASSERT(sizeof(T) == kPointerSize);
     set_reg(kLinkRegCode, value);
   }
 
   template<typename T>
   void set_sp(T value) {
     ASSERT(sizeof(T) == kPointerSize);
     set_reg(31, value, Reg31IsStackPointer);
   }
 
   int64_t sp() { return xreg(31, Reg31IsStackPointer); }
   int64_t jssp() { return xreg(kJSSPCode, Reg31IsStackPointer); }
   int64_t fp() {
       return xreg(kFramePointerRegCode, Reg31IsStackPointer);
   }
   Instruction* lr() { return reg<Instruction*>(kLinkRegCode); }
 
   Address get_sp() { return reg<Address>(31, Reg31IsStackPointer); }
 
   // Return 'size' bits of the value of a floating-point register, as the
   // specified type. The value is zero-extended to fill the result.
   //
-  // The only supported values of 'size' are kDRegSize and kSRegSize.
+  // The only supported values of 'size' are kDRegSizeInBits and
+  // kSRegSizeInBits.
   template<typename T>
   T fpreg(unsigned size, unsigned code) const {
     unsigned size_in_bytes = size / 8;
     ASSERT(size_in_bytes <= sizeof(T));
-    ASSERT((size == kDRegSize) || (size == kSRegSize));
+    ASSERT((size == kDRegSizeInBits) || (size == kSRegSizeInBits));
     ASSERT(code < kNumberOfFPRegisters);
     return fpregisters_[code].Get<T>(size_in_bytes);
   }
 
   // Like fpreg(), but infer the access size from the template type.
   template<typename T>
   T fpreg(unsigned code) const {
     return fpreg<T>(sizeof(T) * 8, code);
   }
 
   // Common specialized accessors for the fpreg() template.
   float sreg(unsigned code) const {
     return fpreg<float>(code);
   }
 
   uint32_t sreg_bits(unsigned code) const {
     return fpreg<uint32_t>(code);
   }
 
   double dreg(unsigned code) const {
     return fpreg<double>(code);
   }
 
   uint64_t dreg_bits(unsigned code) const {
     return fpreg<uint64_t>(code);
   }
 
   double fpreg(unsigned size, unsigned code) const {
     switch (size) {
-      case kSRegSize: return sreg(code);
-      case kDRegSize: return dreg(code);
+      case kSRegSizeInBits: return sreg(code);
+      case kDRegSizeInBits: return dreg(code);
       default:
         UNREACHABLE();
         return 0.0;
     }
   }
 
   // Write 'value' into a floating-point register. The value is zero-extended.
   // This behaviour matches AArch64 register writes.
   template<typename T>
   void set_fpreg(unsigned code, T value) {
-    ASSERT((sizeof(value) == kDRegSizeInBytes) ||
-           (sizeof(value) == kSRegSizeInBytes));
+    ASSERT((sizeof(value) == kDRegSize) || (sizeof(value) == kSRegSize));
     ASSERT(code < kNumberOfFPRegisters);
     fpregisters_[code].Set(value, sizeof(value));
   }
 
   // Common specialized accessors for the set_fpreg() template.
   void set_sreg(unsigned code, float value) {
     set_fpreg(code, value);
   }
 
   void set_sreg_bits(unsigned code, uint32_t value) {
     set_fpreg(code, value);
   }
 
   void set_dreg(unsigned code, double value) {
     set_fpreg(code, value);
   }
 
   void set_dreg_bits(unsigned code, uint64_t value) {
     set_fpreg(code, value);
   }
 
   bool N() { return nzcv_.N() != 0; }
   bool Z() { return nzcv_.Z() != 0; }
   bool C() { return nzcv_.C() != 0; }
   bool V() { return nzcv_.V() != 0; }
   SimSystemRegister& nzcv() { return nzcv_; }
 
   // TODO(jbramley): Find a way to make the fpcr_ members return the proper
-  // types, so this accessor is not necessary.
+  // types, so these accessors are not necessary.
   FPRounding RMode() { return static_cast<FPRounding>(fpcr_.RMode()); }
+  bool DN() { return fpcr_.DN() != 0; }
   SimSystemRegister& fpcr() { return fpcr_; }
 
   // Debug helpers
 
   // Simulator breakpoints.
   struct Breakpoint {
     Instruction* location;
     bool enabled;
   };
   std::vector<Breakpoint> breakpoints_;
@@ skipping 148 matching lines @@
                  Shift shift_type,
                  unsigned amount);
   int64_t ExtendValue(unsigned reg_width,
                       int64_t value,
                       Extend extend_type,
                       unsigned left_shift = 0);
 
   uint64_t ReverseBits(uint64_t value, unsigned num_bits);
   uint64_t ReverseBytes(uint64_t value, ReverseByteMode mode);
 
+  template <typename T>
+  T FPDefaultNaN() const;
+
   void FPCompare(double val0, double val1);
   double FPRoundInt(double value, FPRounding round_mode);
   double FPToDouble(float value);
   float FPToFloat(double value, FPRounding round_mode);
   double FixedToDouble(int64_t src, int fbits, FPRounding round_mode);
   double UFixedToDouble(uint64_t src, int fbits, FPRounding round_mode);
   float FixedToFloat(int64_t src, int fbits, FPRounding round_mode);
   float UFixedToFloat(uint64_t src, int fbits, FPRounding round_mode);
   int32_t FPToInt32(double value, FPRounding rmode);
   int64_t FPToInt64(double value, FPRounding rmode);
   uint32_t FPToUInt32(double value, FPRounding rmode);
   uint64_t FPToUInt64(double value, FPRounding rmode);
 
   template <typename T>
+  T FPAdd(T op1, T op2);
+
+  template <typename T>
+  T FPDiv(T op1, T op2);
+
+  template <typename T>
   T FPMax(T a, T b);
 
   template <typename T>
-  T FPMin(T a, T b);
+  T FPMaxNM(T a, T b);
 
   template <typename T>
-  T FPMaxNM(T a, T b);
+  T FPMin(T a, T b);
 
   template <typename T>
   T FPMinNM(T a, T b);
 
+  template <typename T>
+  T FPMul(T op1, T op2);
+
+  template <typename T>
+  T FPMulAdd(T a, T op1, T op2);
+
+  template <typename T>
+  T FPSqrt(T op);
+
+  template <typename T>
+  T FPSub(T op1, T op2);
+
+  // Standard NaN processing.
+  template <typename T>
+  T FPProcessNaN(T op);
+
+  bool FPProcessNaNs(Instruction* instr);
+
+  template <typename T>
+  T FPProcessNaNs(T op1, T op2);
+
+  template <typename T>
+  T FPProcessNaNs3(T op1, T op2, T op3);
+
   void CheckStackAlignment();
 
   inline void CheckPCSComplianceAndRun();
 
 #ifdef DEBUG
   // Corruption values should have their least significant byte cleared to
   // allow the code of the register being corrupted to be inserted.
   static const uint64_t kCallerSavedRegisterCorruptionValue =
       0xca11edc0de000000UL;
   // This value is a NaN in both 32-bit and 64-bit FP.
@@ skipping 32 matching lines @@
   SimSystemRegister fpcr_;
 
   // Only a subset of FPCR features are supported by the simulator. This helper
   // checks that the FPCR settings are supported.
   //
   // This is checked when floating-point instructions are executed, not when
   // FPCR is set. This allows generated code to modify FPCR for external
   // functions, or to save and restore it when entering and leaving generated
   // code.
   void AssertSupportedFPCR() {
-    ASSERT(fpcr().DN() == 0);             // No default-NaN support.
     ASSERT(fpcr().FZ() == 0);             // No flush-to-zero support.
     ASSERT(fpcr().RMode() == FPTieEven);  // Ties-to-even rounding only.
 
     // The simulator does not support half-precision operations so fpcr().AHP()
     // is irrelevant, and is not checked here.
   }
 
   static int CalcNFlag(uint64_t result, unsigned reg_size) {
     return (result >> (reg_size - 1)) & 1;
   }
@@ skipping 76 matching lines @@
   static void UnregisterCTryCatch() {
     Simulator::current(Isolate::Current())->PopAddress();
   }
 };
 
 #endif  // !defined(USE_SIMULATOR)
 
 } }  // namespace v8::internal
 
 #endif  // V8_A64_SIMULATOR_A64_H_