Experimental parser: merge r19949

src/a64/simulator-a64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 288 matching lines @@
 
   CorruptRegisters(&register_list, kCallerSavedRegisterCorruptionValue);
   CorruptRegisters(&fpregister_list, kCallerSavedFPRegisterCorruptionValue);
 }
 #endif
 
 
 // Extending the stack by 2 * 64 bits is required for stack alignment purposes.
 // TODO(all): Insert a marker in the extra space allocated on the stack.
 uintptr_t Simulator::PushAddress(uintptr_t address) {
-  ASSERT(sizeof(uintptr_t) < 2 * kXRegSizeInBytes);
-  intptr_t new_sp = sp() - 2 * kXRegSizeInBytes;
+  ASSERT(sizeof(uintptr_t) < 2 * kXRegSize);
+  intptr_t new_sp = sp() - 2 * kXRegSize;
   uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(new_sp);
   *stack_slot = address;
   set_sp(new_sp);
   return new_sp;
 }
 
 
 uintptr_t Simulator::PopAddress() {
   intptr_t current_sp = sp();
   uintptr_t* stack_slot = reinterpret_cast<uintptr_t*>(current_sp);
   uintptr_t address = *stack_slot;
-  ASSERT(sizeof(uintptr_t) < 2 * kXRegSizeInBytes);
-  set_sp(current_sp + 2 * kXRegSizeInBytes);
+  ASSERT(sizeof(uintptr_t) < 2 * kXRegSize);
+  set_sp(current_sp + 2 * kXRegSize);
   return address;
 }
 
 
 // Returns the limit of the stack area to enable checking for stack overflows.
 uintptr_t Simulator::StackLimit() const {
   // Leave a safety margin of 1024 bytes to prevent overrunning the stack when
   // pushing values.
   // TODO(all): Increase the stack limit protection.
 
@@ skipping 273 matching lines @@
 }
 
 
 // Helpers ---------------------------------------------------------------------
 int64_t Simulator::AddWithCarry(unsigned reg_size,
                                 bool set_flags,
                                 int64_t src1,
                                 int64_t src2,
                                 int64_t carry_in) {
   ASSERT((carry_in == 0) || (carry_in == 1));
-  ASSERT((reg_size == kXRegSize) || (reg_size == kWRegSize));
+  ASSERT((reg_size == kXRegSizeInBits) || (reg_size == kWRegSizeInBits));
 
   uint64_t u1, u2;
   int64_t result;
   int64_t signed_sum = src1 + src2 + carry_in;
 
   uint32_t N, Z, C, V;
 
-  if (reg_size == kWRegSize) {
+  if (reg_size == kWRegSizeInBits) {
     u1 = static_cast<uint64_t>(src1) & kWRegMask;
     u2 = static_cast<uint64_t>(src2) & kWRegMask;
 
     result = signed_sum & kWRegMask;
     // Compute the C flag by comparing the sum to the max unsigned integer.
     C = ((kWMaxUInt - u1) < (u2 + carry_in)) ||
         ((kWMaxUInt - u1 - carry_in) < u2);
     // Overflow iff the sign bit is the same for the two inputs and different
     // for the result.
-    int64_t s_src1 = src1 << (kXRegSize - kWRegSize);
-    int64_t s_src2 = src2 << (kXRegSize - kWRegSize);
-    int64_t s_result = result << (kXRegSize - kWRegSize);
+    int64_t s_src1 = src1 << (kXRegSizeInBits - kWRegSizeInBits);
+    int64_t s_src2 = src2 << (kXRegSizeInBits - kWRegSizeInBits);
+    int64_t s_result = result << (kXRegSizeInBits - kWRegSizeInBits);
     V = ((s_src1 ^ s_src2) >= 0) && ((s_src1 ^ s_result) < 0);
 
   } else {
     u1 = static_cast<uint64_t>(src1);
     u2 = static_cast<uint64_t>(src2);
 
     result = signed_sum;
     // Compute the C flag by comparing the sum to the max unsigned integer.
     C = ((kXMaxUInt - u1) < (u2 + carry_in)) ||
         ((kXMaxUInt - u1 - carry_in) < u2);
@@ skipping 15 matching lines @@
 }
 
 
 int64_t Simulator::ShiftOperand(unsigned reg_size,
                                 int64_t value,
                                 Shift shift_type,
                                 unsigned amount) {
   if (amount == 0) {
     return value;
   }
-  int64_t mask = reg_size == kXRegSize ? kXRegMask : kWRegMask;
+  int64_t mask = reg_size == kXRegSizeInBits ? kXRegMask : kWRegMask;
   switch (shift_type) {
     case LSL:
       return (value << amount) & mask;
     case LSR:
       return static_cast<uint64_t>(value) >> amount;
     case ASR: {
       // Shift used to restore the sign.
-      unsigned s_shift = kXRegSize - reg_size;
+      unsigned s_shift = kXRegSizeInBits - reg_size;
       // Value with its sign restored.
       int64_t s_value = (value << s_shift) >> s_shift;
       return (s_value >> amount) & mask;
     }
     case ROR: {
-      if (reg_size == kWRegSize) {
+      if (reg_size == kWRegSizeInBits) {
         value &= kWRegMask;
       }
       return (static_cast<uint64_t>(value) >> amount) |
              ((value & ((1L << amount) - 1L)) << (reg_size - amount));
     }
     default:
       UNIMPLEMENTED();
       return 0;
   }
 }
@@ skipping 21 matching lines @@
       break;
     case SXTW:
       value = (value << 32) >> 32;
       break;
     case UXTX:
     case SXTX:
       break;
     default:
       UNREACHABLE();
   }
-  int64_t mask = (reg_size == kXRegSize) ? kXRegMask : kWRegMask;
+  int64_t mask = (reg_size == kXRegSizeInBits) ? kXRegMask : kWRegMask;
   return (value << left_shift) & mask;
 }
 
 
+template<> double Simulator::FPDefaultNaN<double>() const {
+  return kFP64DefaultNaN;
+}
+
+
+template<> float Simulator::FPDefaultNaN<float>() const {
+  return kFP32DefaultNaN;
+}
+
+
 void Simulator::FPCompare(double val0, double val1) {
   AssertSupportedFPCR();
 
   // TODO(jbramley): This assumes that the C++ implementation handles
   // comparisons in the way that we expect (as per AssertSupportedFPCR()).
   if ((std::isnan(val0) != 0) || (std::isnan(val1) != 0)) {
     nzcv().SetRawValue(FPUnorderedFlag);
   } else if (val0 < val1) {
     nzcv().SetRawValue(FPLessThanFlag);
   } else if (val0 > val1) {
@@ skipping 305 matching lines @@
     case CBNZ_x: take_branch = (xreg(rt) != 0); break;
     default: UNIMPLEMENTED();
   }
   if (take_branch) {
     set_pc(instr->ImmPCOffsetTarget());
   }
 }
 
 
 void Simulator::AddSubHelper(Instruction* instr, int64_t op2) {
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSize : kWRegSize;
+  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
+                                             : kWRegSizeInBits;
   bool set_flags = instr->FlagsUpdate();
   int64_t new_val = 0;
   Instr operation = instr->Mask(AddSubOpMask);
 
   switch (operation) {
     case ADD:
     case ADDS: {
       new_val = AddWithCarry(reg_size,
                              set_flags,
                              reg(reg_size, instr->Rn(), instr->RnMode()),
@@ skipping 10 matching lines @@
       break;
     }
     default: UNREACHABLE();
   }
 
   set_reg(reg_size, instr->Rd(), new_val, instr->RdMode());
 }
 
 
 void Simulator::VisitAddSubShifted(Instruction* instr) {
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSize : kWRegSize;
+  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
+                                             : kWRegSizeInBits;
   int64_t op2 = ShiftOperand(reg_size,
                              reg(reg_size, instr->Rm()),
                              static_cast<Shift>(instr->ShiftDP()),
                              instr->ImmDPShift());
   AddSubHelper(instr, op2);
 }
 
 
 void Simulator::VisitAddSubImmediate(Instruction* instr) {
   int64_t op2 = instr->ImmAddSub() << ((instr->ShiftAddSub() == 1) ? 12 : 0);
   AddSubHelper(instr, op2);
 }
 
 
 void Simulator::VisitAddSubExtended(Instruction* instr) {
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSize : kWRegSize;
+  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
+                                             : kWRegSizeInBits;
   int64_t op2 = ExtendValue(reg_size,
                             reg(reg_size, instr->Rm()),
                             static_cast<Extend>(instr->ExtendMode()),
                             instr->ImmExtendShift());
   AddSubHelper(instr, op2);
 }
 
 
 void Simulator::VisitAddSubWithCarry(Instruction* instr) {
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSize : kWRegSize;
+  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
+                                             : kWRegSizeInBits;
   int64_t op2 = reg(reg_size, instr->Rm());
   int64_t new_val;
 
   if ((instr->Mask(AddSubOpMask) == SUB) || instr->Mask(AddSubOpMask) == SUBS) {
     op2 = ~op2;
   }
 
   new_val = AddWithCarry(reg_size,
                          instr->FlagsUpdate(),
                          reg(reg_size, instr->Rn()),
                          op2,
                          C());
 
   set_reg(reg_size, instr->Rd(), new_val);
 }
 
 
 void Simulator::VisitLogicalShifted(Instruction* instr) {
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSize : kWRegSize;
+  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
+                                             : kWRegSizeInBits;
   Shift shift_type = static_cast<Shift>(instr->ShiftDP());
   unsigned shift_amount = instr->ImmDPShift();
   int64_t op2 = ShiftOperand(reg_size, reg(reg_size, instr->Rm()), shift_type,
                              shift_amount);
   if (instr->Mask(NOT) == NOT) {
     op2 = ~op2;
   }
   LogicalHelper(instr, op2);
 }
 
 
 void Simulator::VisitLogicalImmediate(Instruction* instr) {
   LogicalHelper(instr, instr->ImmLogical());
 }
 
 
 void Simulator::LogicalHelper(Instruction* instr, int64_t op2) {
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSize : kWRegSize;
+  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
+                                             : kWRegSizeInBits;
   int64_t op1 = reg(reg_size, instr->Rn());
   int64_t result = 0;
   bool update_flags = false;
 
   // Switch on the logical operation, stripping out the NOT bit, as it has a
   // different meaning for logical immediate instructions.
   switch (instr->Mask(LogicalOpMask & ~NOT)) {
     case ANDS: update_flags = true;  // Fall through.
     case AND: result = op1 & op2; break;
     case ORR: result = op1 | op2; break;
     case EOR: result = op1 ^ op2; break;
     default:
       UNIMPLEMENTED();
   }
 
   if (update_flags) {
     nzcv().SetN(CalcNFlag(result, reg_size));
     nzcv().SetZ(CalcZFlag(result));
     nzcv().SetC(0);
     nzcv().SetV(0);
   }
 
   set_reg(reg_size, instr->Rd(), result, instr->RdMode());
 }
 
 
 void Simulator::VisitConditionalCompareRegister(Instruction* instr) {
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSize : kWRegSize;
+  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
+                                             : kWRegSizeInBits;
   ConditionalCompareHelper(instr, reg(reg_size, instr->Rm()));
 }
 
 
 void Simulator::VisitConditionalCompareImmediate(Instruction* instr) {
   ConditionalCompareHelper(instr, instr->ImmCondCmp());
 }
 
 
 void Simulator::ConditionalCompareHelper(Instruction* instr, int64_t op2) {
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSize : kWRegSize;
+  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
+                                             : kWRegSizeInBits;
   int64_t op1 = reg(reg_size, instr->Rn());
 
   if (ConditionPassed(static_cast<Condition>(instr->Condition()))) {
     // If the condition passes, set the status flags to the result of comparing
     // the operands.
     if (instr->Mask(ConditionalCompareMask) == CCMP) {
       AddWithCarry(reg_size, true, op1, ~op2, 1);
     } else {
       ASSERT(instr->Mask(ConditionalCompareMask) == CCMN);
       AddWithCarry(reg_size, true, op1, op2, 0);
@@ skipping 24 matching lines @@
 void Simulator::VisitLoadStorePostIndex(Instruction* instr) {
   LoadStoreHelper(instr, instr->ImmLS(), PostIndex);
 }
 
 
 void Simulator::VisitLoadStoreRegisterOffset(Instruction* instr) {
   Extend ext = static_cast<Extend>(instr->ExtendMode());
   ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX));
   unsigned shift_amount = instr->ImmShiftLS() * instr->SizeLS();
 
-  int64_t offset = ExtendValue(kXRegSize, xreg(instr->Rm()), ext,
+  int64_t offset = ExtendValue(kXRegSizeInBits, xreg(instr->Rm()), ext,
                                shift_amount);
   LoadStoreHelper(instr, offset, Offset);
 }
 
 
 void Simulator::LoadStoreHelper(Instruction* instr,
                                 int64_t offset,
                                 AddrMode addrmode) {
   unsigned srcdst = instr->Rt();
   unsigned addr_reg = instr->Rn();
@@ skipping 20 matching lines @@
   switch (op) {
     case LDRB_w:
     case LDRH_w:
     case LDR_w:
     case LDR_x: set_xreg(srcdst, MemoryRead(address, num_bytes)); break;
     case STRB_w:
     case STRH_w:
     case STR_w:
     case STR_x: MemoryWrite(address, xreg(srcdst), num_bytes); break;
     case LDRSB_w: {
-      set_wreg(srcdst, ExtendValue(kWRegSize, MemoryRead8(address), SXTB));
+      set_wreg(srcdst,
+               ExtendValue(kWRegSizeInBits, MemoryRead8(address), SXTB));
       break;
     }
     case LDRSB_x: {
-      set_xreg(srcdst, ExtendValue(kXRegSize, MemoryRead8(address), SXTB));
+      set_xreg(srcdst,
+               ExtendValue(kXRegSizeInBits, MemoryRead8(address), SXTB));
       break;
     }
     case LDRSH_w: {
-      set_wreg(srcdst, ExtendValue(kWRegSize, MemoryRead16(address), SXTH));
+      set_wreg(srcdst,
+               ExtendValue(kWRegSizeInBits, MemoryRead16(address), SXTH));
       break;
     }
     case LDRSH_x: {
-      set_xreg(srcdst, ExtendValue(kXRegSize, MemoryRead16(address), SXTH));
+      set_xreg(srcdst,
+               ExtendValue(kXRegSizeInBits, MemoryRead16(address), SXTH));
       break;
     }
     case LDRSW_x: {
-      set_xreg(srcdst, ExtendValue(kXRegSize, MemoryRead32(address), SXTW));
+      set_xreg(srcdst,
+               ExtendValue(kXRegSizeInBits, MemoryRead32(address), SXTW));
       break;
     }
     case LDR_s: set_sreg(srcdst, MemoryReadFP32(address)); break;
     case LDR_d: set_dreg(srcdst, MemoryReadFP64(address)); break;
     case STR_s: MemoryWriteFP32(address, sreg(srcdst)); break;
     case STR_d: MemoryWriteFP64(address, dreg(srcdst)); break;
     default: UNIMPLEMENTED();
   }
 
   // Handle the writeback for loads after the load to ensure safe pop
@@ skipping 60 matching lines @@
 
   LoadStorePairOp op =
     static_cast<LoadStorePairOp>(instr->Mask(LoadStorePairMask));
 
   // 'rt' and 'rt2' can only be aliased for stores.
   ASSERT(((op & LoadStorePairLBit) == 0) || (rt != rt2));
 
   switch (op) {
     case LDP_w: {
       set_wreg(rt, MemoryRead32(address));
-      set_wreg(rt2, MemoryRead32(address + kWRegSizeInBytes));
+      set_wreg(rt2, MemoryRead32(address + kWRegSize));
       break;
     }
     case LDP_s: {
       set_sreg(rt, MemoryReadFP32(address));
-      set_sreg(rt2, MemoryReadFP32(address + kSRegSizeInBytes));
+      set_sreg(rt2, MemoryReadFP32(address + kSRegSize));
       break;
     }
     case LDP_x: {
       set_xreg(rt, MemoryRead64(address));
-      set_xreg(rt2, MemoryRead64(address + kXRegSizeInBytes));
+      set_xreg(rt2, MemoryRead64(address + kXRegSize));
       break;
     }
     case LDP_d: {
       set_dreg(rt, MemoryReadFP64(address));
-      set_dreg(rt2, MemoryReadFP64(address + kDRegSizeInBytes));
+      set_dreg(rt2, MemoryReadFP64(address + kDRegSize));
       break;
     }
     case LDPSW_x: {
-      set_xreg(rt, ExtendValue(kXRegSize, MemoryRead32(address), SXTW));
-      set_xreg(rt2, ExtendValue(kXRegSize,
-               MemoryRead32(address + kWRegSizeInBytes), SXTW));
+      set_xreg(rt, ExtendValue(kXRegSizeInBits, MemoryRead32(address), SXTW));
+      set_xreg(rt2, ExtendValue(kXRegSizeInBits,
+               MemoryRead32(address + kWRegSize), SXTW));
       break;
     }
     case STP_w: {
       MemoryWrite32(address, wreg(rt));
-      MemoryWrite32(address + kWRegSizeInBytes, wreg(rt2));
+      MemoryWrite32(address + kWRegSize, wreg(rt2));
       break;
     }
     case STP_s: {
       MemoryWriteFP32(address, sreg(rt));
-      MemoryWriteFP32(address + kSRegSizeInBytes, sreg(rt2));
+      MemoryWriteFP32(address + kSRegSize, sreg(rt2));
       break;
     }
     case STP_x: {
       MemoryWrite64(address, xreg(rt));
-      MemoryWrite64(address + kXRegSizeInBytes, xreg(rt2));
+      MemoryWrite64(address + kXRegSize, xreg(rt2));
       break;
     }
     case STP_d: {
       MemoryWriteFP64(address, dreg(rt));
-      MemoryWriteFP64(address + kDRegSizeInBytes, dreg(rt2));
+      MemoryWriteFP64(address + kDRegSize, dreg(rt2));
       break;
     }
     default: UNREACHABLE();
   }
 
   // Handle the writeback for loads after the load to ensure safe pop
   // operation even when interrupted in the middle of it. The stack pointer
   // is only updated after the load so pop(fp) will never break the invariant
   // sp <= fp expected while walking the stack in the sampler.
   if (instr->IsLoad()) {
@@ skipping 190 matching lines @@
       case CSEL_x: break;
       case CSINC_w:
       case CSINC_x: new_val++; break;
       case CSINV_w:
       case CSINV_x: new_val = ~new_val; break;
       case CSNEG_w:
       case CSNEG_x: new_val = -new_val; break;
       default: UNIMPLEMENTED();
     }
   }
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSize : kWRegSize;
+  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
+                                             : kWRegSizeInBits;
   set_reg(reg_size, instr->Rd(), new_val);
 }
 
 
 void Simulator::VisitDataProcessing1Source(Instruction* instr) {
   unsigned dst = instr->Rd();
   unsigned src = instr->Rn();
 
   switch (instr->Mask(DataProcessing1SourceMask)) {
-    case RBIT_w: set_wreg(dst, ReverseBits(wreg(src), kWRegSize)); break;
-    case RBIT_x: set_xreg(dst, ReverseBits(xreg(src), kXRegSize)); break;
+    case RBIT_w: set_wreg(dst, ReverseBits(wreg(src), kWRegSizeInBits)); break;
+    case RBIT_x: set_xreg(dst, ReverseBits(xreg(src), kXRegSizeInBits)); break;
     case REV16_w: set_wreg(dst, ReverseBytes(wreg(src), Reverse16)); break;
     case REV16_x: set_xreg(dst, ReverseBytes(xreg(src), Reverse16)); break;
     case REV_w: set_wreg(dst, ReverseBytes(wreg(src), Reverse32)); break;
     case REV32_x: set_xreg(dst, ReverseBytes(xreg(src), Reverse32)); break;
     case REV_x: set_xreg(dst, ReverseBytes(xreg(src), Reverse64)); break;
-    case CLZ_w: set_wreg(dst, CountLeadingZeros(wreg(src), kWRegSize)); break;
-    case CLZ_x: set_xreg(dst, CountLeadingZeros(xreg(src), kXRegSize)); break;
+    case CLZ_w: set_wreg(dst, CountLeadingZeros(wreg(src), kWRegSizeInBits));
+                break;
+    case CLZ_x: set_xreg(dst, CountLeadingZeros(xreg(src), kXRegSizeInBits));
+                break;
     case CLS_w: {
-      set_wreg(dst, CountLeadingSignBits(wreg(src), kWRegSize));
+      set_wreg(dst, CountLeadingSignBits(wreg(src), kWRegSizeInBits));
       break;
     }
     case CLS_x: {
-      set_xreg(dst, CountLeadingSignBits(xreg(src), kXRegSize));
+      set_xreg(dst, CountLeadingSignBits(xreg(src), kXRegSizeInBits));
       break;
     }
     default: UNIMPLEMENTED();
   }
 }
 
 
 uint64_t Simulator::ReverseBits(uint64_t value, unsigned num_bits) {
-  ASSERT((num_bits == kWRegSize) || (num_bits == kXRegSize));
+  ASSERT((num_bits == kWRegSizeInBits) || (num_bits == kXRegSizeInBits));
   uint64_t result = 0;
   for (unsigned i = 0; i < num_bits; i++) {
     result = (result << 1) | (value & 1);
     value >>= 1;
   }
   return result;
 }
 
 
 uint64_t Simulator::ReverseBytes(uint64_t value, ReverseByteMode mode) {
@@ skipping 84 matching lines @@
     case LSLV_x: shift_op = LSL; break;
     case LSRV_w:
     case LSRV_x: shift_op = LSR; break;
     case ASRV_w:
     case ASRV_x: shift_op = ASR; break;
     case RORV_w:
     case RORV_x: shift_op = ROR; break;
     default: UNIMPLEMENTED();
   }
 
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSize : kWRegSize;
+  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
+                                             : kWRegSizeInBits;
   if (shift_op != NO_SHIFT) {
     // Shift distance encoded in the least-significant five/six bits of the
     // register.
     int mask = (instr->SixtyFourBits() == 1) ? 0x3f : 0x1f;
     unsigned shift = wreg(instr->Rm()) & mask;
     result = ShiftOperand(reg_size, reg(reg_size, instr->Rn()), shift_op,
                           shift);
   }
   set_reg(reg_size, instr->Rd(), result);
 }
@@ skipping 15 matching lines @@
   t = u1 * v0 + (w0 >> 32);
   w1 = t & 0xffffffffL;
   w2 = t >> 32;
   w1 = u0 * v1 + w1;
 
   return u1 * v1 + w2 + (w1 >> 32);
 }
 
 
 void Simulator::VisitDataProcessing3Source(Instruction* instr) {
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSize : kWRegSize;
+  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
+                                             : kWRegSizeInBits;
 
   int64_t result = 0;
   // Extract and sign- or zero-extend 32-bit arguments for widening operations.
   uint64_t rn_u32 = reg<uint32_t>(instr->Rn());
   uint64_t rm_u32 = reg<uint32_t>(instr->Rm());
   int64_t rn_s32 = reg<int32_t>(instr->Rn());
   int64_t rm_s32 = reg<int32_t>(instr->Rm());
   switch (instr->Mask(DataProcessing3SourceMask)) {
     case MADD_w:
     case MADD_x:
@@ skipping 11 matching lines @@
       ASSERT(instr->Ra() == kZeroRegCode);
       result = MultiplyHighSigned(xreg(instr->Rn()), xreg(instr->Rm()));
       break;
     default: UNIMPLEMENTED();
   }
   set_reg(reg_size, instr->Rd(), result);
 }
 
 
 void Simulator::VisitBitfield(Instruction* instr) {
-  unsigned reg_size = instr->SixtyFourBits() ? kXRegSize : kWRegSize;
+  unsigned reg_size = instr->SixtyFourBits() ? kXRegSizeInBits
+                                             : kWRegSizeInBits;
   int64_t reg_mask = instr->SixtyFourBits() ? kXRegMask : kWRegMask;
   int64_t R = instr->ImmR();
   int64_t S = instr->ImmS();
   int64_t diff = S - R;
   int64_t mask;
   if (diff >= 0) {
     mask = diff < reg_size - 1 ? (1L << (diff + 1)) - 1
                                : reg_mask;
   } else {
     mask = ((1L << (S + 1)) - 1);
@@ skipping 33 matching lines @@
 
   // Merge sign extension, dest/zero and bitfield.
   result = signbits | (result & mask) | (dst & ~mask);
 
   set_reg(reg_size, instr->Rd(), result);
 }
 
 
 void Simulator::VisitExtract(Instruction* instr) {
   unsigned lsb = instr->ImmS();
-  unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSize
-                                                    : kWRegSize;
+  unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSizeInBits
+                                                    : kWRegSizeInBits;
   set_reg(reg_size,
           instr->Rd(),
           (static_cast<uint64_t>(reg(reg_size, instr->Rm())) >> lsb) |
           (reg(reg_size, instr->Rn()) << (reg_size - lsb)));
 }
 
 
 void Simulator::VisitFPImmediate(Instruction* instr) {
   AssertSupportedFPCR();
 
@@ skipping 175 matching lines @@
   } else if (value < 0.0) {
     return 0;
   }
   return std::isnan(value) ? 0 : static_cast<uint64_t>(value);
 }
 
 
 void Simulator::VisitFPCompare(Instruction* instr) {
   AssertSupportedFPCR();
 
-  unsigned reg_size = instr->FPType() == FP32 ? kSRegSize : kDRegSize;
+  unsigned reg_size = (instr->Mask(FP64) == FP64) ? kDRegSizeInBits
+                                                  : kSRegSizeInBits;
   double fn_val = fpreg(reg_size, instr->Rn());
 
   switch (instr->Mask(FPCompareMask)) {
     case FCMP_s:
     case FCMP_d: FPCompare(fn_val, fpreg(reg_size, instr->Rm())); break;
     case FCMP_s_zero:
     case FCMP_d_zero: FPCompare(fn_val, 0.0); break;
     default: UNIMPLEMENTED();
   }
 }
 
 
 void Simulator::VisitFPConditionalCompare(Instruction* instr) {
   AssertSupportedFPCR();
 
   switch (instr->Mask(FPConditionalCompareMask)) {
     case FCCMP_s:
     case FCCMP_d: {
       if (ConditionPassed(static_cast<Condition>(instr->Condition()))) {
         // If the condition passes, set the status flags to the result of
         // comparing the operands.
-        unsigned reg_size = instr->FPType() == FP32 ? kSRegSize : kDRegSize;
+        unsigned reg_size = (instr->Mask(FP64) == FP64) ? kDRegSizeInBits
+                                                        : kSRegSizeInBits;
         FPCompare(fpreg(reg_size, instr->Rn()), fpreg(reg_size, instr->Rm()));
       } else {
         // If the condition fails, set the status flags to the nzcv immediate.
         nzcv().SetFlags(instr->Nzcv());
       }
       break;
     }
     default: UNIMPLEMENTED();
   }
 }
@@ skipping 23 matching lines @@
   unsigned fd = instr->Rd();
   unsigned fn = instr->Rn();
 
   switch (instr->Mask(FPDataProcessing1SourceMask)) {
     case FMOV_s: set_sreg(fd, sreg(fn)); break;
     case FMOV_d: set_dreg(fd, dreg(fn)); break;
     case FABS_s: set_sreg(fd, std::fabs(sreg(fn))); break;
     case FABS_d: set_dreg(fd, std::fabs(dreg(fn))); break;
     case FNEG_s: set_sreg(fd, -sreg(fn)); break;
     case FNEG_d: set_dreg(fd, -dreg(fn)); break;
-    case FSQRT_s: set_sreg(fd, std::sqrt(sreg(fn))); break;
-    case FSQRT_d: set_dreg(fd, std::sqrt(dreg(fn))); break;
+    case FSQRT_s: set_sreg(fd, FPSqrt(sreg(fn))); break;
+    case FSQRT_d: set_dreg(fd, FPSqrt(dreg(fn))); break;
     case FRINTA_s: set_sreg(fd, FPRoundInt(sreg(fn), FPTieAway)); break;
     case FRINTA_d: set_dreg(fd, FPRoundInt(dreg(fn), FPTieAway)); break;
     case FRINTN_s: set_sreg(fd, FPRoundInt(sreg(fn), FPTieEven)); break;
     case FRINTN_d: set_dreg(fd, FPRoundInt(dreg(fn), FPTieEven)); break;
     case FRINTZ_s: set_sreg(fd, FPRoundInt(sreg(fn), FPZero)); break;
     case FRINTZ_d: set_dreg(fd, FPRoundInt(dreg(fn), FPZero)); break;
     case FCVT_ds: set_dreg(fd, FPToDouble(sreg(fn))); break;
     case FCVT_sd: set_sreg(fd, FPToFloat(dreg(fn), FPTieEven)); break;
     default: UNIMPLEMENTED();
   }
@@ skipping 238 matching lines @@
   // 2^exponent.
   const int highest_significant_bit = 63 - CountLeadingZeros(src, 64);
   const int32_t exponent = highest_significant_bit - fbits;
 
   return FPRoundToFloat(0, exponent, src, round);
 }
 
 
 double Simulator::FPRoundInt(double value, FPRounding round_mode) {
   if ((value == 0.0) || (value == kFP64PositiveInfinity) ||
-      (value == kFP64NegativeInfinity) || std::isnan(value)) {
+      (value == kFP64NegativeInfinity)) {
     return value;
+  } else if (std::isnan(value)) {
+    return FPProcessNaN(value);
   }
 
   double int_result = floor(value);
   double error = value - int_result;
   switch (round_mode) {
     case FPTieAway: {
       // If the error is greater than 0.5, or is equal to 0.5 and the integer
       // result is positive, round up.
       if ((error > 0.5) || ((error == 0.5) && (int_result >= 0.0))) {
         int_result++;
@@ skipping 23 matching lines @@
     }
     default: UNIMPLEMENTED();
   }
   return int_result;
 }
 
 
 double Simulator::FPToDouble(float value) {
   switch (std::fpclassify(value)) {
     case FP_NAN: {
-      // Convert NaNs as the processor would, assuming that FPCR.DN (default
-      // NaN) is not set:
+      if (DN()) return kFP64DefaultNaN;
+
+      // Convert NaNs as the processor would:
       //  - The sign is propagated.
       //  - The payload (mantissa) is transferred entirely, except that the top
       //    bit is forced to '1', making the result a quiet NaN. The unused
       //    (low-order) payload bits are set to 0.
       uint32_t raw = float_to_rawbits(value);
 
       uint64_t sign = raw >> 31;
       uint64_t exponent = (1 << 11) - 1;
       uint64_t payload = unsigned_bitextract_64(21, 0, raw);
       payload <<= (52 - 23);  // The unused low-order bits should be 0.
@@ skipping 18 matching lines @@
 }
 
 
 float Simulator::FPToFloat(double value, FPRounding round_mode) {
   // Only the FPTieEven rounding mode is implemented.
   ASSERT(round_mode == FPTieEven);
   USE(round_mode);
 
   switch (std::fpclassify(value)) {
     case FP_NAN: {
-      // Convert NaNs as the processor would, assuming that FPCR.DN (default
-      // NaN) is not set:
+      if (DN()) return kFP32DefaultNaN;
+
+      // Convert NaNs as the processor would:
       //  - The sign is propagated.
       //  - The payload (mantissa) is transferred as much as possible, except
       //    that the top bit is forced to '1', making the result a quiet NaN.
       uint64_t raw = double_to_rawbits(value);
 
       uint32_t sign = raw >> 63;
       uint32_t exponent = (1 << 8) - 1;
       uint32_t payload = unsigned_bitextract_64(50, 52 - 23, raw);
       payload |= (1 << 22);   // Force a quiet NaN.
 
@@ skipping 30 matching lines @@
 }
 
 
 void Simulator::VisitFPDataProcessing2Source(Instruction* instr) {
   AssertSupportedFPCR();
 
   unsigned fd = instr->Rd();
   unsigned fn = instr->Rn();
   unsigned fm = instr->Rm();
 
+  // Fmaxnm and Fminnm have special NaN handling.
   switch (instr->Mask(FPDataProcessing2SourceMask)) {
-    case FADD_s: set_sreg(fd, sreg(fn) + sreg(fm)); break;
-    case FADD_d: set_dreg(fd, dreg(fn) + dreg(fm)); break;
-    case FSUB_s: set_sreg(fd, sreg(fn) - sreg(fm)); break;
-    case FSUB_d: set_dreg(fd, dreg(fn) - dreg(fm)); break;
-    case FMUL_s: set_sreg(fd, sreg(fn) * sreg(fm)); break;
-    case FMUL_d: set_dreg(fd, dreg(fn) * dreg(fm)); break;
-    case FDIV_s: set_sreg(fd, sreg(fn) / sreg(fm)); break;
-    case FDIV_d: set_dreg(fd, dreg(fn) / dreg(fm)); break;
+    case FMAXNM_s: set_sreg(fd, FPMaxNM(sreg(fn), sreg(fm))); return;
+    case FMAXNM_d: set_dreg(fd, FPMaxNM(dreg(fn), dreg(fm))); return;
+    case FMINNM_s: set_sreg(fd, FPMinNM(sreg(fn), sreg(fm))); return;
+    case FMINNM_d: set_dreg(fd, FPMinNM(dreg(fn), dreg(fm))); return;
+    default:
+      break;    // Fall through.
+  }
+
+  if (FPProcessNaNs(instr)) return;
+
+  switch (instr->Mask(FPDataProcessing2SourceMask)) {
+    case FADD_s: set_sreg(fd, FPAdd(sreg(fn), sreg(fm))); break;
+    case FADD_d: set_dreg(fd, FPAdd(dreg(fn), dreg(fm))); break;
+    case FSUB_s: set_sreg(fd, FPSub(sreg(fn), sreg(fm))); break;
+    case FSUB_d: set_dreg(fd, FPSub(dreg(fn), dreg(fm))); break;
+    case FMUL_s: set_sreg(fd, FPMul(sreg(fn), sreg(fm))); break;
+    case FMUL_d: set_dreg(fd, FPMul(dreg(fn), dreg(fm))); break;
+    case FDIV_s: set_sreg(fd, FPDiv(sreg(fn), sreg(fm))); break;
+    case FDIV_d: set_dreg(fd, FPDiv(dreg(fn), dreg(fm))); break;
     case FMAX_s: set_sreg(fd, FPMax(sreg(fn), sreg(fm))); break;
     case FMAX_d: set_dreg(fd, FPMax(dreg(fn), dreg(fm))); break;
     case FMIN_s: set_sreg(fd, FPMin(sreg(fn), sreg(fm))); break;
     case FMIN_d: set_dreg(fd, FPMin(dreg(fn), dreg(fm))); break;
-    case FMAXNM_s: set_sreg(fd, FPMaxNM(sreg(fn), sreg(fm))); break;
-    case FMAXNM_d: set_dreg(fd, FPMaxNM(dreg(fn), dreg(fm))); break;
-    case FMINNM_s: set_sreg(fd, FPMinNM(sreg(fn), sreg(fm))); break;
-    case FMINNM_d: set_dreg(fd, FPMinNM(dreg(fn), dreg(fm))); break;
+    case FMAXNM_s:
+    case FMAXNM_d:
+    case FMINNM_s:
+    case FMINNM_d:
+      // These were handled before the standard FPProcessNaNs() stage.
+      UNREACHABLE();
     default: UNIMPLEMENTED();
   }
 }
 
 
 void Simulator::VisitFPDataProcessing3Source(Instruction* instr) {
   AssertSupportedFPCR();
 
   unsigned fd = instr->Rd();
   unsigned fn = instr->Rn();
   unsigned fm = instr->Rm();
   unsigned fa = instr->Ra();
 
   // The C99 (and C++11) fma function performs a fused multiply-accumulate.
   switch (instr->Mask(FPDataProcessing3SourceMask)) {
     // fd = fa +/- (fn * fm)
-    case FMADD_s: set_sreg(fd, fmaf(sreg(fn), sreg(fm), sreg(fa))); break;
-    case FMSUB_s: set_sreg(fd, fmaf(-sreg(fn), sreg(fm), sreg(fa))); break;
-    case FMADD_d: set_dreg(fd, fma(dreg(fn), dreg(fm), dreg(fa))); break;
-    case FMSUB_d: set_dreg(fd, fma(-dreg(fn), dreg(fm), dreg(fa))); break;
-    // Variants of the above where the result is negated.
-    case FNMADD_s: set_sreg(fd, -fmaf(sreg(fn), sreg(fm), sreg(fa))); break;
-    case FNMSUB_s: set_sreg(fd, -fmaf(-sreg(fn), sreg(fm), sreg(fa))); break;
-    case FNMADD_d: set_dreg(fd, -fma(dreg(fn), dreg(fm), dreg(fa))); break;
-    case FNMSUB_d: set_dreg(fd, -fma(-dreg(fn), dreg(fm), dreg(fa))); break;
+    case FMADD_s: set_sreg(fd, FPMulAdd(sreg(fa), sreg(fn), sreg(fm))); break;
+    case FMSUB_s: set_sreg(fd, FPMulAdd(sreg(fa), -sreg(fn), sreg(fm))); break;
+    case FMADD_d: set_dreg(fd, FPMulAdd(dreg(fa), dreg(fn), dreg(fm))); break;
+    case FMSUB_d: set_dreg(fd, FPMulAdd(dreg(fa), -dreg(fn), dreg(fm))); break;
+    // Negated variants of the above.
+    case FNMADD_s:
+      set_sreg(fd, FPMulAdd(-sreg(fa), -sreg(fn), sreg(fm)));
+      break;
+    case FNMSUB_s:
+      set_sreg(fd, FPMulAdd(-sreg(fa), sreg(fn), sreg(fm)));
+      break;
+    case FNMADD_d:
+      set_dreg(fd, FPMulAdd(-dreg(fa), -dreg(fn), dreg(fm)));
+      break;
+    case FNMSUB_d:
+      set_dreg(fd, FPMulAdd(-dreg(fa), dreg(fn), dreg(fm)));
+      break;
     default: UNIMPLEMENTED();
   }
 }
 
 
 template <typename T>
+T Simulator::FPAdd(T op1, T op2) {
+  // NaNs should be handled elsewhere.
+  ASSERT(!std::isnan(op1) && !std::isnan(op2));
+
+  if (isinf(op1) && isinf(op2) && (op1 != op2)) {
+    // inf + -inf returns the default NaN.
+    return FPDefaultNaN<T>();
+  } else {
+    // Other cases should be handled by standard arithmetic.
+    return op1 + op2;
+  }
+}
+
+
+template <typename T>
+T Simulator::FPDiv(T op1, T op2) {
+  // NaNs should be handled elsewhere.
+  ASSERT(!std::isnan(op1) && !std::isnan(op2));
+
+  if ((isinf(op1) && isinf(op2)) || ((op1 == 0.0) && (op2 == 0.0))) {
+    // inf / inf and 0.0 / 0.0 return the default NaN.
+    return FPDefaultNaN<T>();
+  } else {
+    // Other cases should be handled by standard arithmetic.
+    return op1 / op2;
+  }
+}
+
+
+template <typename T>
 T Simulator::FPMax(T a, T b) {
-  if (IsSignallingNaN(a)) {
-    return a;
-  } else if (IsSignallingNaN(b)) {
-    return b;
-  } else if (std::isnan(a)) {
-    ASSERT(IsQuietNaN(a));
-    return a;
-  } else if (std::isnan(b)) {
-    ASSERT(IsQuietNaN(b));
-    return b;
-  }
+  // NaNs should be handled elsewhere.
+  ASSERT(!std::isnan(a) && !std::isnan(b));
 
   if ((a == 0.0) && (b == 0.0) &&
       (copysign(1.0, a) != copysign(1.0, b))) {
     // a and b are zero, and the sign differs: return +0.0.
     return 0.0;
   } else {
     return (a > b) ? a : b;
   }
 }
 
 
 template <typename T>
 T Simulator::FPMaxNM(T a, T b) {
   if (IsQuietNaN(a) && !IsQuietNaN(b)) {
     a = kFP64NegativeInfinity;
   } else if (!IsQuietNaN(a) && IsQuietNaN(b)) {
     b = kFP64NegativeInfinity;
   }
-  return FPMax(a, b);
+
+  T result = FPProcessNaNs(a, b);
+  return std::isnan(result) ? result : FPMax(a, b);
 }
 
 template <typename T>
 T Simulator::FPMin(T a, T b) {
-  if (IsSignallingNaN(a)) {
-    return a;
-  } else if (IsSignallingNaN(b)) {
-    return b;
-  } else if (std::isnan(a)) {
-    ASSERT(IsQuietNaN(a));
-    return a;
-  } else if (std::isnan(b)) {
-    ASSERT(IsQuietNaN(b));
-    return b;
-  }
+  // NaNs should be handled elsewhere.
+  ASSERT(!isnan(a) && !isnan(b));
 
   if ((a == 0.0) && (b == 0.0) &&
       (copysign(1.0, a) != copysign(1.0, b))) {
     // a and b are zero, and the sign differs: return -0.0.
     return -0.0;
   } else {
     return (a < b) ? a : b;
   }
 }
 
 
 template <typename T>
 T Simulator::FPMinNM(T a, T b) {
   if (IsQuietNaN(a) && !IsQuietNaN(b)) {
     a = kFP64PositiveInfinity;
   } else if (!IsQuietNaN(a) && IsQuietNaN(b)) {
     b = kFP64PositiveInfinity;
   }
-  return FPMin(a, b);
+
+  T result = FPProcessNaNs(a, b);
+  return isnan(result) ? result : FPMin(a, b);
 }
 
 
+template <typename T>
+T Simulator::FPMul(T op1, T op2) {
+  // NaNs should be handled elsewhere.
+  ASSERT(!std::isnan(op1) && !std::isnan(op2));
+
+  if ((isinf(op1) && (op2 == 0.0)) || (isinf(op2) && (op1 == 0.0))) {
+    // inf * 0.0 returns the default NaN.
+    return FPDefaultNaN<T>();
+  } else {
+    // Other cases should be handled by standard arithmetic.
+    return op1 * op2;
+  }
+}
+
+
+template<typename T>
+T Simulator::FPMulAdd(T a, T op1, T op2) {
+  T result = FPProcessNaNs3(a, op1, op2);
+
+  T sign_a = copysign(1.0, a);
+  T sign_prod = copysign(1.0, op1) * copysign(1.0, op2);
+  bool isinf_prod = std::isinf(op1) || std::isinf(op2);
+  bool operation_generates_nan =
+      (std::isinf(op1) && (op2 == 0.0)) ||                      // inf * 0.0
+      (std::isinf(op2) && (op1 == 0.0)) ||                      // 0.0 * inf
+      (std::isinf(a) && isinf_prod && (sign_a != sign_prod));   // inf - inf
+
+  if (std::isnan(result)) {
+    // Generated NaNs override quiet NaNs propagated from a.
+    if (operation_generates_nan && IsQuietNaN(a)) {
+      return FPDefaultNaN<T>();
+    } else {
+      return result;
+    }
+  }
+
+  // If the operation would produce a NaN, return the default NaN.
+  if (operation_generates_nan) {
+    return FPDefaultNaN<T>();
+  }
+
+  // Work around broken fma implementations for exact zero results: The sign of
+  // exact 0.0 results is positive unless both a and op1 * op2 are negative.
+  if (((op1 == 0.0) || (op2 == 0.0)) && (a == 0.0)) {
+    return ((sign_a < 0) && (sign_prod < 0)) ? -0.0 : 0.0;
+  }
+
+  result = FusedMultiplyAdd(op1, op2, a);
+  ASSERT(!std::isnan(result));
+
+  // Work around broken fma implementations for rounded zero results: If a is
+  // 0.0, the sign of the result is the sign of op1 * op2 before rounding.
+  if ((a == 0.0) && (result == 0.0)) {
+    return copysign(0.0, sign_prod);
+  }
+
+  return result;
+}
+
+
+template <typename T>
+T Simulator::FPSqrt(T op) {
+  if (std::isnan(op)) {
+    return FPProcessNaN(op);
+  } else if (op < 0.0) {
+    return FPDefaultNaN<T>();
+  } else {
+    return std::sqrt(op);
+  }
+}
+
+
+template <typename T>
+T Simulator::FPSub(T op1, T op2) {
+  // NaNs should be handled elsewhere.
+  ASSERT(!std::isnan(op1) && !std::isnan(op2));
+
+  if (isinf(op1) && isinf(op2) && (op1 == op2)) {
+    // inf - inf returns the default NaN.
+    return FPDefaultNaN<T>();
+  } else {
+    // Other cases should be handled by standard arithmetic.
+    return op1 - op2;
+  }
+}
+
+
+template <typename T>
+T Simulator::FPProcessNaN(T op) {
+  ASSERT(std::isnan(op));
+  return DN() ? FPDefaultNaN<T>() : ToQuietNaN(op);
+}
+
+
+template <typename T>
+T Simulator::FPProcessNaNs(T op1, T op2) {
+  if (IsSignallingNaN(op1)) {
+    return FPProcessNaN(op1);
+  } else if (IsSignallingNaN(op2)) {
+    return FPProcessNaN(op2);
+  } else if (std::isnan(op1)) {
+    ASSERT(IsQuietNaN(op1));
+    return FPProcessNaN(op1);
+  } else if (std::isnan(op2)) {
+    ASSERT(IsQuietNaN(op2));
+    return FPProcessNaN(op2);
+  } else {
+    return 0.0;
+  }
+}
+
+
+template <typename T>
+T Simulator::FPProcessNaNs3(T op1, T op2, T op3) {
+  if (IsSignallingNaN(op1)) {
+    return FPProcessNaN(op1);
+  } else if (IsSignallingNaN(op2)) {
+    return FPProcessNaN(op2);
+  } else if (IsSignallingNaN(op3)) {
+    return FPProcessNaN(op3);
+  } else if (std::isnan(op1)) {
+    ASSERT(IsQuietNaN(op1));
+    return FPProcessNaN(op1);
+  } else if (std::isnan(op2)) {
+    ASSERT(IsQuietNaN(op2));
+    return FPProcessNaN(op2);
+  } else if (std::isnan(op3)) {
+    ASSERT(IsQuietNaN(op3));
+    return FPProcessNaN(op3);
+  } else {
+    return 0.0;
+  }
+}
+
+
+bool Simulator::FPProcessNaNs(Instruction* instr) {
+  unsigned fd = instr->Rd();
+  unsigned fn = instr->Rn();
+  unsigned fm = instr->Rm();
+  bool done = false;
+
+  if (instr->Mask(FP64) == FP64) {
+    double result = FPProcessNaNs(dreg(fn), dreg(fm));
+    if (std::isnan(result)) {
+      set_dreg(fd, result);
+      done = true;
+    }
+  } else {
+    float result = FPProcessNaNs(sreg(fn), sreg(fm));
+    if (std::isnan(result)) {
+      set_sreg(fd, result);
+      done = true;
+    }
+  }
+
+  return done;
+}
+
+
 void Simulator::VisitSystem(Instruction* instr) {
   // Some system instructions hijack their Op and Cp fields to represent a
   // range of immediates instead of indicating a different instruction. This
   // makes the decoding tricky.
   if (instr->Mask(SystemSysRegFMask) == SystemSysRegFixed) {
     switch (instr->Mask(SystemSysRegMask)) {
       case MRS: {
         switch (instr->ImmSystemRegister()) {
           case NZCV: set_xreg(instr->Rt(), nzcv().RawValue()); break;
           case FPCR: set_xreg(instr->Rt(), fpcr().RawValue()); break;
@@ skipping 756 matching lines @@
     default:
       UNIMPLEMENTED();
   }
 }
 
 #endif  // USE_SIMULATOR
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_A64