Experimental parser: merge r19949

src/a64/macro-assembler-a64.h

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 339 matching lines @@
                      const FPRegister& fn,
                      const FPRegister& fm);
   inline void Fmin(const FPRegister& fd,
                    const FPRegister& fn,
                    const FPRegister& fm);
   inline void Fminnm(const FPRegister& fd,
                      const FPRegister& fn,
                      const FPRegister& fm);
   inline void Fmov(FPRegister fd, FPRegister fn);
   inline void Fmov(FPRegister fd, Register rn);
+  // Provide explicit double and float interfaces for FP immediate moves, rather
+  // than relying on implicit C++ casts. This allows signalling NaNs to be
+  // preserved when the immediate matches the format of fd. Most systems convert
+  // signalling NaNs to quiet NaNs when converting between float and double.
   inline void Fmov(FPRegister fd, double imm);
+  inline void Fmov(FPRegister fd, float imm);
+  // Provide a template to allow other types to be converted automatically.
+  template<typename T>
+  void Fmov(FPRegister fd, T imm) {
+    ASSERT(allow_macro_instructions_);
+    Fmov(fd, static_cast<double>(imm));
+  }
   inline void Fmov(Register rd, FPRegister fn);
   inline void Fmsub(const FPRegister& fd,
                     const FPRegister& fn,
                     const FPRegister& fm,
                     const FPRegister& fa);
   inline void Fmul(const FPRegister& fd,
                    const FPRegister& fn,
                    const FPRegister& fm);
   inline void Fneg(const FPRegister& fd, const FPRegister& fn);
   inline void Fnmadd(const FPRegister& fd,
@@ skipping 16 matching lines @@
   inline void Isb();
   inline void Ldnp(const CPURegister& rt,
                    const CPURegister& rt2,
                    const MemOperand& src);
   inline void Ldp(const CPURegister& rt,
                   const CPURegister& rt2,
                   const MemOperand& src);
   inline void Ldpsw(const Register& rt,
                     const Register& rt2,
                     const MemOperand& src);
+  // Provide both double and float interfaces for FP immediate loads, rather
+  // than relying on implicit C++ casts. This allows signalling NaNs to be
+  // preserved when the immediate matches the format of fd. Most systems convert
+  // signalling NaNs to quiet NaNs when converting between float and double.
   inline void Ldr(const FPRegister& ft, double imm);
+  inline void Ldr(const FPRegister& ft, float imm);
   inline void Ldr(const Register& rt, uint64_t imm);
   inline void Lsl(const Register& rd, const Register& rn, unsigned shift);
   inline void Lsl(const Register& rd, const Register& rn, const Register& rm);
   inline void Lsr(const Register& rd, const Register& rn, unsigned shift);
   inline void Lsr(const Register& rd, const Register& rn, const Register& rm);
   inline void Madd(const Register& rd,
                    const Register& rn,
                    const Register& rm,
                    const Register& ra);
   inline void Mneg(const Register& rd, const Register& rn, const Register& rm);
@@ skipping 105 matching lines @@
   // must be aligned to 16 bytes on entry and the total size of the specified
   // registers must also be a multiple of 16 bytes.
   //
   // Even if the current stack pointer is not the system stack pointer (csp),
   // Push (and derived methods) will still modify the system stack pointer in
   // order to comply with ABI rules about accessing memory below the system
   // stack pointer.
   //
   // Other than the registers passed into Pop, the stack pointer and (possibly)
   // the system stack pointer, these methods do not modify any other registers.
-  // Scratch registers such as Tmp0() and Tmp1() are preserved.
   void Push(const CPURegister& src0, const CPURegister& src1 = NoReg,
             const CPURegister& src2 = NoReg, const CPURegister& src3 = NoReg);
   void Pop(const CPURegister& dst0, const CPURegister& dst1 = NoReg,
            const CPURegister& dst2 = NoReg, const CPURegister& dst3 = NoReg);
 
   // Alternative forms of Push and Pop, taking a RegList or CPURegList that
   // specifies the registers that are to be pushed or popped. Higher-numbered
   // registers are associated with higher memory addresses (as in the A32 push
   // and pop instructions).
   //
   // (Push|Pop)SizeRegList allow you to specify the register size as a
-  // parameter. Only kXRegSize, kWRegSize, kDRegSize and kSRegSize are
-  // supported.
+  // parameter. Only kXRegSizeInBits, kWRegSizeInBits, kDRegSizeInBits and
+  // kSRegSizeInBits are supported.
   //
   // Otherwise, (Push|Pop)(CPU|X|W|D|S)RegList is preferred.
   void PushCPURegList(CPURegList registers);
   void PopCPURegList(CPURegList registers);
 
   inline void PushSizeRegList(RegList registers, unsigned reg_size,
       CPURegister::RegisterType type = CPURegister::kRegister) {
     PushCPURegList(CPURegList(type, reg_size, registers));
   }
   inline void PopSizeRegList(RegList registers, unsigned reg_size,
       CPURegister::RegisterType type = CPURegister::kRegister) {
     PopCPURegList(CPURegList(type, reg_size, registers));
   }
   inline void PushXRegList(RegList regs) {
-    PushSizeRegList(regs, kXRegSize);
+    PushSizeRegList(regs, kXRegSizeInBits);
   }
   inline void PopXRegList(RegList regs) {
-    PopSizeRegList(regs, kXRegSize);
+    PopSizeRegList(regs, kXRegSizeInBits);
   }
   inline void PushWRegList(RegList regs) {
-    PushSizeRegList(regs, kWRegSize);
+    PushSizeRegList(regs, kWRegSizeInBits);
   }
   inline void PopWRegList(RegList regs) {
-    PopSizeRegList(regs, kWRegSize);
+    PopSizeRegList(regs, kWRegSizeInBits);
   }
   inline void PushDRegList(RegList regs) {
-    PushSizeRegList(regs, kDRegSize, CPURegister::kFPRegister);
+    PushSizeRegList(regs, kDRegSizeInBits, CPURegister::kFPRegister);
   }
   inline void PopDRegList(RegList regs) {
-    PopSizeRegList(regs, kDRegSize, CPURegister::kFPRegister);
+    PopSizeRegList(regs, kDRegSizeInBits, CPURegister::kFPRegister);
   }
   inline void PushSRegList(RegList regs) {
-    PushSizeRegList(regs, kSRegSize, CPURegister::kFPRegister);
+    PushSizeRegList(regs, kSRegSizeInBits, CPURegister::kFPRegister);
   }
   inline void PopSRegList(RegList regs) {
-    PopSizeRegList(regs, kSRegSize, CPURegister::kFPRegister);
+    PopSizeRegList(regs, kSRegSizeInBits, CPURegister::kFPRegister);
   }
 
   // Push the specified register 'count' times.
   void PushMultipleTimes(CPURegister src, Register count);
   void PushMultipleTimes(CPURegister src, int count);
 
   // This is a convenience method for pushing a single Handle<Object>.
   inline void Push(Handle<Object> handle);
   void Push(Smi* smi) { Push(Handle<Smi>(smi, isolate())); }
 
@@ skipping 65 matching lines @@
   //
   // In debug mode, both of these will write invalid data into the claimed or
   // dropped space.
   //
   // If the current stack pointer (according to StackPointer()) is csp, then it
   // must be aligned to 16 bytes and the size claimed or dropped must be a
   // multiple of 16 bytes.
   //
   // Note that unit_size must be specified in bytes. For variants which take a
   // Register count, the unit size must be a power of two.
-  inline void Claim(uint64_t count, uint64_t unit_size = kXRegSizeInBytes);
+  inline void Claim(uint64_t count, uint64_t unit_size = kXRegSize);
   inline void Claim(const Register& count,
-                    uint64_t unit_size = kXRegSizeInBytes);
-  inline void Drop(uint64_t count, uint64_t unit_size = kXRegSizeInBytes);
+                    uint64_t unit_size = kXRegSize);
+  inline void Drop(uint64_t count, uint64_t unit_size = kXRegSize);
   inline void Drop(const Register& count,
-                   uint64_t unit_size = kXRegSizeInBytes);
+                   uint64_t unit_size = kXRegSize);
 
   // Variants of Claim and Drop, where the 'count' parameter is a SMI held in a
   // register.
   inline void ClaimBySMI(const Register& count_smi,
-                         uint64_t unit_size = kXRegSizeInBytes);
+                         uint64_t unit_size = kXRegSize);
   inline void DropBySMI(const Register& count_smi,
-                        uint64_t unit_size = kXRegSizeInBytes);
+                        uint64_t unit_size = kXRegSize);
 
   // Compare a register with an operand, and branch to label depending on the
   // condition. May corrupt the status flags.
   inline void CompareAndBranch(const Register& lhs,
                                const Operand& rhs,
                                Condition cond,
                                Label* label);
 
   // Test the bits of register defined by bit_pattern, and branch if ANY of
   // those bits are set. May corrupt the status flags.
@@ skipping 58 matching lines @@
   // Floating-point registers are popped after general-purpose registers, and
   // thus come from higher addresses.
   //
   // This method must not be called unless the current stack pointer (as set by
   // SetStackPointer) is the system stack pointer (csp), and is aligned to
   // ActivationFrameAlignment().
   void PopCalleeSavedRegisters();
 
   // Set the current stack pointer, but don't generate any code.
   inline void SetStackPointer(const Register& stack_pointer) {
-    ASSERT(!AreAliased(stack_pointer, Tmp0(), Tmp1()));
+    ASSERT(!TmpList()->IncludesAliasOf(stack_pointer));
     sp_ = stack_pointer;
   }
 
   // Return the current stack pointer, as set by SetStackPointer.
   inline const Register& StackPointer() const {
     return sp_;
   }
 
   // Align csp for a frame, as per ActivationFrameAlignment, and make it the
   // current stack pointer.
@@ skipping 173 matching lines @@
                                Label* on_failed_conversion = NULL) {
     ASSERT(as_int.Is64Bits());
     TryConvertDoubleToInt(as_int, value, scratch_d, on_successful_conversion,
                           on_failed_conversion);
   }
 
   // ---- Object Utilities ----
 
   // Copy fields from 'src' to 'dst', where both are tagged objects.
   // The 'temps' list is a list of X registers which can be used for scratch
-  // values. The temps list must include at least one register, and it must not
-  // contain Tmp0() or Tmp1().
+  // values. The temps list must include at least one register.
   //
   // Currently, CopyFields cannot make use of more than three registers from
   // the 'temps' list.
   //
-  // As with several MacroAssembler methods, Tmp0() and Tmp1() will be used.
+  // CopyFields expects to be able to take at least two registers from
+  // MacroAssembler::TmpList().
   void CopyFields(Register dst, Register src, CPURegList temps, unsigned count);
 
+  // Starting at address in dst, initialize field_count 64-bit fields with
+  // 64-bit value in register filler. Register dst is corrupted.
+  void FillFields(Register dst,
+                  Register field_count,
+                  Register filler);
+
   // Copies a number of bytes from src to dst. All passed registers are
   // clobbered. On exit src and dst will point to the place just after where the
   // last byte was read or written and length will be zero. Hint may be used to
   // determine which is the most efficient algorithm to use for copying.
   void CopyBytes(Register dst,
                  Register src,
                  Register length,
                  Register scratch,
                  CopyHint hint = kCopyUnknown);
 
-  // Initialize fields with filler values. Fields starting at start_offset not
-  // including end_offset are overwritten with the value in filler. At the end
-  // of the loop, start_offset takes the value of end_offset.
-  void InitializeFieldsWithFiller(Register start_offset,
-                                  Register end_offset,
-                                  Register filler);
-
   // ---- String Utilities ----
 
 
   // Jump to label if either object is not a sequential ASCII string.
   // Optionally perform a smi check on the objects first.
   void JumpIfEitherIsNotSequentialAsciiStrings(
       Register first,
       Register second,
       Register scratch1,
       Register scratch2,
@@ skipping 62 matching lines @@
   void CallRuntime(const Runtime::Function* f,
                    int num_arguments,
                    SaveFPRegsMode save_doubles = kDontSaveFPRegs);
 
   void CallRuntime(Runtime::FunctionId id,
                    int num_arguments,
                    SaveFPRegsMode save_doubles = kDontSaveFPRegs) {
     CallRuntime(Runtime::FunctionForId(id), num_arguments, save_doubles);
   }
 
-  // TODO(all): Why does this variant save FP regs unconditionally?
   void CallRuntimeSaveDoubles(Runtime::FunctionId id) {
     const Runtime::Function* function = Runtime::FunctionForId(id);
     CallRuntime(function, function->nargs, kSaveFPRegs);
   }
 
   void TailCallRuntime(Runtime::FunctionId fid,
                        int num_arguments,
                        int result_size);
 
   int ActivationFrameAlignment();
@@ skipping 42 matching lines @@
                              int num_arguments);
 
 
   // Invoke specified builtin JavaScript function. Adds an entry to
   // the unresolved list if the name does not resolve.
   void InvokeBuiltin(Builtins::JavaScript id,
                      InvokeFlag flag,
                      const CallWrapper& call_wrapper = NullCallWrapper());
 
   // Store the code object for the given builtin in the target register and
-  // setup the function in x1.
-  // TODO(all): Can we use another register than x1?
-  void GetBuiltinEntry(Register target, Builtins::JavaScript id);
+  // setup the function in the function register.
+  void GetBuiltinEntry(Register target,
+                       Register function,
+                       Builtins::JavaScript id);
 
   // Store the function for the given builtin in the target register.
   void GetBuiltinFunction(Register target, Builtins::JavaScript id);
 
   void Jump(Register target);
   void Jump(Address target, RelocInfo::Mode rmode);
   void Jump(Handle<Code> code, RelocInfo::Mode rmode);
   void Jump(intptr_t target, RelocInfo::Mode rmode);
 
   void Call(Register target);
@@ skipping 315 matching lines @@
 
   // Test the bitfield of the heap object map with mask and set the condition
   // flags. The object register is preserved.
   void TestMapBitfield(Register object, uint64_t mask);
 
   // Load the elements kind field of an object, and return it in the result
   // register.
   void LoadElementsKind(Register result, Register object);
 
   // Compare the object in a register to a value from the root list.
-  // Uses the Tmp0() register as scratch.
   void CompareRoot(const Register& obj, Heap::RootListIndex index);
 
   // Compare the object in a register to a value and jump if they are equal.
   void JumpIfRoot(const Register& obj,
                   Heap::RootListIndex index,
                   Label* if_equal);
 
   // Compare the object in a register to a value and jump if they are not equal.
   void JumpIfNotRoot(const Register& obj,
                      Heap::RootListIndex index,
@@ skipping 86 matching lines @@
   void EmitSeqStringSetCharCheck(Register string,
                                  Register index,
                                  SeqStringSetCharCheckIndexType index_type,
                                  Register scratch,
                                  uint32_t encoding_mask);
 
   // Generate code for checking access rights - used for security checks
   // on access to global objects across environments. The holder register
   // is left untouched, whereas both scratch registers are clobbered.
   void CheckAccessGlobalProxy(Register holder_reg,
-                              Register scratch,
+                              Register scratch1,
+                              Register scratch2,
                               Label* miss);
 
   // Hash the interger value in 'key' register.
   // It uses the same algorithm as ComputeIntegerHash in utils.h.
   void GetNumberHash(Register key, Register scratch);
 
   // Load value from the dictionary.
   //
   // elements - holds the slow-case elements of the receiver on entry.
   //            Unchanged unless 'result' is the same register.
@@ skipping 11 matching lines @@
                                 Register result,
                                 Register scratch0,
                                 Register scratch1,
                                 Register scratch2,
                                 Register scratch3);
 
   // ---------------------------------------------------------------------------
   // Frames.
 
   // Activation support.
-  // Note that Tmp0() and Tmp1() are used as a scratch registers. This is safe
-  // because these methods are not used in Crankshaft.
   void EnterFrame(StackFrame::Type type);
   void LeaveFrame(StackFrame::Type type);
 
   // Returns map with validated enum cache in object register.
   void CheckEnumCache(Register object,
                       Register null_value,
                       Register scratch0,
                       Register scratch1,
                       Register scratch2,
                       Register scratch3,
@@ skipping 67 matching lines @@
   //  * The exit frame is dropped.
   //  * The stack pointer is reset to jssp.
   //
   // The stack pointer must be csp on entry.
   void LeaveExitFrame(bool save_doubles,
                       const Register& scratch,
                       bool restore_context);
 
   void LoadContext(Register dst, int context_chain_length);
 
+  // Emit code for a flooring division by a constant. The dividend register is
+  // unchanged. Dividend and result must be different.
+  void FlooringDiv(Register result, Register dividend, int32_t divisor);
+
   // ---------------------------------------------------------------------------
   // StatsCounter support
 
   void SetCounter(StatsCounter* counter, int value, Register scratch1,
                   Register scratch2);
   void IncrementCounter(StatsCounter* counter, int value, Register scratch1,
                         Register scratch2);
   void DecrementCounter(StatsCounter* counter, int value, Register scratch1,
                         Register scratch2);
 
   // ---------------------------------------------------------------------------
   // Garbage collector support (GC).
 
   enum RememberedSetFinalAction {
     kReturnAtEnd,
     kFallThroughAtEnd
   };
 
   // Record in the remembered set the fact that we have a pointer to new space
   // at the address pointed to by the addr register. Only works if addr is not
   // in new space.
   void RememberedSetHelper(Register object,  // Used for debug code.
                            Register addr,
-                           Register scratch,
+                           Register scratch1,
                            SaveFPRegsMode save_fp,
                            RememberedSetFinalAction and_then);
 
   // Push and pop the registers that can hold pointers, as defined by the
   // RegList constant kSafepointSavedRegisters.
   void PushSafepointRegisters();
   void PopSafepointRegisters();
 
   void PushSafepointFPRegisters();
   void PopSafepointFPRegisters();
@@ skipping 164 matching lines @@
   void Abort(BailoutReason reason);
 
   // Conditionally load the cached Array transitioned map of type
   // transitioned_kind from the native context if the map in register
   // map_in_out is the cached Array map in the native context of
   // expected_kind.
   void LoadTransitionedArrayMapConditional(
       ElementsKind expected_kind,
       ElementsKind transitioned_kind,
       Register map_in_out,
-      Register scratch,
+      Register scratch1,
+      Register scratch2,
       Label* no_map_match);
 
   void LoadGlobalFunction(int index, Register function);
 
   // Load the initial map from the global function. The registers function and
   // map can be the same, function is then overwritten.
   void LoadGlobalFunctionInitialMap(Register function,
                                     Register map,
                                     Register scratch);
 
-  // --------------------------------------------------------------------------
-  // Set the registers used internally by the MacroAssembler as scratch
-  // registers. These registers are used to implement behaviours which are not
-  // directly supported by A64, and where an intermediate result is required.
-  //
-  // Both tmp0 and tmp1 may be set to any X register except for xzr, sp,
-  // and StackPointer(). Also, they must not be the same register (though they
-  // may both be NoReg).
-  //
-  // It is valid to set either or both of these registers to NoReg if you don't
-  // want the MacroAssembler to use any scratch registers. In a debug build, the
-  // Assembler will assert that any registers it uses are valid. Be aware that
-  // this check is not present in release builds. If this is a problem, use the
-  // Assembler directly.
-  void SetScratchRegisters(const Register& tmp0, const Register& tmp1) {
-    // V8 assumes the macro assembler uses ip0 and ip1 as temp registers.
-    ASSERT(tmp0.IsNone() || tmp0.Is(ip0));
-    ASSERT(tmp1.IsNone() || tmp1.Is(ip1));
-
-    ASSERT(!AreAliased(xzr, csp, tmp0, tmp1));
-    ASSERT(!AreAliased(StackPointer(), tmp0, tmp1));
-    tmp0_ = tmp0;
-    tmp1_ = tmp1;
-  }
-
-  const Register& Tmp0() const {
-    return tmp0_;
-  }
-
-  const Register& Tmp1() const {
-    return tmp1_;
-  }
-
-  const Register WTmp0() const {
-    return Register::Create(tmp0_.code(), kWRegSize);
-  }
-
-  const Register WTmp1() const {
-    return Register::Create(tmp1_.code(), kWRegSize);
-  }
-
-  void SetFPScratchRegister(const FPRegister& fptmp0) {
-    fptmp0_ = fptmp0;
-  }
-
-  const FPRegister& FPTmp0() const {
-    return fptmp0_;
-  }
-
-  const Register AppropriateTempFor(
-      const Register& target,
-      const CPURegister& forbidden = NoCPUReg) const {
-    Register candidate = forbidden.Is(Tmp0()) ? Tmp1() : Tmp0();
-    ASSERT(!candidate.Is(target));
-    return Register::Create(candidate.code(), target.SizeInBits());
-  }
-
-  const FPRegister AppropriateTempFor(
-      const FPRegister& target,
-      const CPURegister& forbidden = NoCPUReg) const {
-    USE(forbidden);
-    FPRegister candidate = FPTmp0();
-    ASSERT(!candidate.Is(forbidden));
-    ASSERT(!candidate.Is(target));
-    return FPRegister::Create(candidate.code(), target.SizeInBits());
-  }
+  CPURegList* TmpList() { return &tmp_list_; }
+  CPURegList* FPTmpList() { return &fptmp_list_; }
 
   // Like printf, but print at run-time from generated code.
   //
   // The caller must ensure that arguments for floating-point placeholders
   // (such as %e, %f or %g) are FPRegisters, and that arguments for integer
   // placeholders are Registers.
   //
   // A maximum of four arguments may be given to any single Printf call. The
   // arguments must be of the same type, but they do not need to have the same
   // size.
   //
   // The following registers cannot be printed:
-  //    Tmp0(), Tmp1(), StackPointer(), csp.
+  //    StackPointer(), csp.
   //
   // This function automatically preserves caller-saved registers so that
   // calling code can use Printf at any point without having to worry about
   // corruption. The preservation mechanism generates a lot of code. If this is
   // a problem, preserve the important registers manually and then call
   // PrintfNoPreserve. Callee-saved registers are not used by Printf, and are
   // implicitly preserved.
   //
   // Unlike many MacroAssembler functions, x8 and x9 are guaranteed to be
   // preserved, and can be printed. This allows Printf to be used during debug
@@ skipping 64 matching lines @@
 
   // Jumps to found label if a prototype map has dictionary elements.
   void JumpIfDictionaryInPrototypeChain(Register object, Register scratch0,
                                         Register scratch1, Label* found);
 
  private:
   // Helpers for CopyFields.
   // These each implement CopyFields in a different way.
   void CopyFieldsLoopPairsHelper(Register dst, Register src, unsigned count,
                                  Register scratch1, Register scratch2,
-                                 Register scratch3);
+                                 Register scratch3, Register scratch4,
+                                 Register scratch5);
   void CopyFieldsUnrolledPairsHelper(Register dst, Register src, unsigned count,
-                                     Register scratch1, Register scratch2);
+                                     Register scratch1, Register scratch2,
+                                     Register scratch3, Register scratch4);
   void CopyFieldsUnrolledHelper(Register dst, Register src, unsigned count,
-                                Register scratch1);
+                                Register scratch1, Register scratch2,
+                                Register scratch3);
 
   // The actual Push and Pop implementations. These don't generate any code
   // other than that required for the push or pop. This allows
   // (Push|Pop)CPURegList to bundle together run-time assertions for a large
   // block of registers.
   //
   // Note that size is per register, and is specified in bytes.
   void PushHelper(int count, int size,
                   const CPURegister& src0, const CPURegister& src1,
                   const CPURegister& src2, const CPURegister& src3);
@@ skipping 60 matching lines @@
   // The purpose of this is to allow Aborts to be compiled whilst CEntryStub is
   // being generated.
   bool use_real_aborts_;
 
   // This handle will be patched with the code object on installation.
   Handle<Object> code_object_;
 
   // The register to use as a stack pointer for stack operations.
   Register sp_;
 
-  // Scratch registers used internally by the MacroAssembler.
-  Register tmp0_;
-  Register tmp1_;
-  FPRegister fptmp0_;
+  // Scratch registers available for use by the MacroAssembler.
+  CPURegList tmp_list_;
+  CPURegList fptmp_list_;
 
   void InitializeNewString(Register string,
                            Register length,
                            Heap::RootListIndex map_index,
                            Register scratch1,
                            Register scratch2);
 
  public:
   // Far branches resolving.
   //
   // The various classes of branch instructions with immediate offsets have
   // different ranges. While the Assembler will fail to assemble a branch
   // exceeding its range, the MacroAssembler offers a mechanism to resolve
   // branches to too distant targets, either by tweaking the generated code to
   // use branch instructions with wider ranges or generating veneers.
   //
   // Currently branches to distant targets are resolved using unconditional
   // branch isntructions with a range of +-128MB. If that becomes too little
   // (!), the mechanism can be extended to generate special veneers for really
   // far targets.
 
-  // Returns true if we should emit a veneer as soon as possible for a branch
-  // which can at most reach to specified pc.
-  bool ShouldEmitVeneer(int max_reachable_pc,
-                        int margin = kVeneerDistanceMargin);
-
-  // The maximum code size generated for a veneer. Currently one branch
-  // instruction. This is for code size checking purposes, and can be extended
-  // in the future for example if we decide to add nops between the veneers.
-  static const int kMaxVeneerCodeSize = 1 * kInstructionSize;
-
-  // Emits veneers for branches that are approaching their maximum range.
-  // If need_protection is true, the veneers are protected by a branch jumping
-  // over the code.
-  void EmitVeneers(bool need_protection);
-  void EmitVeneersGuard();
-  // Checks wether veneers need to be emitted at this point.
-  void CheckVeneers(bool need_protection);
-
   // Helps resolve branching to labels potentially out of range.
   // If the label is not bound, it registers the information necessary to later
   // be able to emit a veneer for this branch if necessary.
   // If the label is bound, it returns true if the label (or the previous link
   // in the label chain) is out of range. In that case the caller is responsible
   // for generating appropriate code.
   // Otherwise it returns false.
   // This function also checks wether veneers need to be emitted.
   bool NeedExtraInstructionsOrRegisterBranch(Label *label,
                                              ImmBranchType branch_type);
-
- private:
-  // We generate a veneer for a branch if we reach within this distance of the
-  // limit of the range.
-  static const int kVeneerDistanceMargin = 4 * KB;
-  int unresolved_branches_first_limit() const {
-    ASSERT(!unresolved_branches_.empty());
-    return unresolved_branches_.begin()->first;
-  }
 };
 
 
 // Use this scope when you need a one-to-one mapping bewteen methods and
 // instructions. This scope prevents the MacroAssembler from being called and
 // literal pools from being emitted. It also asserts the number of instructions
 // emitted is what you specified when creating the scope.
 class InstructionAccurateScope BASE_EMBEDDED {
  public:
   InstructionAccurateScope(MacroAssembler* masm, size_t count = 0)
@@ skipping 29 matching lines @@
  private:
   MacroAssembler* masm_;
 #ifdef DEBUG
   size_t size_;
   Label start_;
   bool previous_allow_macro_instructions_;
 #endif
 };
 
 
+// This scope utility allows scratch registers to be managed safely. The
+// MacroAssembler's TmpList() (and FPTmpList()) is used as a pool of scratch
+// registers. These registers can be allocated on demand, and will be returned
+// at the end of the scope.
+//
+// When the scope ends, the MacroAssembler's lists will be restored to their
+// original state, even if the lists were modified by some other means.
+class UseScratchRegisterScope {
+ public:
+  explicit UseScratchRegisterScope(MacroAssembler* masm)
+      : available_(masm->TmpList()),
+        availablefp_(masm->FPTmpList()),
+        old_available_(available_->list()),
+        old_availablefp_(availablefp_->list()) {
+    ASSERT(available_->type() == CPURegister::kRegister);
+    ASSERT(availablefp_->type() == CPURegister::kFPRegister);
+  }
+
+  ~UseScratchRegisterScope();
+
+  // Take a register from the appropriate temps list. It will be returned
+  // automatically when the scope ends.
+  Register AcquireW() { return AcquireNextAvailable(available_).W(); }
+  Register AcquireX() { return AcquireNextAvailable(available_).X(); }
+  FPRegister AcquireS() { return AcquireNextAvailable(availablefp_).S(); }
+  FPRegister AcquireD() { return AcquireNextAvailable(availablefp_).D(); }
+
+  Register AcquireSameSizeAs(const Register& reg);
+  FPRegister AcquireSameSizeAs(const FPRegister& reg);
+
+ private:
+  static CPURegister AcquireNextAvailable(CPURegList* available);
+
+  // Available scratch registers.
+  CPURegList* available_;     // kRegister
+  CPURegList* availablefp_;   // kFPRegister
+
+  // The state of the available lists at the start of this scope.
+  RegList old_available_;     // kRegister
+  RegList old_availablefp_;   // kFPRegister
+};
+
+
 inline MemOperand ContextMemOperand(Register context, int index) {
   return MemOperand(context, Context::SlotOffset(index));
 }
 
 inline MemOperand GlobalObjectMemOperand() {
   return ContextMemOperand(cp, Context::GLOBAL_OBJECT_INDEX);
 }
 
 
 // Encode and decode information about patchable inline SMI checks.
@@ skipping 50 matching lines @@
 #error "Unsupported option"
 #define CODE_COVERAGE_STRINGIFY(x) #x
 #define CODE_COVERAGE_TOSTRING(x) CODE_COVERAGE_STRINGIFY(x)
 #define __FILE_LINE__ __FILE__ ":" CODE_COVERAGE_TOSTRING(__LINE__)
 #define ACCESS_MASM(masm) masm->stop(__FILE_LINE__); masm->
 #else
 #define ACCESS_MASM(masm) masm->
 #endif
 
 #endif  // V8_A64_MACRO_ASSEMBLER_A64_H_