Experimental parser: merge r19949

src/a64/disasm-a64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 237 matching lines @@
     Format(instr, "unallocated", "(LogicalImmediate)");
     return;
   }
 
   switch (instr->Mask(LogicalImmediateMask)) {
     case AND_w_imm:
     case AND_x_imm: mnemonic = "and"; break;
     case ORR_w_imm:
     case ORR_x_imm: {
       mnemonic = "orr";
-      unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSize
-                                                        : kWRegSize;
+      unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSizeInBits
+                                                        : kWRegSizeInBits;
       if (rn_is_zr && !IsMovzMovnImm(reg_size, instr->ImmLogical())) {
         mnemonic = "mov";
         form = "'Rds, 'ITri";
       }
       break;
     }
     case EOR_w_imm:
     case EOR_x_imm: mnemonic = "eor"; break;
     case ANDS_w_imm:
     case ANDS_x_imm: {
       mnemonic = "ands";
       if (rd_is_zr) {
         mnemonic = "tst";
         form = "'Rn, 'ITri";
       }
       break;
     }
     default: UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
 bool Disassembler::IsMovzMovnImm(unsigned reg_size, uint64_t value) {
-  ASSERT((reg_size == kXRegSize) ||
-         ((reg_size == kWRegSize) && (value <= 0xffffffff)));
+  ASSERT((reg_size == kXRegSizeInBits) ||
+         ((reg_size == kWRegSizeInBits) && (value <= 0xffffffff)));
 
   // Test for movz: 16-bits set at positions 0, 16, 32 or 48.
   if (((value & 0xffffffffffff0000UL) == 0UL) ||
       ((value & 0xffffffff0000ffffUL) == 0UL) ||
       ((value & 0xffff0000ffffffffUL) == 0UL) ||
       ((value & 0x0000ffffffffffffUL) == 0UL)) {
     return true;
   }
 
   // Test for movn: NOT(16-bits set at positions 0, 16, 32 or 48).
-  if ((reg_size == kXRegSize) &&
+  if ((reg_size == kXRegSizeInBits) &&
       (((value & 0xffffffffffff0000UL) == 0xffffffffffff0000UL) ||
        ((value & 0xffffffff0000ffffUL) == 0xffffffff0000ffffUL) ||
        ((value & 0xffff0000ffffffffUL) == 0xffff0000ffffffffUL) ||
        ((value & 0x0000ffffffffffffUL) == 0x0000ffffffffffffUL))) {
     return true;
   }
-  if ((reg_size == kWRegSize) &&
+  if ((reg_size == kWRegSizeInBits) &&
       (((value & 0xffff0000) == 0xffff0000) ||
        ((value & 0x0000ffff) == 0x0000ffff))) {
     return true;
   }
   return false;
 }
 
 
 void Disassembler::VisitLogicalShifted(Instruction* instr) {
   bool rd_is_zr = RdIsZROrSP(instr);
@@ skipping 126 matching lines @@
     default: UNREACHABLE();
   }
   Format(instr, mnemonic, form);
 }
 
 
 void Disassembler::VisitBitfield(Instruction* instr) {
   unsigned s = instr->ImmS();
   unsigned r = instr->ImmR();
   unsigned rd_size_minus_1 =
-    ((instr->SixtyFourBits() == 1) ? kXRegSize : kWRegSize) - 1;
+    ((instr->SixtyFourBits() == 1) ? kXRegSizeInBits : kWRegSizeInBits) - 1;
   const char *mnemonic = "";
   const char *form = "";
   const char *form_shift_right = "'Rd, 'Rn, 'IBr";
   const char *form_extend = "'Rd, 'Wn";
   const char *form_bfiz = "'Rd, 'Rn, 'IBZ-r, 'IBs+1";
   const char *form_bfx = "'Rd, 'Rn, 'IBr, 'IBs-r+1";
   const char *form_lsl = "'Rd, 'Rn, 'IBZ-r";
 
   switch (instr->Mask(BitfieldMask)) {
     case SBFM_w:
@@ skipping 1020 matching lines @@
     case 'S': {  // IS - Test and branch bit.
       AppendToOutput("#%d", (instr->ImmTestBranchBit5() << 5) |
                             instr->ImmTestBranchBit40());
       return 2;
     }
     case 'D': {  // IDebug - HLT and BRK instructions.
       AppendToOutput("#0x%x", instr->ImmException());
       return 6;
     }
     default: {
-      UNIMPLEMENTED();
+      UNREACHABLE();
       return 0;
     }
   }
 }
 
 
 int Disassembler::SubstituteBitfieldImmediateField(Instruction* instr,
                                                    const char* format) {
   ASSERT((format[0] == 'I') && (format[1] == 'B'));
   unsigned r = instr->ImmR();
   unsigned s = instr->ImmS();
 
   switch (format[2]) {
     case 'r': {  // IBr.
       AppendToOutput("#%d", r);
       return 3;
     }
     case 's': {  // IBs+1 or IBs-r+1.
       if (format[3] == '+') {
         AppendToOutput("#%d", s + 1);
         return 5;
       } else {
         ASSERT(format[3] == '-');
         AppendToOutput("#%d", s - r + 1);
         return 7;
       }
     }
     case 'Z': {  // IBZ-r.
       ASSERT((format[3] == '-') && (format[4] == 'r'));
-      unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSize : kWRegSize;
+      unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSizeInBits
+                                                        : kWRegSizeInBits;
       AppendToOutput("#%d", reg_size - r);
       return 5;
     }
     default: {
       UNREACHABLE();
       return 0;
     }
   }
 }
 
@@ skipping 25 matching lines @@
     }  // Fall through.
     case 'L': {  // HLo.
       if (instr->ImmDPShift() != 0) {
         const char* shift_type[] = {"lsl", "lsr", "asr", "ror"};
         AppendToOutput(", %s #%" PRId64, shift_type[instr->ShiftDP()],
                        instr->ImmDPShift());
       }
       return 3;
     }
     default:
-      UNIMPLEMENTED();
+      UNREACHABLE();
       return 0;
   }
 }
 
 
 int Disassembler::SubstituteConditionField(Instruction* instr,
                                            const char* format) {
   ASSERT(format[0] == 'C');
   const char* condition_code[] = { "eq", "ne", "hs", "lo",
                                    "mi", "pl", "vs", "vc",
@@ skipping 21 matching lines @@
   int offset = instr->ImmPCRel();
 
   // Only ADR (AddrPCRelByte) is supported.
   ASSERT(strcmp(format, "AddrPCRelByte") == 0);
 
   char sign = '+';
   if (offset < 0) {
     offset = -offset;
     sign = '-';
   }
-  // TODO(jbramley): Can we print the target address here?
-  AppendToOutput("#%c0x%x", sign, offset);
+  STATIC_ASSERT(sizeof(*instr) == 1);
+  AppendToOutput("#%c0x%x (addr %p)", sign, offset, instr + offset);
   return 13;
 }
 
 
 int Disassembler::SubstituteBranchTargetField(Instruction* instr,
                                               const char* format) {
   ASSERT(strncmp(format, "BImm", 4) == 0);
 
   int64_t offset = 0;
   switch (format[5]) {
     // BImmUncn - unconditional branch immediate.
     case 'n': offset = instr->ImmUncondBranch(); break;
     // BImmCond - conditional branch immediate.
     case 'o': offset = instr->ImmCondBranch(); break;
     // BImmCmpa - compare and branch immediate.
     case 'm': offset = instr->ImmCmpBranch(); break;
     // BImmTest - test and branch immediate.
     case 'e': offset = instr->ImmTestBranch(); break;
-    default: UNIMPLEMENTED();
+    default: UNREACHABLE();
   }
   offset <<= kInstructionSizeLog2;
   char sign = '+';
   if (offset < 0) {
     offset = -offset;
     sign = '-';
   }
-  // TODO(mcapewel): look up pc + offset in label table.
-  AppendToOutput("#%c0x%" PRIx64, sign, offset);
+  STATIC_ASSERT(sizeof(*instr) == 1);
+  AppendToOutput("#%c0x%" PRIx64 " (addr %p)", sign, offset, instr + offset);
   return 8;
 }
 
 
 int Disassembler::SubstituteExtendField(Instruction* instr,
                                         const char* format) {
   ASSERT(strncmp(format, "Ext", 3) == 0);
   ASSERT(instr->ExtendMode() <= 7);
   USE(format);
 
@@ skipping 197 matching lines @@
   decoder.AppendVisitor(&disasm);
 
   for (byte* pc = start; pc < end; pc += v8::internal::kInstructionSize) {
     decoder.Decode(reinterpret_cast<v8::internal::Instruction*>(pc));
   }
 }
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_A64