Experimental parser: merge r19949

src/a64/assembler-a64.h

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 209 matching lines @@
       return NumAllocatableRegisters() - 1;
     }
 
     return (code <= kAllocatableLowRangeEnd)
         ? code
         : code - kAllocatableRangeGapSize;
   }
 
   static Register from_code(int code) {
     // Always return an X register.
-    return Register::Create(code, kXRegSize);
+    return Register::Create(code, kXRegSizeInBits);
   }
 
   // End of V8 compatibility section -----------------------
 };
 
 
 struct FPRegister : public CPURegister {
   static FPRegister Create(unsigned code, unsigned size) {
     return CPURegister::Create(code, size, CPURegister::kFPRegister);
   }
@@ skipping 16 matching lines @@
     return IsValidFPRegister();
   }
 
   static FPRegister SRegFromCode(unsigned code);
   static FPRegister DRegFromCode(unsigned code);
 
   // Start of V8 compatibility section ---------------------
   static const int kMaxNumRegisters = kNumberOfFPRegisters;
 
   // Crankshaft can use all the FP registers except:
-  //   - d29 which is used in crankshaft as a double scratch register
-  //   - d30 which is used to keep the 0 double value
+  //   - d15 which is used to keep the 0 double value
+  //   - d30 which is used in crankshaft as a double scratch register
   //   - d31 which is used in the MacroAssembler as a double scratch register
-  static const int kNumReservedRegisters = 3;
+  static const unsigned kAllocatableLowRangeBegin = 0;
+  static const unsigned kAllocatableLowRangeEnd = 14;
+  static const unsigned kAllocatableHighRangeBegin = 16;
+  static const unsigned kAllocatableHighRangeEnd = 29;
+
+  static const RegList kAllocatableFPRegisters = 0x3fff7fff;
+
+  // Gap between low and high ranges.
+  static const int kAllocatableRangeGapSize =
+      (kAllocatableHighRangeBegin - kAllocatableLowRangeEnd) - 1;
+
   static const int kMaxNumAllocatableRegisters =
-      kNumberOfFPRegisters - kNumReservedRegisters;
+      (kAllocatableLowRangeEnd - kAllocatableLowRangeBegin + 1) +
+      (kAllocatableHighRangeEnd - kAllocatableHighRangeBegin + 1);
   static int NumAllocatableRegisters() { return kMaxNumAllocatableRegisters; }
-  static const RegList kAllocatableFPRegisters =
-      (1 << kMaxNumAllocatableRegisters) - 1;
 
-  static FPRegister FromAllocationIndex(int index) {
-    ASSERT((index >= 0) && (index < NumAllocatableRegisters()));
-    return from_code(index);
+  // Return true if the register is one that crankshaft can allocate.
+  bool IsAllocatable() const {
+    return (Bit() & kAllocatableFPRegisters) != 0;
+  }
+
+  static FPRegister FromAllocationIndex(unsigned int index) {
+    ASSERT(index < static_cast<unsigned>(NumAllocatableRegisters()));
+
+    return (index <= kAllocatableLowRangeEnd)
+        ? from_code(index)
+        : from_code(index + kAllocatableRangeGapSize);
   }
 
   static const char* AllocationIndexToString(int index) {
     ASSERT((index >= 0) && (index < NumAllocatableRegisters()));
+    ASSERT((kAllocatableLowRangeBegin == 0) &&
+           (kAllocatableLowRangeEnd == 14) &&
+           (kAllocatableHighRangeBegin == 16) &&
+           (kAllocatableHighRangeEnd == 29));
     const char* const names[] = {
       "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
-      "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
+      "d8", "d9", "d10", "d11", "d12", "d13", "d14",
       "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
-      "d24", "d25", "d26", "d27", "d28",
+      "d24", "d25", "d26", "d27", "d28", "d29"
     };
     return names[index];
   }
 
   static int ToAllocationIndex(FPRegister reg) {
-    int code = reg.code();
-    ASSERT(code < NumAllocatableRegisters());
-    return code;
+    ASSERT(reg.IsAllocatable());
+    unsigned code = reg.code();
+
+    return (code <= kAllocatableLowRangeEnd)
+        ? code
+        : code - kAllocatableRangeGapSize;
   }
 
   static FPRegister from_code(int code) {
     // Always return a D register.
-    return FPRegister::Create(code, kDRegSize);
+    return FPRegister::Create(code, kDRegSizeInBits);
   }
   // End of V8 compatibility section -----------------------
 };
 
 
 STATIC_ASSERT(sizeof(CPURegister) == sizeof(Register));
 STATIC_ASSERT(sizeof(CPURegister) == sizeof(FPRegister));
 
 
 #if defined(A64_DEFINE_REG_STATICS)
@@ skipping 15 matching lines @@
 // these all compare equal (using the Is() method). The Register and FPRegister
 // variants are provided for convenience.
 INITIALIZE_REGISTER(Register, NoReg, 0, 0, CPURegister::kNoRegister);
 INITIALIZE_REGISTER(FPRegister, NoFPReg, 0, 0, CPURegister::kNoRegister);
 INITIALIZE_REGISTER(CPURegister, NoCPUReg, 0, 0, CPURegister::kNoRegister);
 
 // v8 compatibility.
 INITIALIZE_REGISTER(Register, no_reg, 0, 0, CPURegister::kNoRegister);
 
 #define DEFINE_REGISTERS(N)                                                  \
-  INITIALIZE_REGISTER(Register, w##N, N, kWRegSize, CPURegister::kRegister); \
-  INITIALIZE_REGISTER(Register, x##N, N, kXRegSize, CPURegister::kRegister);
+  INITIALIZE_REGISTER(Register, w##N, N,                                     \
+                      kWRegSizeInBits, CPURegister::kRegister);              \
+  INITIALIZE_REGISTER(Register, x##N, N,                                     \
+                      kXRegSizeInBits, CPURegister::kRegister);
 REGISTER_CODE_LIST(DEFINE_REGISTERS)
 #undef DEFINE_REGISTERS
 
-INITIALIZE_REGISTER(Register, wcsp, kSPRegInternalCode, kWRegSize,
+INITIALIZE_REGISTER(Register, wcsp, kSPRegInternalCode, kWRegSizeInBits,
                     CPURegister::kRegister);
-INITIALIZE_REGISTER(Register, csp, kSPRegInternalCode, kXRegSize,
+INITIALIZE_REGISTER(Register, csp, kSPRegInternalCode, kXRegSizeInBits,
                     CPURegister::kRegister);
 
-#define DEFINE_FPREGISTERS(N)                         \
-  INITIALIZE_REGISTER(FPRegister, s##N, N, kSRegSize, \
-                      CPURegister::kFPRegister);      \
-  INITIALIZE_REGISTER(FPRegister, d##N, N, kDRegSize, CPURegister::kFPRegister);
+#define DEFINE_FPREGISTERS(N)                                                  \
+  INITIALIZE_REGISTER(FPRegister, s##N, N,                                     \
+                      kSRegSizeInBits, CPURegister::kFPRegister);              \
+  INITIALIZE_REGISTER(FPRegister, d##N, N,                                     \
+                      kDRegSizeInBits, CPURegister::kFPRegister);
 REGISTER_CODE_LIST(DEFINE_FPREGISTERS)
 #undef DEFINE_FPREGISTERS
 
 #undef INITIALIZE_REGISTER
 
 // Registers aliases.
 ALIAS_REGISTER(Register, ip0, x16);
 ALIAS_REGISTER(Register, ip1, x17);
 ALIAS_REGISTER(Register, wip0, w16);
 ALIAS_REGISTER(Register, wip1, w17);
 // Root register.
 ALIAS_REGISTER(Register, root, x26);
 ALIAS_REGISTER(Register, rr, x26);
 // Context pointer register.
 ALIAS_REGISTER(Register, cp, x27);
 // We use a register as a JS stack pointer to overcome the restriction on the
 // architectural SP alignment.
 // We chose x28 because it is contiguous with the other specific purpose
 // registers.
 STATIC_ASSERT(kJSSPCode == 28);
 ALIAS_REGISTER(Register, jssp, x28);
 ALIAS_REGISTER(Register, wjssp, w28);
 ALIAS_REGISTER(Register, fp, x29);
 ALIAS_REGISTER(Register, lr, x30);
 ALIAS_REGISTER(Register, xzr, x31);
 ALIAS_REGISTER(Register, wzr, w31);
 
+// Keeps the 0 double value.
+ALIAS_REGISTER(FPRegister, fp_zero, d15);
 // Crankshaft double scratch register.
-ALIAS_REGISTER(FPRegister, crankshaft_fp_scratch, d29);
-// Keeps the 0 double value.
-ALIAS_REGISTER(FPRegister, fp_zero, d30);
+ALIAS_REGISTER(FPRegister, crankshaft_fp_scratch, d30);
 // MacroAssembler double scratch register.
 ALIAS_REGISTER(FPRegister, fp_scratch, d31);
 
 #undef ALIAS_REGISTER
 
 
 Register GetAllocatableRegisterThatIsNotOneOf(Register reg1,
                                               Register reg2 = NoReg,
                                               Register reg3 = NoReg,
                                               Register reg4 = NoReg);
@@ skipping 62 matching lines @@
   CPURegister::RegisterType type() const {
     ASSERT(IsValid());
     return type_;
   }
 
   RegList list() const {
     ASSERT(IsValid());
     return list_;
   }
 
+  inline void set_list(RegList new_list) {
+    ASSERT(IsValid());
+    list_ = new_list;
+  }
+
   // Combine another CPURegList into this one. Registers that already exist in
   // this list are left unchanged. The type and size of the registers in the
   // 'other' list must match those in this list.
   void Combine(const CPURegList& other);
 
   // Remove every register in the other CPURegList from this one. Registers that
   // do not exist in this list are ignored. The type and size of the registers
   // in the 'other' list must match those in this list.
   void Remove(const CPURegList& other);
 
-  // Variants of Combine and Remove which take a single register.
+  // Variants of Combine and Remove which take CPURegisters.
   void Combine(const CPURegister& other);
-  void Remove(const CPURegister& other);
+  void Remove(const CPURegister& other1,
+              const CPURegister& other2 = NoCPUReg,
+              const CPURegister& other3 = NoCPUReg,
+              const CPURegister& other4 = NoCPUReg);
 
   // Variants of Combine and Remove which take a single register by its code;
   // the type and size of the register is inferred from this list.
   void Combine(int code);
   void Remove(int code);
 
   // Remove all callee-saved registers from the list. This can be useful when
   // preparing registers for an AAPCS64 function call, for example.
   void RemoveCalleeSaved();
 
   CPURegister PopLowestIndex();
   CPURegister PopHighestIndex();
 
   // AAPCS64 callee-saved registers.
-  static CPURegList GetCalleeSaved(unsigned size = kXRegSize);
-  static CPURegList GetCalleeSavedFP(unsigned size = kDRegSize);
+  static CPURegList GetCalleeSaved(unsigned size = kXRegSizeInBits);
+  static CPURegList GetCalleeSavedFP(unsigned size = kDRegSizeInBits);
 
   // AAPCS64 caller-saved registers. Note that this includes lr.
-  static CPURegList GetCallerSaved(unsigned size = kXRegSize);
-  static CPURegList GetCallerSavedFP(unsigned size = kDRegSize);
+  static CPURegList GetCallerSaved(unsigned size = kXRegSizeInBits);
+  static CPURegList GetCallerSavedFP(unsigned size = kDRegSizeInBits);
 
   // Registers saved as safepoints.
   static CPURegList GetSafepointSavedRegisters();
 
   bool IsEmpty() const {
     ASSERT(IsValid());
     return list_ == 0;
   }
 
-  bool IncludesAliasOf(const CPURegister& other) const {
+  bool IncludesAliasOf(const CPURegister& other1,
+                       const CPURegister& other2 = NoCPUReg,
+                       const CPURegister& other3 = NoCPUReg,
+                       const CPURegister& other4 = NoCPUReg) const {
     ASSERT(IsValid());
-    return (type_ == other.type()) && (other.Bit() & list_);
+    RegList list = 0;
+    if (!other1.IsNone() && (other1.type() == type_)) list |= other1.Bit();
+    if (!other2.IsNone() && (other2.type() == type_)) list |= other2.Bit();
+    if (!other3.IsNone() && (other3.type() == type_)) list |= other3.Bit();
+    if (!other4.IsNone() && (other4.type() == type_)) list |= other4.Bit();
+    return (list_ & list) != 0;
   }
 
   int Count() const {
     ASSERT(IsValid());
     return CountSetBits(list_, kRegListSizeInBits);
   }
 
   unsigned RegisterSizeInBits() const {
     ASSERT(IsValid());
     return size_;
@@ skipping 204 matching lines @@
 
   inline void Unreachable();
 
   // Label --------------------------------------------------------------------
   // Bind a label to the current pc. Note that labels can only be bound once,
   // and if labels are linked to other instructions, they _must_ be bound
   // before they go out of scope.
   void bind(Label* label);
 
 
-  // RelocInfo and constant pool ----------------------------------------------
+  // RelocInfo and pools ------------------------------------------------------
 
   // Record relocation information for current pc_.
   void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
 
   // Return the address in the constant pool of the code target address used by
   // the branch/call instruction at pc.
   inline static Address target_pointer_address_at(Address pc);
 
   // Read/Modify the code target address in the branch/call instruction at pc.
-  inline static Address target_address_at(Address pc);
-  inline static void set_target_address_at(Address pc, Address target);
+  inline static Address target_address_at(Address pc,
+                                          ConstantPoolArray* constant_pool);
+  inline static void set_target_address_at(Address pc,
+                                           ConstantPoolArray* constant_pool,
+                                           Address target);
+  static inline Address target_address_at(Address pc, Code* code);
+  static inline void set_target_address_at(Address pc,
+                                           Code* code,
+                                           Address target);
 
   // Return the code target address at a call site from the return address of
   // that call in the instruction stream.
   inline static Address target_address_from_return_address(Address pc);
 
   // Given the address of the beginning of a call, return the address in the
   // instruction stream that call will return from.
   inline static Address return_address_from_call_start(Address pc);
 
   // This sets the branch destination (which is in the constant pool on ARM).
   // This is for calls and branches within generated code.
   inline static void deserialization_set_special_target_at(
-      Address constant_pool_entry, Address target);
+      Address constant_pool_entry, Code* code, Address target);
 
   // All addresses in the constant pool are the same size as pointers.
   static const int kSpecialTargetSize = kPointerSize;
 
   // The sizes of the call sequences emitted by MacroAssembler::Call.
   // Wherever possible, use MacroAssembler::CallSize instead of these constants,
   // as it will choose the correct value for a given relocation mode.
   //
   // Without relocation:
   //  movz  ip0, #(target & 0x000000000000ffff)
@@ skipping 31 matching lines @@
     ASSERT(size >= 0);
     ASSERT(static_cast<uint64_t>(size) == SizeOfCodeGeneratedSince(label));
   }
 
   // Return the number of instructions generated from label to the
   // current position.
   int InstructionsGeneratedSince(const Label* label) {
     return SizeOfCodeGeneratedSince(label) / kInstructionSize;
   }
 
-  // TODO(all): Initialize these constants related with code patching.
-  // TODO(all): Set to -1 to hopefully crash if mistakenly used.
-
   // Number of instructions generated for the return sequence in
   // FullCodeGenerator::EmitReturnSequence.
   static const int kJSRetSequenceInstructions = 7;
   // Distance between start of patched return sequence and the emitted address
   // to jump to.
   static const int kPatchReturnSequenceAddressOffset =  0;
   static const int kPatchDebugBreakSlotAddressOffset =  0;
 
   // Number of instructions necessary to be able to later patch it to a call.
   // See Debug::GenerateSlot() and BreakLocationIterator::SetDebugBreakAtSlot().
@@ skipping 10 matching lines @@
 
   // Resume constant pool emission. Need to be called as many time as
   // StartBlockConstPool to have an effect.
   void EndBlockConstPool();
 
   bool is_const_pool_blocked() const;
   static bool IsConstantPoolAt(Instruction* instr);
   static int ConstantPoolSizeAt(Instruction* instr);
   // See Assembler::CheckConstPool for more info.
   void ConstantPoolMarker(uint32_t size);
+  void EmitPoolGuard();
   void ConstantPoolGuard();
 
+  // Prevent veneer pool emission until EndBlockVeneerPool is called.
+  // Call to this function can be nested but must be followed by an equal
+  // number of call to EndBlockConstpool.
+  void StartBlockVeneerPool();
+
+  // Resume constant pool emission. Need to be called as many time as
+  // StartBlockVeneerPool to have an effect.
+  void EndBlockVeneerPool();
+
+  bool is_veneer_pool_blocked() const {
+    return veneer_pool_blocked_nesting_ > 0;
+  }
+
+  // Block/resume emission of constant pools and veneer pools.
+  void StartBlockPools() {
+    StartBlockConstPool();
+    StartBlockVeneerPool();
+  }
+  void EndBlockPools() {
+    EndBlockConstPool();
+    EndBlockVeneerPool();
+  }
 
   // Debugging ----------------------------------------------------------------
   PositionsRecorder* positions_recorder() { return &positions_recorder_; }
   void RecordComment(const char* msg);
   int buffer_space() const;
 
   // Mark address of the ExitJSFrame code.
   void RecordJSReturn();
 
   // Mark address of a debug break slot.
   void RecordDebugBreakSlot();
 
   // Record the emission of a constant pool.
   //
-  // The emission of constant pool depends on the size of the code generated and
-  // the number of RelocInfo recorded.
+  // The emission of constant and veneer pools depends on the size of the code
+  // generated and the number of RelocInfo recorded.
   // The Debug mechanism needs to map code offsets between two versions of a
   // function, compiled with and without debugger support (see for example
   // Debug::PrepareForBreakPoints()).
   // Compiling functions with debugger support generates additional code
-  // (Debug::GenerateSlot()). This may affect the emission of the constant
-  // pools and cause the version of the code with debugger support to have
-  // constant pools generated in different places.
-  // Recording the position and size of emitted constant pools allows to
-  // correctly compute the offset mappings between the different versions of a
-  // function in all situations.
+  // (Debug::GenerateSlot()). This may affect the emission of the pools and
+  // cause the version of the code with debugger support to have pools generated
+  // in different places.
+  // Recording the position and size of emitted pools allows to correctly
+  // compute the offset mappings between the different versions of a function in
+  // all situations.
   //
-  // The parameter indicates the size of the constant pool (in bytes), including
+  // The parameter indicates the size of the pool (in bytes), including
   // the marker and branch over the data.
   void RecordConstPool(int size);
 
 
   // Instruction set functions ------------------------------------------------
 
   // Branch / Jump instructions.
   // For branches offsets are scaled, i.e. they in instrcutions not in bytes.
   // Branch to register.
   void br(const Register& xn);
@@ skipping 459 matching lines @@
 
   // Store integer or FP register pair, non-temporal.
   void stnp(const CPURegister& rt, const CPURegister& rt2,
             const MemOperand& dst);
 
   // Load literal to register.
   void ldr(const Register& rt, uint64_t imm);
 
   // Load literal to FP register.
   void ldr(const FPRegister& ft, double imm);
+  void ldr(const FPRegister& ft, float imm);
 
   // Move instructions. The default shift of -1 indicates that the move
   // instruction will calculate an appropriate 16-bit immediate and left shift
   // that is equal to the 64-bit immediate argument. If an explicit left shift
   // is specified (0, 16, 32 or 48), the immediate must be a 16-bit value.
   //
   // For movk, an explicit shift can be used to indicate which half word should
   // be overwritten, eg. movk(x0, 0, 0) will overwrite the least-significant
   // half word with zero, whereas movk(x0, 0, 48) will overwrite the
   // most-significant.
@@ skipping 58 matching lines @@
   };
 
   void nop(NopMarkerTypes n) {
     ASSERT((FIRST_NOP_MARKER <= n) && (n <= LAST_NOP_MARKER));
     mov(Register::XRegFromCode(n), Register::XRegFromCode(n));
   }
 
   // FP instructions.
   // Move immediate to FP register.
   void fmov(FPRegister fd, double imm);
+  void fmov(FPRegister fd, float imm);
 
   // Move FP register to register.
   void fmov(Register rd, FPRegister fn);
 
   // Move register to FP register.
   void fmov(FPRegister fd, Register rn);
 
   // Move FP register to FP register.
   void fmov(FPRegister fd, FPRegister fn);
 
@@ skipping 272 matching lines @@
 
    private:
     Assembler* assem_;
 
     DISALLOW_IMPLICIT_CONSTRUCTORS(BlockConstPoolScope);
   };
 
   // Check if is time to emit a constant pool.
   void CheckConstPool(bool force_emit, bool require_jump);
 
+
+  // Returns true if we should emit a veneer as soon as possible for a branch
+  // which can at most reach to specified pc.
+  bool ShouldEmitVeneer(int max_reachable_pc,
+                        int margin = kVeneerDistanceMargin);
+  bool ShouldEmitVeneers(int margin = kVeneerDistanceMargin) {
+    return ShouldEmitVeneer(unresolved_branches_first_limit(), margin);
+  }
+
+  // The maximum code size generated for a veneer. Currently one branch
+  // instruction. This is for code size checking purposes, and can be extended
+  // in the future for example if we decide to add nops between the veneers.
+  static const int kMaxVeneerCodeSize = 1 * kInstructionSize;
+
+  void RecordVeneerPool(int location_offset, int size);
+  // Emits veneers for branches that are approaching their maximum range.
+  // If need_protection is true, the veneers are protected by a branch jumping
+  // over the code.
+  void EmitVeneers(bool need_protection, int margin = kVeneerDistanceMargin);
+  void EmitVeneersGuard() { EmitPoolGuard(); }
+  // Checks whether veneers need to be emitted at this point.
+  void CheckVeneerPool(bool require_jump, int margin = kVeneerDistanceMargin);
+
+
+  class BlockPoolsScope {
+   public:
+    explicit BlockPoolsScope(Assembler* assem) : assem_(assem) {
+      assem_->StartBlockPools();
+    }
+    ~BlockPoolsScope() {
+      assem_->EndBlockPools();
+    }
+
+   private:
+    Assembler* assem_;
+
+    DISALLOW_IMPLICIT_CONSTRUCTORS(BlockPoolsScope);
+  };
+
   // Available for constrained code generation scopes. Prefer
   // MacroAssembler::Mov() when possible.
   inline void LoadRelocated(const CPURegister& rt, const Operand& operand);
 
  protected:
   inline const Register& AppropriateZeroRegFor(const CPURegister& reg) const;
 
   void LoadStore(const CPURegister& rt,
                  const MemOperand& addr,
                  LoadStoreOp op);
@@ skipping 165 matching lines @@
     // TODO(all): Somehow register we have some data here. Then we can
     // disassemble it correctly.
     memcpy(pc_, data, size);
     pc_ += size;
     CheckBuffer();
   }
 
   void GrowBuffer();
   void CheckBuffer();
 
-  // Pc offset of the next buffer check.
-  int next_buffer_check_;
+  // Pc offset of the next constant pool check.
+  int next_constant_pool_check_;
 
   // Constant pool generation
   // Pools are emitted in the instruction stream, preferably after unconditional
   // jumps or after returns from functions (in dead code locations).
   // If a long code sequence does not contain unconditional jumps, it is
   // necessary to emit the constant pool before the pool gets too far from the
   // location it is accessed from. In this case, we emit a jump over the emitted
   // constant pool.
   // Constants in the pool may be addresses of functions that gets relocated;
   // if so, a relocation info entry is associated to the constant pool entry.
 
   // Repeated checking whether the constant pool should be emitted is rather
   // expensive. By default we only check again once a number of instructions
   // has been generated. That also means that the sizing of the buffers is not
   // an exact science, and that we rely on some slop to not overrun buffers.
-  static const int kCheckPoolIntervalInst = 128;
-  static const int kCheckPoolInterval =
-    kCheckPoolIntervalInst * kInstructionSize;
+  static const int kCheckConstPoolIntervalInst = 128;
+  static const int kCheckConstPoolInterval =
+    kCheckConstPoolIntervalInst * kInstructionSize;
 
   // Constants in pools are accessed via pc relative addressing, which can
   // reach +/-4KB thereby defining a maximum distance between the instruction
   // and the accessed constant.
-  static const int kMaxDistToPool = 4 * KB;
-  static const int kMaxNumPendingRelocInfo = kMaxDistToPool / kInstructionSize;
+  static const int kMaxDistToConstPool = 4 * KB;
+  static const int kMaxNumPendingRelocInfo =
+    kMaxDistToConstPool / kInstructionSize;
 
 
   // Average distance beetween a constant pool and the first instruction
   // accessing the constant pool. Longer distance should result in less I-cache
   // pollution.
   // In practice the distance will be smaller since constant pool emission is
   // forced after function return and sometimes after unconditional branches.
-  static const int kAvgDistToPool = kMaxDistToPool - kCheckPoolInterval;
+  static const int kAvgDistToConstPool =
+    kMaxDistToConstPool - kCheckConstPoolInterval;
 
   // Emission of the constant pool may be blocked in some code sequences.
   int const_pool_blocked_nesting_;  // Block emission if this is not zero.
   int no_const_pool_before_;  // Block emission before this pc offset.
 
   // Keep track of the first instruction requiring a constant pool entry
   // since the previous constant pool was emitted.
   int first_const_pool_use_;
 
+  // Emission of the veneer pools may be blocked in some code sequences.
+  int veneer_pool_blocked_nesting_;  // Block emission if this is not zero.
+
   // Relocation info generation
   // Each relocation is encoded as a variable size value
   static const int kMaxRelocSize = RelocInfoWriter::kMaxSize;
   RelocInfoWriter reloc_info_writer;
 
   // Relocation info records are also used during code generation as temporary
   // containers for constants and code target addresses until they are emitted
   // to the constant pool. These pending relocation info records are temporarily
   // stored in a separate buffer until a constant pool is emitted.
   // If every instruction in a long sequence is accessing the pool, we need one
@@ skipping 47 matching lines @@
   //
   // The second member gives information about the unresolved branch. The first
   // member of the pair is the maximum offset that the branch can reach in the
   // buffer. The map is sorted according to this reachable offset, allowing to
   // easily check when veneers need to be emitted.
   // Note that the maximum reachable offset (first member of the pairs) should
   // always be positive but has the same type as the return value for
   // pc_offset() for convenience.
   std::multimap<int, FarBranchInfo> unresolved_branches_;
 
+  // We generate a veneer for a branch if we reach within this distance of the
+  // limit of the range.
+  static const int kVeneerDistanceMargin = 1 * KB;
+  // The factor of 2 is a finger in the air guess. With a default margin of
+  // 1KB, that leaves us an addional 256 instructions to avoid generating a
+  // protective branch.
+  static const int kVeneerNoProtectionFactor = 2;
+  static const int kVeneerDistanceCheckMargin =
+    kVeneerNoProtectionFactor * kVeneerDistanceMargin;
+  int unresolved_branches_first_limit() const {
+    ASSERT(!unresolved_branches_.empty());
+    return unresolved_branches_.begin()->first;
+  }
+  // This is similar to next_constant_pool_check_ and helps reduce the overhead
+  // of checking for veneer pools.
+  // It is maintained to the closest unresolved branch limit minus the maximum
+  // veneer margin (or kMaxInt if there are no unresolved branches).
+  int next_veneer_pool_check_;
+
  private:
   // If a veneer is emitted for a branch instruction, that instruction must be
   // removed from the associated label's link chain so that the assembler does
   // not later attempt (likely unsuccessfully) to patch it to branch directly to
   // the label.
   void DeleteUnresolvedBranchInfoForLabel(Label* label);
 
  private:
-  // TODO(jbramley): VIXL uses next_literal_pool_check_ and
-  // literal_pool_monitor_ to determine when to consider emitting a literal
-  // pool. V8 doesn't use them, so they should either not be here at all, or
-  // should replace or be merged with next_buffer_check_ and
-  // const_pool_blocked_nesting_.
-  Instruction* next_literal_pool_check_;
-  unsigned literal_pool_monitor_;
-
   PositionsRecorder positions_recorder_;
   friend class PositionsRecorder;
   friend class EnsureSpace;
 };
 
 class PatchingAssembler : public Assembler {
  public:
   // Create an Assembler with a buffer starting at 'start'.
   // The buffer size is
   //   size of instructions to patch + kGap
   // Where kGap is the distance from which the Assembler tries to grow the
   // buffer.
   // If more or fewer instructions than expected are generated or if some
   // relocation information takes space in the buffer, the PatchingAssembler
   // will crash trying to grow the buffer.
   PatchingAssembler(Instruction* start, unsigned count)
     : Assembler(NULL,
                 reinterpret_cast<byte*>(start),
                 count * kInstructionSize + kGap) {
-    // Block constant pool emission.
-    StartBlockConstPool();
+    StartBlockPools();
   }
 
   PatchingAssembler(byte* start, unsigned count)
     : Assembler(NULL, start, count * kInstructionSize + kGap) {
     // Block constant pool emission.
-    StartBlockConstPool();
+    StartBlockPools();
   }
 
   ~PatchingAssembler() {
     // Const pool should still be blocked.
     ASSERT(is_const_pool_blocked());
-    EndBlockConstPool();
+    EndBlockPools();
     // Verify we have generated the number of instruction we expected.
     ASSERT((pc_offset() + kGap) == buffer_size_);
     // Verify no relocation information has been emitted.
     ASSERT(num_pending_reloc_info() == 0);
     // Flush the Instruction cache.
     size_t length = buffer_size_ - kGap;
     CPU::FlushICache(buffer_, length);
   }
 };
 
 
 class EnsureSpace BASE_EMBEDDED {
  public:
   explicit EnsureSpace(Assembler* assembler) {
     assembler->CheckBuffer();
   }
 };
 
 } }  // namespace v8::internal
 
 #endif  // V8_A64_ASSEMBLER_A64_H_