Experimental parser: merge r19949

src/a64/assembler-a64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
@@ skipping 102 matching lines @@
 }
 
 
 // This function defines the list of registers which are associated with a
 // safepoint slot. Safepoint register slots are saved contiguously on the stack.
 // MacroAssembler::SafepointRegisterStackIndex handles mapping from register
 // code to index in the safepoint register slots. Any change here can affect
 // this mapping.
 CPURegList CPURegList::GetSafepointSavedRegisters() {
   CPURegList list = CPURegList::GetCalleeSaved();
-  list.Combine(CPURegList(CPURegister::kRegister, kXRegSize, kJSCallerSaved));
+  list.Combine(
+      CPURegList(CPURegister::kRegister, kXRegSizeInBits, kJSCallerSaved));
 
   // Note that unfortunately we can't use symbolic names for registers and have
   // to directly use register codes. This is because this function is used to
   // initialize some static variables and we can't rely on register variables
   // to be initialized due to static initialization order issues in C++.
 
   // Drop ip0 and ip1 (i.e. x16 and x17), as they should not be expected to be
   // preserved outside of the macro assembler.
   list.Remove(16);
   list.Remove(17);
@@ skipping 19 matching lines @@
 
 
 bool RelocInfo::IsCodedSpecially() {
   // The deserializer needs to know whether a pointer is specially coded. Being
   // specially coded on A64 means that it is a movz/movk sequence. We don't
   // generate those for relocatable pointers.
   return false;
 }
 
 
+bool RelocInfo::IsInConstantPool() {
+  Instruction* instr = reinterpret_cast<Instruction*>(pc_);
+  return instr->IsLdrLiteralX();
+}
+
+
 void RelocInfo::PatchCode(byte* instructions, int instruction_count) {
   // Patch the code at the current address with the supplied instructions.
   Instr* pc = reinterpret_cast<Instr*>(pc_);
   Instr* instr = reinterpret_cast<Instr*>(instructions);
   for (int i = 0; i < instruction_count; i++) {
     *(pc + i) = *(instr + i);
   }
 
   // Indicate that code has changed.
   CPU::FlushICache(pc_, instruction_count * kInstructionSize);
@@ skipping 106 matching lines @@
 
 
 // Assembler
 
 Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size)
     : AssemblerBase(isolate, buffer, buffer_size),
       recorded_ast_id_(TypeFeedbackId::None()),
       unresolved_branches_(),
       positions_recorder_(this) {
   const_pool_blocked_nesting_ = 0;
+  veneer_pool_blocked_nesting_ = 0;
   Reset();
 }
 
 
 Assembler::~Assembler() {
   ASSERT(num_pending_reloc_info_ == 0);
   ASSERT(const_pool_blocked_nesting_ == 0);
+  ASSERT(veneer_pool_blocked_nesting_ == 0);
 }
 
 
 void Assembler::Reset() {
 #ifdef DEBUG
   ASSERT((pc_ >= buffer_) && (pc_ < buffer_ + buffer_size_));
   ASSERT(const_pool_blocked_nesting_ == 0);
+  ASSERT(veneer_pool_blocked_nesting_ == 0);
+  ASSERT(unresolved_branches_.empty());
   memset(buffer_, 0, pc_ - buffer_);
 #endif
   pc_ = buffer_;
   reloc_info_writer.Reposition(reinterpret_cast<byte*>(buffer_ + buffer_size_),
                                reinterpret_cast<byte*>(pc_));
   num_pending_reloc_info_ = 0;
-  next_buffer_check_ = 0;
+  next_constant_pool_check_ = 0;
+  next_veneer_pool_check_ = kMaxInt;
   no_const_pool_before_ = 0;
   first_const_pool_use_ = -1;
   ClearRecordedAstId();
 }
 
 
 void Assembler::GetCode(CodeDesc* desc) {
   // Emit constant pool if necessary.
   CheckConstPool(true, false);
   ASSERT(num_pending_reloc_info_ == 0);
@@ skipping 207 matching lines @@
     }
     // The instruction at pc is now the last link in the label's chain.
     label->link_to(pc_offset());
   }
 
   return offset;
 }
 
 
 void Assembler::DeleteUnresolvedBranchInfoForLabel(Label* label) {
+  if (unresolved_branches_.empty()) {
+    ASSERT(next_veneer_pool_check_ == kMaxInt);
+    return;
+  }
+
   // Branches to this label will be resolved when the label is bound below.
   std::multimap<int, FarBranchInfo>::iterator it_tmp, it;
   it = unresolved_branches_.begin();
   while (it != unresolved_branches_.end()) {
     it_tmp = it++;
     if (it_tmp->second.label_ == label) {
       CHECK(it_tmp->first >= pc_offset());
       unresolved_branches_.erase(it_tmp);
     }
   }
+  if (unresolved_branches_.empty()) {
+    next_veneer_pool_check_ = kMaxInt;
+  } else {
+    next_veneer_pool_check_ =
+      unresolved_branches_first_limit() - kVeneerDistanceCheckMargin;
+  }
 }
 
 
 void Assembler::StartBlockConstPool() {
   if (const_pool_blocked_nesting_++ == 0) {
     // Prevent constant pool checks happening by setting the next check to
     // the biggest possible offset.
-    next_buffer_check_ = kMaxInt;
+    next_constant_pool_check_ = kMaxInt;
   }
 }
 
 
 void Assembler::EndBlockConstPool() {
   if (--const_pool_blocked_nesting_ == 0) {
     // Check the constant pool hasn't been blocked for too long.
     ASSERT((num_pending_reloc_info_ == 0) ||
-           (pc_offset() < (first_const_pool_use_ + kMaxDistToPool)));
+           (pc_offset() < (first_const_pool_use_ + kMaxDistToConstPool)));
     // Two cases:
-    //  * no_const_pool_before_ >= next_buffer_check_ and the emission is
+    //  * no_const_pool_before_ >= next_constant_pool_check_ and the emission is
     //    still blocked
-    //  * no_const_pool_before_ < next_buffer_check_ and the next emit will
-    //    trigger a check.
-    next_buffer_check_ = no_const_pool_before_;
+    //  * no_const_pool_before_ < next_constant_pool_check_ and the next emit
+    //    will trigger a check.
+    next_constant_pool_check_ = no_const_pool_before_;
   }
 }
 
 
 bool Assembler::is_const_pool_blocked() const {
   return (const_pool_blocked_nesting_ > 0) ||
          (pc_offset() < no_const_pool_before_);
 }
 
 
@@ skipping 21 matching lines @@
 }
 
 
 void Assembler::ConstantPoolMarker(uint32_t size) {
   ASSERT(is_const_pool_blocked());
   // + 1 is for the crash guard.
   Emit(LDR_x_lit | ImmLLiteral(2 * size + 1) | Rt(xzr));
 }
 
 
+void Assembler::EmitPoolGuard() {
+  // We must generate only one instruction as this is used in scopes that
+  // control the size of the code generated.
+  Emit(BLR | Rn(xzr));
+}
+
+
 void Assembler::ConstantPoolGuard() {
 #ifdef DEBUG
   // Currently this is only used after a constant pool marker.
   ASSERT(is_const_pool_blocked());
   Instruction* instr = reinterpret_cast<Instruction*>(pc_);
   ASSERT(instr->preceding()->IsLdrLiteralX() &&
          instr->preceding()->Rt() == xzr.code());
 #endif
-
-  // We must generate only one instruction.
-  Emit(BLR | Rn(xzr));
+  EmitPoolGuard();
 }
 
 
+void Assembler::StartBlockVeneerPool() {
+  ++veneer_pool_blocked_nesting_;
+}
+
+
+void Assembler::EndBlockVeneerPool() {
+  if (--veneer_pool_blocked_nesting_ == 0) {
+    // Check the veneer pool hasn't been blocked for too long.
+    ASSERT(unresolved_branches_.empty() ||
+           (pc_offset() < unresolved_branches_first_limit()));
+  }
+}
+
+
 void Assembler::br(const Register& xn) {
   positions_recorder()->WriteRecordedPositions();
   ASSERT(xn.Is64Bits());
   Emit(BR | Rn(xn));
 }
 
 
 void Assembler::blr(const Register& xn) {
   positions_recorder()->WriteRecordedPositions();
   ASSERT(xn.Is64Bits());
@@ skipping 70 matching lines @@
                      Label* label) {
   positions_recorder()->WriteRecordedPositions();
   cbnz(rt, LinkAndGetInstructionOffsetTo(label));
 }
 
 
 void Assembler::tbz(const Register& rt,
                     unsigned bit_pos,
                     int imm14) {
   positions_recorder()->WriteRecordedPositions();
-  ASSERT(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSize)));
+  ASSERT(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSizeInBits)));
   Emit(TBZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt));
 }
 
 
 void Assembler::tbz(const Register& rt,
                     unsigned bit_pos,
                     Label* label) {
   positions_recorder()->WriteRecordedPositions();
   tbz(rt, bit_pos, LinkAndGetInstructionOffsetTo(label));
 }
 
 
 void Assembler::tbnz(const Register& rt,
                      unsigned bit_pos,
                      int imm14) {
   positions_recorder()->WriteRecordedPositions();
-  ASSERT(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSize)));
+  ASSERT(rt.Is64Bits() || (rt.Is32Bits() && (bit_pos < kWRegSizeInBits)));
   Emit(TBNZ | ImmTestBranchBit(bit_pos) | ImmTestBranch(imm14) | Rt(rt));
 }
 
 
 void Assembler::tbnz(const Register& rt,
                      unsigned bit_pos,
                      Label* label) {
   positions_recorder()->WriteRecordedPositions();
   tbnz(rt, bit_pos, LinkAndGetInstructionOffsetTo(label));
 }
@@ skipping 627 matching lines @@
 
 
 void Assembler::ldrsw(const Register& rt, const MemOperand& src) {
   ASSERT(rt.Is64Bits());
   LoadStore(rt, src, LDRSW_x);
 }
 
 
 void Assembler::ldr(const Register& rt, uint64_t imm) {
   // TODO(all): Constant pool may be garbage collected. Hence we cannot store
-  // TODO(all): arbitrary values in them. Manually move it for now.
-  // TODO(all): Fix MacroAssembler::Fmov when this is implemented.
+  // arbitrary values in them. Manually move it for now. Fix
+  // MacroAssembler::Fmov when this is implemented.
   UNIMPLEMENTED();
 }
 
 
 void Assembler::ldr(const FPRegister& ft, double imm) {
   // TODO(all): Constant pool may be garbage collected. Hence we cannot store
-  // TODO(all): arbitrary values in them. Manually move it for now.
-  // TODO(all): Fix MacroAssembler::Fmov when this is implemented.
+  // arbitrary values in them. Manually move it for now. Fix
+  // MacroAssembler::Fmov when this is implemented.
   UNIMPLEMENTED();
 }
 
+
+void Assembler::ldr(const FPRegister& ft, float imm) {
+  // TODO(all): Constant pool may be garbage collected. Hence we cannot store
+  // arbitrary values in them. Manually move it for now. Fix
+  // MacroAssembler::Fmov when this is implemented.
+  UNIMPLEMENTED();
+}
+
 
 void Assembler::mov(const Register& rd, const Register& rm) {
   // Moves involving the stack pointer are encoded as add immediate with
   // second operand of zero. Otherwise, orr with first operand zr is
   // used.
   if (rd.IsSP() || rm.IsSP()) {
     add(rd, rm, 0);
   } else {
     orr(rd, AppropriateZeroRegFor(rd), rm);
   }
@@ skipping 31 matching lines @@
   Emit(DSB | ImmBarrierDomain(domain) | ImmBarrierType(type));
 }
 
 
 void Assembler::isb() {
   Emit(ISB | ImmBarrierDomain(FullSystem) | ImmBarrierType(BarrierAll));
 }
 
 
 void Assembler::fmov(FPRegister fd, double imm) {
-  if (fd.Is64Bits() && IsImmFP64(imm)) {
-    Emit(FMOV_d_imm | Rd(fd) | ImmFP64(imm));
-  } else if (fd.Is32Bits() && IsImmFP32(imm)) {
-    Emit(FMOV_s_imm | Rd(fd) | ImmFP32(static_cast<float>(imm)));
-  } else if ((imm == 0.0) && (copysign(1.0, imm) == 1.0)) {
-    Register zr = AppropriateZeroRegFor(fd);
-    fmov(fd, zr);
-  } else {
-    ldr(fd, imm);
-  }
+  ASSERT(fd.Is64Bits());
+  ASSERT(IsImmFP64(imm));
+  Emit(FMOV_d_imm | Rd(fd) | ImmFP64(imm));
 }
 
 
+void Assembler::fmov(FPRegister fd, float imm) {
+  ASSERT(fd.Is32Bits());
+  ASSERT(IsImmFP32(imm));
+  Emit(FMOV_s_imm | Rd(fd) | ImmFP32(imm));
+}
+
+
 void Assembler::fmov(Register rd, FPRegister fn) {
   ASSERT(rd.SizeInBits() == fn.SizeInBits());
   FPIntegerConvertOp op = rd.Is32Bits() ? FMOV_ws : FMOV_xd;
   Emit(op | Rd(rd) | Rn(fn));
 }
 
 
 void Assembler::fmov(FPRegister fd, Register rn) {
   ASSERT(fd.SizeInBits() == rn.SizeInBits());
   FPIntegerConvertOp op = fd.Is32Bits() ? FMOV_sw : FMOV_dx;
@@ skipping 396 matching lines @@
 
 void Assembler::debug(const char* message, uint32_t code, Instr params) {
 #ifdef USE_SIMULATOR
   // Don't generate simulator specific code if we are building a snapshot, which
   // might be run on real hardware.
   if (!Serializer::enabled()) {
 #ifdef DEBUG
     Serializer::TooLateToEnableNow();
 #endif
     // The arguments to the debug marker need to be contiguous in memory, so
-    // make sure we don't try to emit a literal pool.
-    BlockConstPoolScope scope(this);
+    // make sure we don't try to emit pools.
+    BlockPoolsScope scope(this);
 
     Label start;
     bind(&start);
 
     // Refer to instructions-a64.h for a description of the marker and its
     // arguments.
     hlt(kImmExceptionIsDebug);
     ASSERT(SizeOfCodeGeneratedSince(&start) == kDebugCodeOffset);
     dc32(code);
     ASSERT(SizeOfCodeGeneratedSince(&start) == kDebugParamsOffset);
@@ skipping 157 matching lines @@
   if ((non_shift_bits > high_bit) || (non_shift_bits == 0)) {
     switch (extend) {
       case UXTB:
       case UXTH:
       case UXTW: ubfm(rd, rn_, non_shift_bits, high_bit); break;
       case SXTB:
       case SXTH:
       case SXTW: sbfm(rd, rn_, non_shift_bits, high_bit); break;
       case UXTX:
       case SXTX: {
-        ASSERT(rn.SizeInBits() == kXRegSize);
+        ASSERT(rn.SizeInBits() == kXRegSizeInBits);
         // Nothing to extend. Just shift.
         lsl(rd, rn_, left_shift);
         break;
       }
       default: UNREACHABLE();
     }
   } else {
     // No need to extend as the extended bits would be shifted away.
     lsl(rd, rn_, left_shift);
   }
@@ skipping 124 matching lines @@
 // imm_s and imm_r are updated with immediates encoded in the format required
 // by the corresponding fields in the logical instruction.
 // If it can not be encoded, the function returns false, and the values pointed
 // to by n, imm_s and imm_r are undefined.
 bool Assembler::IsImmLogical(uint64_t value,
                              unsigned width,
                              unsigned* n,
                              unsigned* imm_s,
                              unsigned* imm_r) {
   ASSERT((n != NULL) && (imm_s != NULL) && (imm_r != NULL));
-  ASSERT((width == kWRegSize) || (width == kXRegSize));
+  ASSERT((width == kWRegSizeInBits) || (width == kXRegSizeInBits));
 
   // Logical immediates are encoded using parameters n, imm_s and imm_r using
   // the following table:
   //
   //  N   imms    immr    size        S             R
   //  1  ssssss  rrrrrr    64    UInt(ssssss)  UInt(rrrrrr)
   //  0  0sssss  xrrrrr    32    UInt(sssss)   UInt(rrrrr)
   //  0  10ssss  xxrrrr    16    UInt(ssss)    UInt(rrrr)
   //  0  110sss  xxxrrr     8    UInt(sss)     UInt(rrr)
   //  0  1110ss  xxxxrr     4    UInt(ss)      UInt(rr)
   //  0  11110s  xxxxxr     2    UInt(s)       UInt(r)
   // (s bits must not be all set)
   //
   // A pattern is constructed of size bits, where the least significant S+1
   // bits are set. The pattern is rotated right by R, and repeated across a
   // 32 or 64-bit value, depending on destination register width.
   //
   // To test if an arbitary immediate can be encoded using this scheme, an
   // iterative algorithm is used.
   //
   // TODO(mcapewel) This code does not consider using X/W register overlap to
   // support 64-bit immediates where the top 32-bits are zero, and the bottom
   // 32-bits are an encodable logical immediate.
 
   // 1. If the value has all set or all clear bits, it can't be encoded.
   if ((value == 0) || (value == 0xffffffffffffffffUL) ||
-      ((width == kWRegSize) && (value == 0xffffffff))) {
+      ((width == kWRegSizeInBits) && (value == 0xffffffff))) {
     return false;
   }
 
   unsigned lead_zero = CountLeadingZeros(value, width);
   unsigned lead_one = CountLeadingZeros(~value, width);
   unsigned trail_zero = CountTrailingZeros(value, width);
   unsigned trail_one = CountTrailingZeros(~value, width);
   unsigned set_bits = CountSetBits(value, width);
 
   // The fixed bits in the immediate s field.
   // If width == 64 (X reg), start at 0xFFFFFF80.
   // If width == 32 (W reg), start at 0xFFFFFFC0, as the iteration for 64-bit
   // widths won't be executed.
-  int imm_s_fixed = (width == kXRegSize) ? -128 : -64;
+  int imm_s_fixed = (width == kXRegSizeInBits) ? -128 : -64;
   int imm_s_mask = 0x3F;
 
   for (;;) {
     // 2. If the value is two bits wide, it can be encoded.
     if (width == 2) {
       *n = 0;
       *imm_s = 0x3C;
       *imm_r = (value & 3) - 1;
       return true;
     }
@@ skipping 141 matching lines @@
     }
   }
 }
 
 
 void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
   // We do not try to reuse pool constants.
   RelocInfo rinfo(reinterpret_cast<byte*>(pc_), rmode, data, NULL);
   if (((rmode >= RelocInfo::JS_RETURN) &&
        (rmode <= RelocInfo::DEBUG_BREAK_SLOT)) ||
-      (rmode == RelocInfo::CONST_POOL)) {
+      (rmode == RelocInfo::CONST_POOL) ||
+      (rmode == RelocInfo::VENEER_POOL)) {
     // Adjust code for new modes.
     ASSERT(RelocInfo::IsDebugBreakSlot(rmode)
            || RelocInfo::IsJSReturn(rmode)
            || RelocInfo::IsComment(rmode)
            || RelocInfo::IsPosition(rmode)
-           || RelocInfo::IsConstPool(rmode));
+           || RelocInfo::IsConstPool(rmode)
+           || RelocInfo::IsVeneerPool(rmode));
     // These modes do not need an entry in the constant pool.
   } else {
     ASSERT(num_pending_reloc_info_ < kMaxNumPendingRelocInfo);
     if (num_pending_reloc_info_ == 0) {
       first_const_pool_use_ = pc_offset();
     }
     pending_reloc_info_[num_pending_reloc_info_++] = rinfo;
     // Make sure the constant pool is not emitted in place of the next
     // instruction for which we just recorded relocation info.
     BlockConstPoolFor(1);
@@ skipping 21 matching lines @@
       reloc_info_writer.Write(&rinfo);
     }
   }
 }
 
 
 void Assembler::BlockConstPoolFor(int instructions) {
   int pc_limit = pc_offset() + instructions * kInstructionSize;
   if (no_const_pool_before_ < pc_limit) {
     // If there are some pending entries, the constant pool cannot be blocked
-    // further than first_const_pool_use_ + kMaxDistToPool
+    // further than first_const_pool_use_ + kMaxDistToConstPool
     ASSERT((num_pending_reloc_info_ == 0) ||
-           (pc_limit < (first_const_pool_use_ + kMaxDistToPool)));
+           (pc_limit < (first_const_pool_use_ + kMaxDistToConstPool)));
     no_const_pool_before_ = pc_limit;
   }
 
-  if (next_buffer_check_ < no_const_pool_before_) {
-    next_buffer_check_ = no_const_pool_before_;
+  if (next_constant_pool_check_ < no_const_pool_before_) {
+    next_constant_pool_check_ = no_const_pool_before_;
   }
 }
 
 
 void Assembler::CheckConstPool(bool force_emit, bool require_jump) {
   // Some short sequence of instruction mustn't be broken up by constant pool
   // emission, such sequences are protected by calls to BlockConstPoolFor and
   // BlockConstPoolScope.
   if (is_const_pool_blocked()) {
     // Something is wrong if emission is forced and blocked at the same time.
     ASSERT(!force_emit);
     return;
   }
 
   // There is nothing to do if there are no pending constant pool entries.
   if (num_pending_reloc_info_ == 0)  {
     // Calculate the offset of the next check.
-    next_buffer_check_ = pc_offset() + kCheckPoolInterval;
+    next_constant_pool_check_ = pc_offset() + kCheckConstPoolInterval;
     return;
   }
 
   // We emit a constant pool when:
   //  * requested to do so by parameter force_emit (e.g. after each function).
   //  * the distance to the first instruction accessing the constant pool is
-  //    kAvgDistToPool or more.
+  //    kAvgDistToConstPool or more.
   //  * no jump is required and the distance to the first instruction accessing
-  //    the constant pool is at least kMaxDistToPool / 2.
+  //    the constant pool is at least kMaxDistToPConstool / 2.
   ASSERT(first_const_pool_use_ >= 0);
   int dist = pc_offset() - first_const_pool_use_;
-  if (!force_emit && dist < kAvgDistToPool &&
-      (require_jump || (dist < (kMaxDistToPool / 2)))) {
+  if (!force_emit && dist < kAvgDistToConstPool &&
+      (require_jump || (dist < (kMaxDistToConstPool / 2)))) {
     return;
   }
 
+  int jump_instr = require_jump ? kInstructionSize : 0;
+  int size_pool_marker = kInstructionSize;
+  int size_pool_guard = kInstructionSize;
+  int pool_size = jump_instr + size_pool_marker + size_pool_guard +
+    num_pending_reloc_info_ * kPointerSize;
+  int needed_space = pool_size + kGap;
+
+  // Emit veneers for branches that would go out of range during emission of the
+  // constant pool.
+  CheckVeneerPool(require_jump, kVeneerDistanceMargin + pool_size);
+
   Label size_check;
   bind(&size_check);
 
   // Check that the code buffer is large enough before emitting the constant
   // pool (include the jump over the pool, the constant pool marker, the
   // constant pool guard, and the gap to the relocation information).
-  int jump_instr = require_jump ? kInstructionSize : 0;
-  int size_pool_marker = kInstructionSize;
-  int size_pool_guard = kInstructionSize;
-  int pool_size = jump_instr + size_pool_marker + size_pool_guard +
-    num_pending_reloc_info_ * kPointerSize;
-  int needed_space = pool_size + kGap;
   while (buffer_space() <= needed_space) {
     GrowBuffer();
   }
 
   {
-    // Block recursive calls to CheckConstPool.
-    BlockConstPoolScope block_const_pool(this);
+    // Block recursive calls to CheckConstPool and protect from veneer pools.
+    BlockPoolsScope block_pools(this);
     RecordComment("[ Constant Pool");
     RecordConstPool(pool_size);
 
     // Emit jump over constant pool if necessary.
     Label after_pool;
     if (require_jump) {
       b(&after_pool);
     }
 
     // Emit a constant pool header. The header has two goals:
     //  1) Encode the size of the constant pool, for use by the disassembler.
     //  2) Terminate the program, to try to prevent execution from accidentally
     //     flowing into the constant pool.
     // The header is therefore made of two a64 instructions:
     //   ldr xzr, #<size of the constant pool in 32-bit words>
     //   blr xzr
     // If executed the code will likely segfault and lr will point to the
     // beginning of the constant pool.
     // TODO(all): currently each relocated constant is 64 bits, consider adding
     // support for 32-bit entries.
     ConstantPoolMarker(2 * num_pending_reloc_info_);
     ConstantPoolGuard();
 
     // Emit constant pool entries.
     for (int i = 0; i < num_pending_reloc_info_; i++) {
       RelocInfo& rinfo = pending_reloc_info_[i];
       ASSERT(rinfo.rmode() != RelocInfo::COMMENT &&
              rinfo.rmode() != RelocInfo::POSITION &&
              rinfo.rmode() != RelocInfo::STATEMENT_POSITION &&
-             rinfo.rmode() != RelocInfo::CONST_POOL);
+             rinfo.rmode() != RelocInfo::CONST_POOL &&
+             rinfo.rmode() != RelocInfo::VENEER_POOL);
 
       Instruction* instr = reinterpret_cast<Instruction*>(rinfo.pc());
       // Instruction to patch must be 'ldr rd, [pc, #offset]' with offset == 0.
       ASSERT(instr->IsLdrLiteral() &&
              instr->ImmLLiteral() == 0);
 
       instr->SetImmPCOffsetTarget(reinterpret_cast<Instruction*>(pc_));
       dc64(rinfo.data());
     }
 
     num_pending_reloc_info_ = 0;
     first_const_pool_use_ = -1;
 
     RecordComment("]");
 
     if (after_pool.is_linked()) {
       bind(&after_pool);
     }
   }
 
   // Since a constant pool was just emitted, move the check offset forward by
   // the standard interval.
-  next_buffer_check_ = pc_offset() + kCheckPoolInterval;
+  next_constant_pool_check_ = pc_offset() + kCheckConstPoolInterval;
 
   ASSERT(SizeOfCodeGeneratedSince(&size_check) ==
          static_cast<unsigned>(pool_size));
 }
 
 
+bool Assembler::ShouldEmitVeneer(int max_reachable_pc, int margin) {
+  // Account for the branch around the veneers and the guard.
+  int protection_offset = 2 * kInstructionSize;
+  return pc_offset() > max_reachable_pc - margin - protection_offset -
+    static_cast<int>(unresolved_branches_.size() * kMaxVeneerCodeSize);
+}
+
+
+void Assembler::RecordVeneerPool(int location_offset, int size) {
+#ifdef ENABLE_DEBUGGER_SUPPORT
+  RelocInfo rinfo(buffer_ + location_offset,
+                  RelocInfo::VENEER_POOL, static_cast<intptr_t>(size),
+                  NULL);
+  reloc_info_writer.Write(&rinfo);
+#endif
+}
+
+
+void Assembler::EmitVeneers(bool need_protection, int margin) {
+  BlockPoolsScope scope(this);
+  RecordComment("[ Veneers");
+
+  // The exact size of the veneer pool must be recorded (see the comment at the
+  // declaration site of RecordConstPool()), but computing the number of
+  // veneers that will be generated is not obvious. So instead we remember the
+  // current position and will record the size after the pool has been
+  // generated.
+  Label size_check;
+  bind(&size_check);
+  int veneer_pool_relocinfo_loc = pc_offset();
+
+  Label end;
+  if (need_protection) {
+    b(&end);
+  }
+
+  EmitVeneersGuard();
+
+  Label veneer_size_check;
+
+  std::multimap<int, FarBranchInfo>::iterator it, it_to_delete;
+
+  it = unresolved_branches_.begin();
+  while (it != unresolved_branches_.end()) {
+    if (ShouldEmitVeneer(it->first, margin)) {
+      Instruction* branch = InstructionAt(it->second.pc_offset_);
+      Label* label = it->second.label_;
+
+#ifdef DEBUG
+      bind(&veneer_size_check);
+#endif
+      // Patch the branch to point to the current position, and emit a branch
+      // to the label.
+      Instruction* veneer = reinterpret_cast<Instruction*>(pc_);
+      RemoveBranchFromLabelLinkChain(branch, label, veneer);
+      branch->SetImmPCOffsetTarget(veneer);
+      b(label);
+#ifdef DEBUG
+      ASSERT(SizeOfCodeGeneratedSince(&veneer_size_check) <=
+             static_cast<uint64_t>(kMaxVeneerCodeSize));
+      veneer_size_check.Unuse();
+#endif
+
+      it_to_delete = it++;
+      unresolved_branches_.erase(it_to_delete);
+    } else {
+      ++it;
+    }
+  }
+
+  // Record the veneer pool size.
+  int pool_size = SizeOfCodeGeneratedSince(&size_check);
+  RecordVeneerPool(veneer_pool_relocinfo_loc, pool_size);
+
+  if (unresolved_branches_.empty()) {
+    next_veneer_pool_check_ = kMaxInt;
+  } else {
+    next_veneer_pool_check_ =
+      unresolved_branches_first_limit() - kVeneerDistanceCheckMargin;
+  }
+
+  bind(&end);
+
+  RecordComment("]");
+}
+
+
+void Assembler::CheckVeneerPool(bool require_jump,
+                                int margin) {
+  // There is nothing to do if there are no pending veneer pool entries.
+  if (unresolved_branches_.empty())  {
+    ASSERT(next_veneer_pool_check_ == kMaxInt);
+    return;
+  }
+
+  ASSERT(pc_offset() < unresolved_branches_first_limit());
+
+  // Some short sequence of instruction mustn't be broken up by veneer pool
+  // emission, such sequences are protected by calls to BlockVeneerPoolFor and
+  // BlockVeneerPoolScope.
+  if (is_veneer_pool_blocked()) {
+    return;
+  }
+
+  if (!require_jump) {
+    // Prefer emitting veneers protected by an existing instruction.
+    margin *= kVeneerNoProtectionFactor;
+  }
+  if (ShouldEmitVeneers(margin)) {
+    EmitVeneers(require_jump, margin);
+  } else {
+    next_veneer_pool_check_ =
+      unresolved_branches_first_limit() - kVeneerDistanceCheckMargin;
+  }
+}
+
+
 void Assembler::RecordComment(const char* msg) {
   if (FLAG_code_comments) {
     CheckBuffer();
     RecordRelocInfo(RelocInfo::COMMENT, reinterpret_cast<intptr_t>(msg));
   }
 }
 
 
 int Assembler::buffer_space() const {
   return reloc_info_writer.pos() - reinterpret_cast<byte*>(pc_);
@@ skipping 19 matching lines @@
   // code.
 #ifdef ENABLE_DEBUGGER_SUPPORT
   RecordRelocInfo(RelocInfo::CONST_POOL, static_cast<intptr_t>(size));
 #endif
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_A64