Experimental parser: merge r19949

src/a64/assembler-a64-inl.h

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 26 matching lines @@
 namespace internal {
 
 
 void RelocInfo::apply(intptr_t delta) {
   UNIMPLEMENTED();
 }
 
 
 void RelocInfo::set_target_address(Address target, WriteBarrierMode mode) {
   ASSERT(IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_));
-  Assembler::set_target_address_at(pc_, target);
+  Assembler::set_target_address_at(pc_, host_, target);
   if (mode == UPDATE_WRITE_BARRIER && host() != NULL && IsCodeTarget(rmode_)) {
     Object* target_code = Code::GetCodeFromTargetAddress(target);
     host()->GetHeap()->incremental_marking()->RecordWriteIntoCode(
         host(), this, HeapObject::cast(target_code));
   }
 }
 
 
 inline unsigned CPURegister::code() const {
   ASSERT(IsValid());
@@ skipping 44 matching lines @@
     return true;
   } else {
     ASSERT(IsNone());
     return false;
   }
 }
 
 
 inline bool CPURegister::IsValidRegister() const {
   return IsRegister() &&
-         ((reg_size == kWRegSize) || (reg_size == kXRegSize)) &&
+         ((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits)) &&
          ((reg_code < kNumberOfRegisters) || (reg_code == kSPRegInternalCode));
 }
 
 
 inline bool CPURegister::IsValidFPRegister() const {
   return IsFPRegister() &&
-         ((reg_size == kSRegSize) || (reg_size == kDRegSize)) &&
+         ((reg_size == kSRegSizeInBits) || (reg_size == kDRegSizeInBits)) &&
          (reg_code < kNumberOfFPRegisters);
 }
 
 
 inline bool CPURegister::IsNone() const {
   // kNoRegister types should always have size 0 and code 0.
   ASSERT((reg_type != kNoRegister) || (reg_code == 0));
   ASSERT((reg_type != kNoRegister) || (reg_size == 0));
 
   return reg_type == kNoRegister;
@@ skipping 42 matching lines @@
 inline void CPURegList::Combine(const CPURegList& other) {
   ASSERT(IsValid());
   ASSERT(other.type() == type_);
   ASSERT(other.RegisterSizeInBits() == size_);
   list_ |= other.list();
 }
 
 
 inline void CPURegList::Remove(const CPURegList& other) {
   ASSERT(IsValid());
-  ASSERT(other.type() == type_);
-  ASSERT(other.RegisterSizeInBits() == size_);
-  list_ &= ~other.list();
+  if (other.type() == type_) {
+    list_ &= ~other.list();
+  }
 }
 
 
 inline void CPURegList::Combine(const CPURegister& other) {
   ASSERT(other.type() == type_);
   ASSERT(other.SizeInBits() == size_);
   Combine(other.code());
 }
 
 
-inline void CPURegList::Remove(const CPURegister& other) {
-  ASSERT(other.type() == type_);
-  ASSERT(other.SizeInBits() == size_);
-  Remove(other.code());
+inline void CPURegList::Remove(const CPURegister& other1,
+                               const CPURegister& other2,
+                               const CPURegister& other3,
+                               const CPURegister& other4) {
+  if (!other1.IsNone() && (other1.type() == type_)) Remove(other1.code());
+  if (!other2.IsNone() && (other2.type() == type_)) Remove(other2.code());
+  if (!other3.IsNone() && (other3.type() == type_)) Remove(other3.code());
+  if (!other4.IsNone() && (other4.type() == type_)) Remove(other4.code());
 }
 
 
 inline void CPURegList::Combine(int code) {
   ASSERT(IsValid());
   ASSERT(CPURegister::Create(code, size_, type_).IsValid());
   list_ |= (1UL << code);
 }
 
 
 inline void CPURegList::Remove(int code) {
   ASSERT(IsValid());
   ASSERT(CPURegister::Create(code, size_, type_).IsValid());
   list_ &= ~(1UL << code);
 }
 
 
 inline Register Register::XRegFromCode(unsigned code) {
   // This function returns the zero register when code = 31. The stack pointer
   // can not be returned.
   ASSERT(code < kNumberOfRegisters);
-  return Register::Create(code, kXRegSize);
+  return Register::Create(code, kXRegSizeInBits);
 }
 
 
 inline Register Register::WRegFromCode(unsigned code) {
   ASSERT(code < kNumberOfRegisters);
-  return Register::Create(code, kWRegSize);
+  return Register::Create(code, kWRegSizeInBits);
 }
 
 
 inline FPRegister FPRegister::SRegFromCode(unsigned code) {
   ASSERT(code < kNumberOfFPRegisters);
-  return FPRegister::Create(code, kSRegSize);
+  return FPRegister::Create(code, kSRegSizeInBits);
 }
 
 
 inline FPRegister FPRegister::DRegFromCode(unsigned code) {
   ASSERT(code < kNumberOfFPRegisters);
-  return FPRegister::Create(code, kDRegSize);
+  return FPRegister::Create(code, kDRegSizeInBits);
 }
 
 
 inline Register CPURegister::W() const {
   ASSERT(IsValidRegister());
   return Register::WRegFromCode(reg_code);
 }
 
 
 inline Register CPURegister::X() const {
@@ skipping 74 matching lines @@
   STATIC_ASSERT(OperandInitializer<T>::kIsIntType);
 }
 
 
 Operand::Operand(Register reg, Shift shift, unsigned shift_amount)
     : reg_(reg),
       shift_(shift),
       extend_(NO_EXTEND),
       shift_amount_(shift_amount),
       rmode_(reg.Is64Bits() ? RelocInfo::NONE64 : RelocInfo::NONE32) {
-  ASSERT(reg.Is64Bits() || (shift_amount < kWRegSize));
-  ASSERT(reg.Is32Bits() || (shift_amount < kXRegSize));
+  ASSERT(reg.Is64Bits() || (shift_amount < kWRegSizeInBits));
+  ASSERT(reg.Is32Bits() || (shift_amount < kXRegSizeInBits));
   ASSERT(!reg.IsSP());
 }
 
 
 Operand::Operand(Register reg, Extend extend, unsigned shift_amount)
     : reg_(reg),
       shift_(NO_SHIFT),
       extend_(extend),
       shift_amount_(shift_amount),
       rmode_(reg.Is64Bits() ? RelocInfo::NONE64 : RelocInfo::NONE32) {
@@ skipping 202 matching lines @@
 
 
 Address Assembler::target_pointer_address_at(Address pc) {
   Instruction* instr = reinterpret_cast<Instruction*>(pc);
   ASSERT(instr->IsLdrLiteralX());
   return reinterpret_cast<Address>(instr->ImmPCOffsetTarget());
 }
 
 
 // Read/Modify the code target address in the branch/call instruction at pc.
-Address Assembler::target_address_at(Address pc) {
+Address Assembler::target_address_at(Address pc,
+                                     ConstantPoolArray* constant_pool) {
   return Memory::Address_at(target_pointer_address_at(pc));
 }
 
 
+Address Assembler::target_address_at(Address pc, Code* code) {
+  ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
+  return target_address_at(pc, constant_pool);
+}
+
+
 Address Assembler::target_address_from_return_address(Address pc) {
   // Returns the address of the call target from the return address that will
   // be returned to after a call.
   // Call sequence on A64 is:
   //  ldr ip0, #... @ load from literal pool
   //  blr ip0
   Address candidate = pc - 2 * kInstructionSize;
   Instruction* instr = reinterpret_cast<Instruction*>(candidate);
   USE(instr);
   ASSERT(instr->IsLdrLiteralX());
@@ skipping 33 matching lines @@
   } else {
     // Verify the instruction sequence.
     ASSERT(instr->IsLdrLiteralX());
     ASSERT(instr->following(1)->IsBranchAndLinkToRegister());
     return pc + Assembler::kCallSizeWithRelocation;
   }
 }
 
 
 void Assembler::deserialization_set_special_target_at(
-    Address constant_pool_entry, Address target) {
+    Address constant_pool_entry, Code* code, Address target) {
   Memory::Address_at(constant_pool_entry) = target;
 }
 
 
-void Assembler::set_target_address_at(Address pc, Address target) {
+void Assembler::set_target_address_at(Address pc,
+                                      ConstantPoolArray* constant_pool,
+                                      Address target) {
   Memory::Address_at(target_pointer_address_at(pc)) = target;
   // Intuitively, we would think it is necessary to always flush the
   // instruction cache after patching a target address in the code as follows:
   //   CPU::FlushICache(pc, sizeof(target));
   // However, on ARM, an instruction is actually patched in the case of
   // embedded constants of the form:
   // ldr   ip, [pc, #...]
   // since the instruction accessing this address in the constant pool remains
   // unchanged, a flush is not required.
 }
 
 
+void Assembler::set_target_address_at(Address pc,
+                                      Code* code,
+                                      Address target) {
+  ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
+  set_target_address_at(pc, constant_pool, target);
+}
+
+
 int RelocInfo::target_address_size() {
   return kPointerSize;
 }
 
 
 Address RelocInfo::target_address() {
   ASSERT(IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_));
-  return Assembler::target_address_at(pc_);
+  return Assembler::target_address_at(pc_, host_);
 }
 
 
 Address RelocInfo::target_address_address() {
   ASSERT(IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_)
                               || rmode_ == EMBEDDED_OBJECT
                               || rmode_ == EXTERNAL_REFERENCE);
   return Assembler::target_pointer_address_at(pc_);
 }
 
 
+Address RelocInfo::constant_pool_entry_address() {
+  ASSERT(IsInConstantPool());
+  return Assembler::target_pointer_address_at(pc_);
+}
+
+
 Object* RelocInfo::target_object() {
   ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
-  return reinterpret_cast<Object*>(Assembler::target_address_at(pc_));
+  return reinterpret_cast<Object*>(Assembler::target_address_at(pc_, host_));
 }
 
 
 Handle<Object> RelocInfo::target_object_handle(Assembler* origin) {
   ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
   return Handle<Object>(reinterpret_cast<Object**>(
-      Assembler::target_address_at(pc_)));
+      Assembler::target_address_at(pc_, host_)));
 }
 
 
 void RelocInfo::set_target_object(Object* target, WriteBarrierMode mode) {
   ASSERT(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT);
   ASSERT(!target->IsConsString());
-  Assembler::set_target_address_at(pc_, reinterpret_cast<Address>(target));
+  Assembler::set_target_address_at(pc_, host_,
+                                   reinterpret_cast<Address>(target));
   if (mode == UPDATE_WRITE_BARRIER &&
       host() != NULL &&
       target->IsHeapObject()) {
     host()->GetHeap()->incremental_marking()->RecordWrite(
         host(), &Memory::Object_at(pc_), HeapObject::cast(target));
   }
 }
 
 
 Address RelocInfo::target_reference() {
   ASSERT(rmode_ == EXTERNAL_REFERENCE);
-  return Assembler::target_address_at(pc_);
+  return Assembler::target_address_at(pc_, host_);
 }
 
 
 Address RelocInfo::target_runtime_entry(Assembler* origin) {
   ASSERT(IsRuntimeEntry(rmode_));
   return target_address();
 }
 
 
 void RelocInfo::set_target_runtime_entry(Address target,
@@ skipping 48 matching lines @@
   Address stub_entry_address = pc_ + kCodeAgeStubEntryOffset;
   Memory::Address_at(stub_entry_address) = stub->instruction_start();
 }
 
 
 Address RelocInfo::call_address() {
   ASSERT((IsJSReturn(rmode()) && IsPatchedReturnSequence()) ||
          (IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence()));
   // For the above sequences the Relocinfo points to the load literal loading
   // the call address.
-  return Assembler::target_address_at(pc_);
+  return Assembler::target_address_at(pc_, host_);
 }
 
 
 void RelocInfo::set_call_address(Address target) {
   ASSERT((IsJSReturn(rmode()) && IsPatchedReturnSequence()) ||
          (IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence()));
-  Assembler::set_target_address_at(pc_, target);
+  Assembler::set_target_address_at(pc_, host_, target);
   if (host() != NULL) {
     Object* target_code = Code::GetCodeFromTargetAddress(target);
     host()->GetHeap()->incremental_marking()->RecordWriteIntoCode(
         host(), this, HeapObject::cast(target_code));
   }
 }
 
 
 void RelocInfo::WipeOut() {
   ASSERT(IsEmbeddedObject(rmode_) ||
          IsCodeTarget(rmode_) ||
          IsRuntimeEntry(rmode_) ||
          IsExternalReference(rmode_));
-  Assembler::set_target_address_at(pc_, NULL);
+  Assembler::set_target_address_at(pc_, host_, NULL);
 }
 
 
 bool RelocInfo::IsPatchedReturnSequence() {
   // The sequence must be:
   //   ldr ip0, [pc, #offset]
   //   blr ip0
   // See a64/debug-a64.cc BreakLocationIterator::SetDebugBreakAtReturn().
   Instruction* i1 = reinterpret_cast<Instruction*>(pc_);
   Instruction* i2 = i1->following();
@@ skipping 208 matching lines @@
   ASSERT(IsImmAddSub(imm));
   if (is_uint12(imm)) {  // No shift required.
     return imm << ImmAddSub_offset;
   } else {
     return ((imm >> 12) << ImmAddSub_offset) | (1 << ShiftAddSub_offset);
   }
 }
 
 
 Instr Assembler::ImmS(unsigned imms, unsigned reg_size) {
-  ASSERT(((reg_size == kXRegSize) && is_uint6(imms)) ||
-         ((reg_size == kWRegSize) && is_uint5(imms)));
+  ASSERT(((reg_size == kXRegSizeInBits) && is_uint6(imms)) ||
+         ((reg_size == kWRegSizeInBits) && is_uint5(imms)));
   USE(reg_size);
   return imms << ImmS_offset;
 }
 
 
 Instr Assembler::ImmR(unsigned immr, unsigned reg_size) {
-  ASSERT(((reg_size == kXRegSize) && is_uint6(immr)) ||
-         ((reg_size == kWRegSize) && is_uint5(immr)));
+  ASSERT(((reg_size == kXRegSizeInBits) && is_uint6(immr)) ||
+         ((reg_size == kWRegSizeInBits) && is_uint5(immr)));
   USE(reg_size);
   ASSERT(is_uint6(immr));
   return immr << ImmR_offset;
 }
 
 
 Instr Assembler::ImmSetBits(unsigned imms, unsigned reg_size) {
-  ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize));
+  ASSERT((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits));
   ASSERT(is_uint6(imms));
-  ASSERT((reg_size == kXRegSize) || is_uint6(imms + 3));
+  ASSERT((reg_size == kXRegSizeInBits) || is_uint6(imms + 3));
   USE(reg_size);
   return imms << ImmSetBits_offset;
 }
 
 
 Instr Assembler::ImmRotate(unsigned immr, unsigned reg_size) {
-  ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize));
-  ASSERT(((reg_size == kXRegSize) && is_uint6(immr)) ||
-         ((reg_size == kWRegSize) && is_uint5(immr)));
+  ASSERT((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits));
+  ASSERT(((reg_size == kXRegSizeInBits) && is_uint6(immr)) ||
+         ((reg_size == kWRegSizeInBits) && is_uint5(immr)));
   USE(reg_size);
   return immr << ImmRotate_offset;
 }
 
 
 Instr Assembler::ImmLLiteral(int imm19) {
   CHECK(is_int19(imm19));
   return truncate_to_int19(imm19) << ImmLLiteral_offset;
 }
 
 
 Instr Assembler::BitN(unsigned bitn, unsigned reg_size) {
-  ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize));
-  ASSERT((reg_size == kXRegSize) || (bitn == 0));
+  ASSERT((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits));
+  ASSERT((reg_size == kXRegSizeInBits) || (bitn == 0));
   USE(reg_size);
   return bitn << BitN_offset;
 }
 
 
 Instr Assembler::ShiftDP(Shift shift) {
   ASSERT(shift == LSL || shift == LSR || shift == ASR || shift == ROR);
   return shift << ShiftDP_offset;
 }
 
@@ skipping 119 matching lines @@
 void Assembler::LoadRelocated(const CPURegister& rt, const Operand& operand) {
   LoadRelocatedValue(rt, operand, LDR_x_lit);
 }
 
 
 inline void Assembler::CheckBuffer() {
   ASSERT(pc_ < (buffer_ + buffer_size_));
   if (buffer_space() < kGap) {
     GrowBuffer();
   }
-  if (pc_offset() >= next_buffer_check_) {
+  if (pc_offset() >= next_veneer_pool_check_) {
+    CheckVeneerPool(true);
+  }
+  if (pc_offset() >= next_constant_pool_check_) {
     CheckConstPool(false, true);
   }
 }
 
 
 TypeFeedbackId Assembler::RecordedAstId() {
   ASSERT(!recorded_ast_id_.IsNone());
   return recorded_ast_id_;
 }
 
 
 void Assembler::ClearRecordedAstId() {
   recorded_ast_id_ = TypeFeedbackId::None();
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_A64_ASSEMBLER_A64_INL_H_