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Side by Side Diff: src/compiler/mips/code-generator-mips.cc

Issue 1959763002: [turbofan] Rename floating point register / slot methods. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Unfix arm64. Created 4 years, 7 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/ast/scopes.h" 5 #include "src/ast/scopes.h"
6 #include "src/compiler/code-generator.h" 6 #include "src/compiler/code-generator.h"
7 #include "src/compiler/code-generator-impl.h" 7 #include "src/compiler/code-generator-impl.h"
8 #include "src/compiler/gap-resolver.h" 8 #include "src/compiler/gap-resolver.h"
9 #include "src/compiler/node-matchers.h" 9 #include "src/compiler/node-matchers.h"
10 #include "src/compiler/osr.h" 10 #include "src/compiler/osr.h"
(...skipping 101 matching lines...) Expand 10 before | Expand all | Expand 10 after
112 UNREACHABLE(); 112 UNREACHABLE();
113 } 113 }
114 UNREACHABLE(); 114 UNREACHABLE();
115 return MemOperand(no_reg); 115 return MemOperand(no_reg);
116 } 116 }
117 117
118 MemOperand MemoryOperand(size_t index = 0) { return MemoryOperand(&index); } 118 MemOperand MemoryOperand(size_t index = 0) { return MemoryOperand(&index); }
119 119
120 MemOperand ToMemOperand(InstructionOperand* op) const { 120 MemOperand ToMemOperand(InstructionOperand* op) const {
121 DCHECK_NOT_NULL(op); 121 DCHECK_NOT_NULL(op);
122 DCHECK(op->IsStackSlot() || op->IsDoubleStackSlot()); 122 DCHECK(op->IsStackSlot() || op->IsFPStackSlot());
123 return SlotToMemOperand(AllocatedOperand::cast(op)->index()); 123 return SlotToMemOperand(AllocatedOperand::cast(op)->index());
124 } 124 }
125 125
126 MemOperand SlotToMemOperand(int slot) const { 126 MemOperand SlotToMemOperand(int slot) const {
127 FrameOffset offset = frame_access_state()->GetFrameOffset(slot); 127 FrameOffset offset = frame_access_state()->GetFrameOffset(slot);
128 return MemOperand(offset.from_stack_pointer() ? sp : fp, offset.offset()); 128 return MemOperand(offset.from_stack_pointer() ? sp : fp, offset.offset());
129 } 129 }
130 }; 130 };
131 131
132 132
(...skipping 1136 matching lines...) Expand 10 before | Expand all | Expand 10 after
1269 __ swc1(i.InputSingleRegister(index), operand); 1269 __ swc1(i.InputSingleRegister(index), operand);
1270 break; 1270 break;
1271 } 1271 }
1272 case kMipsLdc1: 1272 case kMipsLdc1:
1273 __ ldc1(i.OutputDoubleRegister(), i.MemoryOperand()); 1273 __ ldc1(i.OutputDoubleRegister(), i.MemoryOperand());
1274 break; 1274 break;
1275 case kMipsSdc1: 1275 case kMipsSdc1:
1276 __ sdc1(i.InputDoubleRegister(2), i.MemoryOperand()); 1276 __ sdc1(i.InputDoubleRegister(2), i.MemoryOperand());
1277 break; 1277 break;
1278 case kMipsPush: 1278 case kMipsPush:
1279 if (instr->InputAt(0)->IsDoubleRegister()) { 1279 if (instr->InputAt(0)->IsFPRegister()) {
1280 __ sdc1(i.InputDoubleRegister(0), MemOperand(sp, -kDoubleSize)); 1280 __ sdc1(i.InputDoubleRegister(0), MemOperand(sp, -kDoubleSize));
1281 __ Subu(sp, sp, Operand(kDoubleSize)); 1281 __ Subu(sp, sp, Operand(kDoubleSize));
1282 frame_access_state()->IncreaseSPDelta(kDoubleSize / kPointerSize); 1282 frame_access_state()->IncreaseSPDelta(kDoubleSize / kPointerSize);
1283 } else { 1283 } else {
1284 __ Push(i.InputRegister(0)); 1284 __ Push(i.InputRegister(0));
1285 frame_access_state()->IncreaseSPDelta(1); 1285 frame_access_state()->IncreaseSPDelta(1);
1286 } 1286 }
1287 break; 1287 break;
1288 case kMipsStackClaim: { 1288 case kMipsStackClaim: {
1289 __ Subu(sp, sp, Operand(i.InputInt32(0))); 1289 __ Subu(sp, sp, Operand(i.InputInt32(0)));
1290 frame_access_state()->IncreaseSPDelta(i.InputInt32(0) / kPointerSize); 1290 frame_access_state()->IncreaseSPDelta(i.InputInt32(0) / kPointerSize);
1291 break; 1291 break;
1292 } 1292 }
1293 case kMipsStoreToStackSlot: { 1293 case kMipsStoreToStackSlot: {
1294 if (instr->InputAt(0)->IsDoubleRegister()) { 1294 if (instr->InputAt(0)->IsFPRegister()) {
1295 __ sdc1(i.InputDoubleRegister(0), MemOperand(sp, i.InputInt32(1))); 1295 __ sdc1(i.InputDoubleRegister(0), MemOperand(sp, i.InputInt32(1)));
1296 } else { 1296 } else {
1297 __ sw(i.InputRegister(0), MemOperand(sp, i.InputInt32(1))); 1297 __ sw(i.InputRegister(0), MemOperand(sp, i.InputInt32(1)));
1298 } 1298 }
1299 break; 1299 break;
1300 } 1300 }
1301 case kCheckedLoadInt8: 1301 case kCheckedLoadInt8:
1302 ASSEMBLE_CHECKED_LOAD_INTEGER(lb); 1302 ASSEMBLE_CHECKED_LOAD_INTEGER(lb);
1303 break; 1303 break;
1304 case kCheckedLoadUint8: 1304 case kCheckedLoadUint8:
(...skipping 529 matching lines...) Expand 10 before | Expand all | Expand 10 after
1834 __ li(dst, src_object); 1834 __ li(dst, src_object);
1835 } 1835 }
1836 break; 1836 break;
1837 } 1837 }
1838 case Constant::kRpoNumber: 1838 case Constant::kRpoNumber:
1839 UNREACHABLE(); // TODO(titzer): loading RPO numbers on mips. 1839 UNREACHABLE(); // TODO(titzer): loading RPO numbers on mips.
1840 break; 1840 break;
1841 } 1841 }
1842 if (destination->IsStackSlot()) __ sw(dst, g.ToMemOperand(destination)); 1842 if (destination->IsStackSlot()) __ sw(dst, g.ToMemOperand(destination));
1843 } else if (src.type() == Constant::kFloat32) { 1843 } else if (src.type() == Constant::kFloat32) {
1844 if (destination->IsDoubleStackSlot()) { 1844 if (destination->IsFPStackSlot()) {
1845 MemOperand dst = g.ToMemOperand(destination); 1845 MemOperand dst = g.ToMemOperand(destination);
1846 __ li(at, Operand(bit_cast<int32_t>(src.ToFloat32()))); 1846 __ li(at, Operand(bit_cast<int32_t>(src.ToFloat32())));
1847 __ sw(at, dst); 1847 __ sw(at, dst);
1848 } else { 1848 } else {
1849 FloatRegister dst = g.ToSingleRegister(destination); 1849 FloatRegister dst = g.ToSingleRegister(destination);
1850 __ Move(dst, src.ToFloat32()); 1850 __ Move(dst, src.ToFloat32());
1851 } 1851 }
1852 } else { 1852 } else {
1853 DCHECK_EQ(Constant::kFloat64, src.type()); 1853 DCHECK_EQ(Constant::kFloat64, src.type());
1854 DoubleRegister dst = destination->IsDoubleRegister() 1854 DoubleRegister dst = destination->IsFPRegister()
1855 ? g.ToDoubleRegister(destination) 1855 ? g.ToDoubleRegister(destination)
1856 : kScratchDoubleReg; 1856 : kScratchDoubleReg;
1857 __ Move(dst, src.ToFloat64()); 1857 __ Move(dst, src.ToFloat64());
1858 if (destination->IsDoubleStackSlot()) { 1858 if (destination->IsFPStackSlot()) {
1859 __ sdc1(dst, g.ToMemOperand(destination)); 1859 __ sdc1(dst, g.ToMemOperand(destination));
1860 } 1860 }
1861 } 1861 }
1862 } else if (source->IsDoubleRegister()) { 1862 } else if (source->IsFPRegister()) {
1863 FPURegister src = g.ToDoubleRegister(source); 1863 FPURegister src = g.ToDoubleRegister(source);
1864 if (destination->IsDoubleRegister()) { 1864 if (destination->IsFPRegister()) {
1865 FPURegister dst = g.ToDoubleRegister(destination); 1865 FPURegister dst = g.ToDoubleRegister(destination);
1866 __ Move(dst, src); 1866 __ Move(dst, src);
1867 } else { 1867 } else {
1868 DCHECK(destination->IsDoubleStackSlot()); 1868 DCHECK(destination->IsFPStackSlot());
1869 __ sdc1(src, g.ToMemOperand(destination)); 1869 __ sdc1(src, g.ToMemOperand(destination));
1870 } 1870 }
1871 } else if (source->IsDoubleStackSlot()) { 1871 } else if (source->IsFPStackSlot()) {
1872 DCHECK(destination->IsDoubleRegister() || destination->IsDoubleStackSlot()); 1872 DCHECK(destination->IsFPRegister() || destination->IsFPStackSlot());
1873 MemOperand src = g.ToMemOperand(source); 1873 MemOperand src = g.ToMemOperand(source);
1874 if (destination->IsDoubleRegister()) { 1874 if (destination->IsFPRegister()) {
1875 __ ldc1(g.ToDoubleRegister(destination), src); 1875 __ ldc1(g.ToDoubleRegister(destination), src);
1876 } else { 1876 } else {
1877 FPURegister temp = kScratchDoubleReg; 1877 FPURegister temp = kScratchDoubleReg;
1878 __ ldc1(temp, src); 1878 __ ldc1(temp, src);
1879 __ sdc1(temp, g.ToMemOperand(destination)); 1879 __ sdc1(temp, g.ToMemOperand(destination));
1880 } 1880 }
1881 } else { 1881 } else {
1882 UNREACHABLE(); 1882 UNREACHABLE();
1883 } 1883 }
1884 } 1884 }
(...skipping 23 matching lines...) Expand all
1908 } else if (source->IsStackSlot()) { 1908 } else if (source->IsStackSlot()) {
1909 DCHECK(destination->IsStackSlot()); 1909 DCHECK(destination->IsStackSlot());
1910 Register temp_0 = kScratchReg; 1910 Register temp_0 = kScratchReg;
1911 Register temp_1 = kCompareReg; 1911 Register temp_1 = kCompareReg;
1912 MemOperand src = g.ToMemOperand(source); 1912 MemOperand src = g.ToMemOperand(source);
1913 MemOperand dst = g.ToMemOperand(destination); 1913 MemOperand dst = g.ToMemOperand(destination);
1914 __ lw(temp_0, src); 1914 __ lw(temp_0, src);
1915 __ lw(temp_1, dst); 1915 __ lw(temp_1, dst);
1916 __ sw(temp_0, dst); 1916 __ sw(temp_0, dst);
1917 __ sw(temp_1, src); 1917 __ sw(temp_1, src);
1918 } else if (source->IsDoubleRegister()) { 1918 } else if (source->IsFPRegister()) {
1919 FPURegister temp = kScratchDoubleReg; 1919 FPURegister temp = kScratchDoubleReg;
1920 FPURegister src = g.ToDoubleRegister(source); 1920 FPURegister src = g.ToDoubleRegister(source);
1921 if (destination->IsDoubleRegister()) { 1921 if (destination->IsFPRegister()) {
1922 FPURegister dst = g.ToDoubleRegister(destination); 1922 FPURegister dst = g.ToDoubleRegister(destination);
1923 __ Move(temp, src); 1923 __ Move(temp, src);
1924 __ Move(src, dst); 1924 __ Move(src, dst);
1925 __ Move(dst, temp); 1925 __ Move(dst, temp);
1926 } else { 1926 } else {
1927 DCHECK(destination->IsDoubleStackSlot()); 1927 DCHECK(destination->IsFPStackSlot());
1928 MemOperand dst = g.ToMemOperand(destination); 1928 MemOperand dst = g.ToMemOperand(destination);
1929 __ Move(temp, src); 1929 __ Move(temp, src);
1930 __ ldc1(src, dst); 1930 __ ldc1(src, dst);
1931 __ sdc1(temp, dst); 1931 __ sdc1(temp, dst);
1932 } 1932 }
1933 } else if (source->IsDoubleStackSlot()) { 1933 } else if (source->IsFPStackSlot()) {
1934 DCHECK(destination->IsDoubleStackSlot()); 1934 DCHECK(destination->IsFPStackSlot());
1935 Register temp_0 = kScratchReg; 1935 Register temp_0 = kScratchReg;
1936 FPURegister temp_1 = kScratchDoubleReg; 1936 FPURegister temp_1 = kScratchDoubleReg;
1937 MemOperand src0 = g.ToMemOperand(source); 1937 MemOperand src0 = g.ToMemOperand(source);
1938 MemOperand src1(src0.rm(), src0.offset() + kIntSize); 1938 MemOperand src1(src0.rm(), src0.offset() + kIntSize);
1939 MemOperand dst0 = g.ToMemOperand(destination); 1939 MemOperand dst0 = g.ToMemOperand(destination);
1940 MemOperand dst1(dst0.rm(), dst0.offset() + kIntSize); 1940 MemOperand dst1(dst0.rm(), dst0.offset() + kIntSize);
1941 __ ldc1(temp_1, dst0); // Save destination in temp_1. 1941 __ ldc1(temp_1, dst0); // Save destination in temp_1.
1942 __ lw(temp_0, src0); // Then use temp_0 to copy source to destination. 1942 __ lw(temp_0, src0); // Then use temp_0 to copy source to destination.
1943 __ sw(temp_0, dst0); 1943 __ sw(temp_0, dst0);
1944 __ lw(temp_0, src1); 1944 __ lw(temp_0, src1);
(...skipping 32 matching lines...) Expand 10 before | Expand all | Expand 10 after
1977 padding_size -= v8::internal::Assembler::kInstrSize; 1977 padding_size -= v8::internal::Assembler::kInstrSize;
1978 } 1978 }
1979 } 1979 }
1980 } 1980 }
1981 1981
1982 #undef __ 1982 #undef __
1983 1983
1984 } // namespace compiler 1984 } // namespace compiler
1985 } // namespace internal 1985 } // namespace internal
1986 } // namespace v8 1986 } // namespace v8
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