[v8-dev] ARM: Make double registers low/high safe

src/arm/disasm-arm.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 1327 matching lines @@
         (instr->VAValue() == 0x0)) {
       DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(instr);
     } else if ((instr->VLValue() == 0x0) &&
                (instr->VCValue() == 0x1) &&
                (instr->Bit(23) == 0x0)) {
       if (instr->Bit(21) == 0x0) {
         Format(instr, "vmov'cond.32 'Dd[0], 'rt");
       } else {
         Format(instr, "vmov'cond.32 'Dd[1], 'rt");
       }
+    } else if ((instr->VLValue() == 0x1) &&
+               (instr->VCValue() == 0x1) &&
+               (instr->Bit(23) == 0x0)) {
+      if (instr->Bit(21) == 0x0) {
+        Format(instr, "vmov'cond.32 'rt, 'Dd[0]");
+      } else {
+        Format(instr, "vmov'cond.32 'rt, 'Dd[1]");
+      }
     } else if ((instr->VCValue() == 0x0) &&
                (instr->VAValue() == 0x7) &&
                (instr->Bits(19, 16) == 0x1)) {
       if (instr->VLValue() == 0) {
         if (instr->Bits(15, 12) == 0xF) {
           Format(instr, "vmsr'cond FPSCR, APSR");
         } else {
           Format(instr, "vmsr'cond FPSCR, 'rt");
         }
       } else {
@@ skipping 432 matching lines @@
     v8::internal::PrintF(
         f, "%p    %08x      %s\n",
         prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_ARM