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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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102 V(r16) V(r17) V(r18) V(r19) V(r20) V(r21) V(r22) V(r23) \ | 102 V(r16) V(r17) V(r18) V(r19) V(r20) V(r21) V(r22) V(r23) \ |
103 V(r24) V(r25) V(r26) V(r27) V(r28) V(r30) | 103 V(r24) V(r25) V(r26) V(r27) V(r28) V(r30) |
104 #endif | 104 #endif |
105 | 105 |
106 #define DOUBLE_REGISTERS(V) \ | 106 #define DOUBLE_REGISTERS(V) \ |
107 V(d0) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) \ | 107 V(d0) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) \ |
108 V(d8) V(d9) V(d10) V(d11) V(d12) V(d13) V(d14) V(d15) \ | 108 V(d8) V(d9) V(d10) V(d11) V(d12) V(d13) V(d14) V(d15) \ |
109 V(d16) V(d17) V(d18) V(d19) V(d20) V(d21) V(d22) V(d23) \ | 109 V(d16) V(d17) V(d18) V(d19) V(d20) V(d21) V(d22) V(d23) \ |
110 V(d24) V(d25) V(d26) V(d27) V(d28) V(d29) V(d30) V(d31) | 110 V(d24) V(d25) V(d26) V(d27) V(d28) V(d29) V(d30) V(d31) |
111 | 111 |
| 112 #define FLOAT_REGISTERS DOUBLE_REGISTERS |
| 113 |
112 #define ALLOCATABLE_DOUBLE_REGISTERS(V) \ | 114 #define ALLOCATABLE_DOUBLE_REGISTERS(V) \ |
113 V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) \ | 115 V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) \ |
114 V(d8) V(d9) V(d10) V(d11) V(d12) V(d15) \ | 116 V(d8) V(d9) V(d10) V(d11) V(d12) V(d15) \ |
115 V(d16) V(d17) V(d18) V(d19) V(d20) V(d21) V(d22) V(d23) \ | 117 V(d16) V(d17) V(d18) V(d19) V(d20) V(d21) V(d22) V(d23) \ |
116 V(d24) V(d25) V(d26) V(d27) V(d28) V(d29) V(d30) V(d31) | 118 V(d24) V(d25) V(d26) V(d27) V(d28) V(d29) V(d30) V(d31) |
117 // clang-format on | 119 // clang-format on |
118 | 120 |
119 // CPU Registers. | 121 // CPU Registers. |
120 // | 122 // |
121 // 1) We would prefer to use an enum, but enum values are assignment- | 123 // 1) We would prefer to use an enum, but enum values are assignment- |
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231 } | 233 } |
232 | 234 |
233 static DoubleRegister from_code(int code) { | 235 static DoubleRegister from_code(int code) { |
234 DoubleRegister r = {code}; | 236 DoubleRegister r = {code}; |
235 return r; | 237 return r; |
236 } | 238 } |
237 | 239 |
238 int reg_code; | 240 int reg_code; |
239 }; | 241 }; |
240 | 242 |
| 243 typedef DoubleRegister FloatRegister; |
| 244 |
| 245 // TODO(ppc) Define SIMD registers. |
| 246 typedef DoubleRegister Simd128Register; |
| 247 |
241 #define DECLARE_REGISTER(R) \ | 248 #define DECLARE_REGISTER(R) \ |
242 const DoubleRegister R = {DoubleRegister::kCode_##R}; | 249 const DoubleRegister R = {DoubleRegister::kCode_##R}; |
243 DOUBLE_REGISTERS(DECLARE_REGISTER) | 250 DOUBLE_REGISTERS(DECLARE_REGISTER) |
244 #undef DECLARE_REGISTER | 251 #undef DECLARE_REGISTER |
245 const Register no_dreg = {Register::kCode_no_reg}; | 252 const Register no_dreg = {Register::kCode_no_reg}; |
246 | 253 |
247 // Aliases for double registers. Defined using #define instead of | 254 // Aliases for double registers. Defined using #define instead of |
248 // "static const DoubleRegister&" because Clang complains otherwise when a | 255 // "static const DoubleRegister&" because Clang complains otherwise when a |
249 // compilation unit that includes this header doesn't use the variables. | 256 // compilation unit that includes this header doesn't use the variables. |
250 #define kFirstCalleeSavedDoubleReg d14 | 257 #define kFirstCalleeSavedDoubleReg d14 |
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276 | 283 |
277 const CRegister cr0 = {0}; | 284 const CRegister cr0 = {0}; |
278 const CRegister cr1 = {1}; | 285 const CRegister cr1 = {1}; |
279 const CRegister cr2 = {2}; | 286 const CRegister cr2 = {2}; |
280 const CRegister cr3 = {3}; | 287 const CRegister cr3 = {3}; |
281 const CRegister cr4 = {4}; | 288 const CRegister cr4 = {4}; |
282 const CRegister cr5 = {5}; | 289 const CRegister cr5 = {5}; |
283 const CRegister cr6 = {6}; | 290 const CRegister cr6 = {6}; |
284 const CRegister cr7 = {7}; | 291 const CRegister cr7 = {7}; |
285 | 292 |
286 // TODO(ppc) Define SIMD registers. | |
287 typedef DoubleRegister Simd128Register; | |
288 | |
289 // ----------------------------------------------------------------------------- | 293 // ----------------------------------------------------------------------------- |
290 // Machine instruction Operands | 294 // Machine instruction Operands |
291 | 295 |
292 #if V8_TARGET_ARCH_PPC64 | 296 #if V8_TARGET_ARCH_PPC64 |
293 const RelocInfo::Mode kRelocInfo_NONEPTR = RelocInfo::NONE64; | 297 const RelocInfo::Mode kRelocInfo_NONEPTR = RelocInfo::NONE64; |
294 #else | 298 #else |
295 const RelocInfo::Mode kRelocInfo_NONEPTR = RelocInfo::NONE32; | 299 const RelocInfo::Mode kRelocInfo_NONEPTR = RelocInfo::NONE32; |
296 #endif | 300 #endif |
297 | 301 |
298 // Class Operand represents a shifter operand in data processing instructions | 302 // Class Operand represents a shifter operand in data processing instructions |
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1475 | 1479 |
1476 | 1480 |
1477 class EnsureSpace BASE_EMBEDDED { | 1481 class EnsureSpace BASE_EMBEDDED { |
1478 public: | 1482 public: |
1479 explicit EnsureSpace(Assembler* assembler) { assembler->CheckBuffer(); } | 1483 explicit EnsureSpace(Assembler* assembler) { assembler->CheckBuffer(); } |
1480 }; | 1484 }; |
1481 } // namespace internal | 1485 } // namespace internal |
1482 } // namespace v8 | 1486 } // namespace v8 |
1483 | 1487 |
1484 #endif // V8_PPC_ASSEMBLER_PPC_H_ | 1488 #endif // V8_PPC_ASSEMBLER_PPC_H_ |
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