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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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56 #define ALLOCATABLE_GENERAL_REGISTERS(V) \ | 56 #define ALLOCATABLE_GENERAL_REGISTERS(V) \ |
57 V(v0) V(v1) V(a0) V(a1) V(a2) V(a3) \ | 57 V(v0) V(v1) V(a0) V(a1) V(a2) V(a3) \ |
58 V(t0) V(t1) V(t2) V(t3) V(t4) V(t5) V(t6) V(s7) | 58 V(t0) V(t1) V(t2) V(t3) V(t4) V(t5) V(t6) V(s7) |
59 | 59 |
60 #define DOUBLE_REGISTERS(V) \ | 60 #define DOUBLE_REGISTERS(V) \ |
61 V(f0) V(f1) V(f2) V(f3) V(f4) V(f5) V(f6) V(f7) \ | 61 V(f0) V(f1) V(f2) V(f3) V(f4) V(f5) V(f6) V(f7) \ |
62 V(f8) V(f9) V(f10) V(f11) V(f12) V(f13) V(f14) V(f15) \ | 62 V(f8) V(f9) V(f10) V(f11) V(f12) V(f13) V(f14) V(f15) \ |
63 V(f16) V(f17) V(f18) V(f19) V(f20) V(f21) V(f22) V(f23) \ | 63 V(f16) V(f17) V(f18) V(f19) V(f20) V(f21) V(f22) V(f23) \ |
64 V(f24) V(f25) V(f26) V(f27) V(f28) V(f29) V(f30) V(f31) | 64 V(f24) V(f25) V(f26) V(f27) V(f28) V(f29) V(f30) V(f31) |
65 | 65 |
| 66 #define FLOAT_REGISTERS DOUBLE_REGISTERS |
| 67 |
66 #define ALLOCATABLE_DOUBLE_REGISTERS(V) \ | 68 #define ALLOCATABLE_DOUBLE_REGISTERS(V) \ |
67 V(f0) V(f2) V(f4) V(f6) V(f8) V(f10) V(f12) V(f14) \ | 69 V(f0) V(f2) V(f4) V(f6) V(f8) V(f10) V(f12) V(f14) \ |
68 V(f16) V(f18) V(f20) V(f22) V(f24) V(f26) | 70 V(f16) V(f18) V(f20) V(f22) V(f24) V(f26) |
69 // clang-format on | 71 // clang-format on |
70 | 72 |
71 // CPU Registers. | 73 // CPU Registers. |
72 // | 74 // |
73 // 1) We would prefer to use an enum, but enum values are assignment- | 75 // 1) We would prefer to use an enum, but enum values are assignment- |
74 // compatible with int, which has caused code-generation bugs. | 76 // compatible with int, which has caused code-generation bugs. |
75 // | 77 // |
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147 GENERAL_REGISTERS(DECLARE_REGISTER) | 149 GENERAL_REGISTERS(DECLARE_REGISTER) |
148 #undef DECLARE_REGISTER | 150 #undef DECLARE_REGISTER |
149 const Register no_reg = {Register::kCode_no_reg}; | 151 const Register no_reg = {Register::kCode_no_reg}; |
150 | 152 |
151 | 153 |
152 int ToNumber(Register reg); | 154 int ToNumber(Register reg); |
153 | 155 |
154 Register ToRegister(int num); | 156 Register ToRegister(int num); |
155 | 157 |
156 // Coprocessor register. | 158 // Coprocessor register. |
157 struct DoubleRegister { | 159 struct FPURegister { |
158 enum Code { | 160 enum Code { |
159 #define REGISTER_CODE(R) kCode_##R, | 161 #define REGISTER_CODE(R) kCode_##R, |
160 DOUBLE_REGISTERS(REGISTER_CODE) | 162 DOUBLE_REGISTERS(REGISTER_CODE) |
161 #undef REGISTER_CODE | 163 #undef REGISTER_CODE |
162 kAfterLast, | 164 kAfterLast, |
163 kCode_no_reg = -1 | 165 kCode_no_reg = -1 |
164 }; | 166 }; |
165 | 167 |
166 static const int kMaxNumRegisters = Code::kAfterLast; | 168 static const int kMaxNumRegisters = Code::kAfterLast; |
167 | 169 |
168 inline static int NumRegisters(); | 170 inline static int NumRegisters(); |
169 | 171 |
170 // TODO(plind): Warning, inconsistent numbering here. kNumFPURegisters refers | 172 // TODO(plind): Warning, inconsistent numbering here. kNumFPURegisters refers |
171 // to number of 32-bit FPU regs, but kNumAllocatableRegisters refers to | 173 // to number of 32-bit FPU regs, but kNumAllocatableRegisters refers to |
172 // number of Double regs (64-bit regs, or FPU-reg-pairs). | 174 // number of Double regs (64-bit regs, or FPU-reg-pairs). |
173 | 175 |
174 const char* ToString(); | 176 const char* ToString(); |
175 bool IsAllocatable() const; | 177 bool IsAllocatable() const; |
176 bool is_valid() const { return 0 <= reg_code && reg_code < kMaxNumRegisters; } | 178 bool is_valid() const { return 0 <= reg_code && reg_code < kMaxNumRegisters; } |
177 bool is(DoubleRegister reg) const { return reg_code == reg.reg_code; } | 179 bool is(FPURegister reg) const { return reg_code == reg.reg_code; } |
178 DoubleRegister low() const { | 180 FPURegister low() const { |
179 // Find low reg of a Double-reg pair, which is the reg itself. | 181 // Find low reg of a Double-reg pair, which is the reg itself. |
180 DCHECK(reg_code % 2 == 0); // Specified Double reg must be even. | 182 DCHECK(reg_code % 2 == 0); // Specified Double reg must be even. |
181 DoubleRegister reg; | 183 FPURegister reg; |
182 reg.reg_code = reg_code; | 184 reg.reg_code = reg_code; |
183 DCHECK(reg.is_valid()); | 185 DCHECK(reg.is_valid()); |
184 return reg; | 186 return reg; |
185 } | 187 } |
186 DoubleRegister high() const { | 188 FPURegister high() const { |
187 // Find high reg of a Doubel-reg pair, which is reg + 1. | 189 // Find high reg of a Doubel-reg pair, which is reg + 1. |
188 DCHECK(reg_code % 2 == 0); // Specified Double reg must be even. | 190 DCHECK(reg_code % 2 == 0); // Specified Double reg must be even. |
189 DoubleRegister reg; | 191 FPURegister reg; |
190 reg.reg_code = reg_code + 1; | 192 reg.reg_code = reg_code + 1; |
191 DCHECK(reg.is_valid()); | 193 DCHECK(reg.is_valid()); |
192 return reg; | 194 return reg; |
193 } | 195 } |
194 | 196 |
195 int code() const { | 197 int code() const { |
196 DCHECK(is_valid()); | 198 DCHECK(is_valid()); |
197 return reg_code; | 199 return reg_code; |
198 } | 200 } |
199 int bit() const { | 201 int bit() const { |
200 DCHECK(is_valid()); | 202 DCHECK(is_valid()); |
201 return 1 << reg_code; | 203 return 1 << reg_code; |
202 } | 204 } |
203 | 205 |
204 static DoubleRegister from_code(int code) { | 206 static FPURegister from_code(int code) { |
205 DoubleRegister r = {code}; | 207 FPURegister r = {code}; |
206 return r; | 208 return r; |
207 } | 209 } |
208 void setcode(int f) { | 210 void setcode(int f) { |
209 reg_code = f; | 211 reg_code = f; |
210 DCHECK(is_valid()); | 212 DCHECK(is_valid()); |
211 } | 213 } |
212 // Unfortunately we can't make this private in a struct. | 214 // Unfortunately we can't make this private in a struct. |
213 int reg_code; | 215 int reg_code; |
214 }; | 216 }; |
215 | 217 |
216 // A few double registers are reserved: one as a scratch register and one to | 218 // A few double registers are reserved: one as a scratch register and one to |
217 // hold 0.0. | 219 // hold 0.0. |
218 // f28: 0.0 | 220 // f28: 0.0 |
219 // f30: scratch register. | 221 // f30: scratch register. |
220 | 222 |
221 // V8 now supports the O32 ABI, and the FPU Registers are organized as 32 | 223 // V8 now supports the O32 ABI, and the FPU Registers are organized as 32 |
222 // 32-bit registers, f0 through f31. When used as 'double' they are used | 224 // 32-bit registers, f0 through f31. When used as 'double' they are used |
223 // in pairs, starting with the even numbered register. So a double operation | 225 // in pairs, starting with the even numbered register. So a double operation |
224 // on f0 really uses f0 and f1. | 226 // on f0 really uses f0 and f1. |
225 // (Modern mips hardware also supports 32 64-bit registers, via setting | 227 // (Modern mips hardware also supports 32 64-bit registers, via setting |
226 // (priviledged) Status Register FR bit to 1. This is used by the N32 ABI, | 228 // (priviledged) Status Register FR bit to 1. This is used by the N32 ABI, |
227 // but it is not in common use. Someday we will want to support this in v8.) | 229 // but it is not in common use. Someday we will want to support this in v8.) |
228 | 230 |
229 // For O32 ABI, Floats and Doubles refer to same set of 32 32-bit registers. | 231 // For O32 ABI, Floats and Doubles refer to same set of 32 32-bit registers. |
230 typedef DoubleRegister FPURegister; | 232 typedef FPURegister FloatRegister; |
231 typedef DoubleRegister FloatRegister; | 233 |
| 234 typedef FPURegister DoubleRegister; |
| 235 |
| 236 // TODO(mips) Define SIMD registers. |
| 237 typedef FPURegister Simd128Register; |
232 | 238 |
233 const DoubleRegister no_freg = {-1}; | 239 const DoubleRegister no_freg = {-1}; |
234 | 240 |
235 const DoubleRegister f0 = {0}; // Return value in hard float mode. | 241 const DoubleRegister f0 = {0}; // Return value in hard float mode. |
236 const DoubleRegister f1 = {1}; | 242 const DoubleRegister f1 = {1}; |
237 const DoubleRegister f2 = {2}; | 243 const DoubleRegister f2 = {2}; |
238 const DoubleRegister f3 = {3}; | 244 const DoubleRegister f3 = {3}; |
239 const DoubleRegister f4 = {4}; | 245 const DoubleRegister f4 = {4}; |
240 const DoubleRegister f5 = {5}; | 246 const DoubleRegister f5 = {5}; |
241 const DoubleRegister f6 = {6}; | 247 const DoubleRegister f6 = {6}; |
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297 reg_code = f; | 303 reg_code = f; |
298 DCHECK(is_valid()); | 304 DCHECK(is_valid()); |
299 } | 305 } |
300 // Unfortunately we can't make this private in a struct. | 306 // Unfortunately we can't make this private in a struct. |
301 int reg_code; | 307 int reg_code; |
302 }; | 308 }; |
303 | 309 |
304 const FPUControlRegister no_fpucreg = { kInvalidFPUControlRegister }; | 310 const FPUControlRegister no_fpucreg = { kInvalidFPUControlRegister }; |
305 const FPUControlRegister FCSR = { kFCSRRegister }; | 311 const FPUControlRegister FCSR = { kFCSRRegister }; |
306 | 312 |
307 // TODO(mips) Define SIMD registers. | |
308 typedef DoubleRegister Simd128Register; | |
309 | |
310 // ----------------------------------------------------------------------------- | 313 // ----------------------------------------------------------------------------- |
311 // Machine instruction Operands. | 314 // Machine instruction Operands. |
312 | 315 |
313 // Class Operand represents a shifter operand in data processing instructions. | 316 // Class Operand represents a shifter operand in data processing instructions. |
314 class Operand BASE_EMBEDDED { | 317 class Operand BASE_EMBEDDED { |
315 public: | 318 public: |
316 // Immediate. | 319 // Immediate. |
317 INLINE(explicit Operand(int32_t immediate, | 320 INLINE(explicit Operand(int32_t immediate, |
318 RelocInfo::Mode rmode = RelocInfo::NONE32)); | 321 RelocInfo::Mode rmode = RelocInfo::NONE32)); |
319 INLINE(explicit Operand(const ExternalReference& f)); | 322 INLINE(explicit Operand(const ExternalReference& f)); |
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1467 public: | 1470 public: |
1468 explicit EnsureSpace(Assembler* assembler) { | 1471 explicit EnsureSpace(Assembler* assembler) { |
1469 assembler->CheckBuffer(); | 1472 assembler->CheckBuffer(); |
1470 } | 1473 } |
1471 }; | 1474 }; |
1472 | 1475 |
1473 } // namespace internal | 1476 } // namespace internal |
1474 } // namespace v8 | 1477 } // namespace v8 |
1475 | 1478 |
1476 #endif // V8_ARM_ASSEMBLER_MIPS_H_ | 1479 #endif // V8_ARM_ASSEMBLER_MIPS_H_ |
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