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Side by Side Diff: src/arm64/assembler-arm64.h

Issue 1954953002: Add the concept of FloatRegister for all platforms. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Rebase Created 4 years, 7 months ago
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1 // Copyright 2013 the V8 project authors. All rights reserved. 1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_ARM64_ASSEMBLER_ARM64_H_ 5 #ifndef V8_ARM64_ASSEMBLER_ARM64_H_
6 #define V8_ARM64_ASSEMBLER_ARM64_H_ 6 #define V8_ARM64_ASSEMBLER_ARM64_H_
7 7
8 #include <deque> 8 #include <deque>
9 #include <list> 9 #include <list>
10 #include <map> 10 #include <map>
(...skipping 22 matching lines...) Expand all
33 R(x0) R(x1) R(x2) R(x3) R(x4) R(x5) R(x6) R(x7) \ 33 R(x0) R(x1) R(x2) R(x3) R(x4) R(x5) R(x6) R(x7) \
34 R(x8) R(x9) R(x10) R(x11) R(x12) R(x13) R(x14) R(x15) \ 34 R(x8) R(x9) R(x10) R(x11) R(x12) R(x13) R(x14) R(x15) \
35 R(x16) R(x17) R(x18) R(x19) R(x20) R(x21) R(x22) R(x23) \ 35 R(x16) R(x17) R(x18) R(x19) R(x20) R(x21) R(x22) R(x23) \
36 R(x24) R(x25) R(x26) R(x27) R(x28) R(x29) R(x30) R(x31) 36 R(x24) R(x25) R(x26) R(x27) R(x28) R(x29) R(x30) R(x31)
37 37
38 #define ALLOCATABLE_GENERAL_REGISTERS(R) \ 38 #define ALLOCATABLE_GENERAL_REGISTERS(R) \
39 R(x0) R(x1) R(x2) R(x3) R(x4) R(x5) R(x6) R(x7) \ 39 R(x0) R(x1) R(x2) R(x3) R(x4) R(x5) R(x6) R(x7) \
40 R(x8) R(x9) R(x10) R(x11) R(x12) R(x13) R(x14) R(x15) \ 40 R(x8) R(x9) R(x10) R(x11) R(x12) R(x13) R(x14) R(x15) \
41 R(x18) R(x19) R(x20) R(x21) R(x22) R(x23) R(x24) R(x27) 41 R(x18) R(x19) R(x20) R(x21) R(x22) R(x23) R(x24) R(x27)
42 42
43 #define FLOAT_REGISTERS(V) \
44 V(s0) V(s1) V(s2) V(s3) V(s4) V(s5) V(s6) V(s7) \
45 V(s8) V(s9) V(s10) V(s11) V(s12) V(s13) V(s14) V(s15) \
46 V(s16) V(s17) V(s18) V(s19) V(s20) V(s21) V(s22) V(s23) \
47 V(s24) V(s25) V(s26) V(s27) V(s28) V(s29) V(s30) V(s31)
48
43 #define DOUBLE_REGISTERS(R) \ 49 #define DOUBLE_REGISTERS(R) \
44 R(d0) R(d1) R(d2) R(d3) R(d4) R(d5) R(d6) R(d7) \ 50 R(d0) R(d1) R(d2) R(d3) R(d4) R(d5) R(d6) R(d7) \
45 R(d8) R(d9) R(d10) R(d11) R(d12) R(d13) R(d14) R(d15) \ 51 R(d8) R(d9) R(d10) R(d11) R(d12) R(d13) R(d14) R(d15) \
46 R(d16) R(d17) R(d18) R(d19) R(d20) R(d21) R(d22) R(d23) \ 52 R(d16) R(d17) R(d18) R(d19) R(d20) R(d21) R(d22) R(d23) \
47 R(d24) R(d25) R(d26) R(d27) R(d28) R(d29) R(d30) R(d31) 53 R(d24) R(d25) R(d26) R(d27) R(d28) R(d29) R(d30) R(d31)
48 54
49 #define ALLOCATABLE_DOUBLE_REGISTERS(R) \ 55 #define ALLOCATABLE_DOUBLE_REGISTERS(R) \
50 R(d0) R(d1) R(d2) R(d3) R(d4) R(d5) R(d6) R(d7) \ 56 R(d0) R(d1) R(d2) R(d3) R(d4) R(d5) R(d6) R(d7) \
51 R(d8) R(d9) R(d10) R(d11) R(d12) R(d13) R(d14) R(d16) \ 57 R(d8) R(d9) R(d10) R(d11) R(d12) R(d13) R(d14) R(d16) \
52 R(d17) R(d18) R(d19) R(d20) R(d21) R(d22) R(d23) R(d24) \ 58 R(d17) R(d18) R(d19) R(d20) R(d21) R(d22) R(d23) R(d24) \
(...skipping 306 matching lines...) Expand 10 before | Expand all | Expand 10 after
359 // arguments. At least one argument (reg1) must be valid (not NoCPUReg). 365 // arguments. At least one argument (reg1) must be valid (not NoCPUReg).
360 bool AreSameSizeAndType(const CPURegister& reg1, 366 bool AreSameSizeAndType(const CPURegister& reg1,
361 const CPURegister& reg2, 367 const CPURegister& reg2,
362 const CPURegister& reg3 = NoCPUReg, 368 const CPURegister& reg3 = NoCPUReg,
363 const CPURegister& reg4 = NoCPUReg, 369 const CPURegister& reg4 = NoCPUReg,
364 const CPURegister& reg5 = NoCPUReg, 370 const CPURegister& reg5 = NoCPUReg,
365 const CPURegister& reg6 = NoCPUReg, 371 const CPURegister& reg6 = NoCPUReg,
366 const CPURegister& reg7 = NoCPUReg, 372 const CPURegister& reg7 = NoCPUReg,
367 const CPURegister& reg8 = NoCPUReg); 373 const CPURegister& reg8 = NoCPUReg);
368 374
369 375 typedef FPRegister FloatRegister;
370 typedef FPRegister DoubleRegister; 376 typedef FPRegister DoubleRegister;
371 377
372 // TODO(arm64) Define SIMD registers. 378 // TODO(arm64) Define SIMD registers.
373 typedef FPRegister Simd128Register; 379 typedef FPRegister Simd128Register;
374 380
375 // ----------------------------------------------------------------------------- 381 // -----------------------------------------------------------------------------
376 // Lists of registers. 382 // Lists of registers.
377 class CPURegList { 383 class CPURegList {
378 public: 384 public:
379 explicit CPURegList(CPURegister reg1, 385 explicit CPURegList(CPURegister reg1,
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2189 public: 2195 public:
2190 explicit EnsureSpace(Assembler* assembler) { 2196 explicit EnsureSpace(Assembler* assembler) {
2191 assembler->CheckBufferSpace(); 2197 assembler->CheckBufferSpace();
2192 } 2198 }
2193 }; 2199 };
2194 2200
2195 } // namespace internal 2201 } // namespace internal
2196 } // namespace v8 2202 } // namespace v8
2197 2203
2198 #endif // V8_ARM64_ASSEMBLER_ARM64_H_ 2204 #endif // V8_ARM64_ASSEMBLER_ARM64_H_
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