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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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50 namespace internal { | 50 namespace internal { |
51 | 51 |
52 // clang-format off | 52 // clang-format off |
53 #define GENERAL_REGISTERS(V) \ | 53 #define GENERAL_REGISTERS(V) \ |
54 V(r0) V(r1) V(r2) V(r3) V(r4) V(r5) V(r6) V(r7) \ | 54 V(r0) V(r1) V(r2) V(r3) V(r4) V(r5) V(r6) V(r7) \ |
55 V(r8) V(r9) V(r10) V(fp) V(ip) V(sp) V(lr) V(pc) | 55 V(r8) V(r9) V(r10) V(fp) V(ip) V(sp) V(lr) V(pc) |
56 | 56 |
57 #define ALLOCATABLE_GENERAL_REGISTERS(V) \ | 57 #define ALLOCATABLE_GENERAL_REGISTERS(V) \ |
58 V(r0) V(r1) V(r2) V(r3) V(r4) V(r5) V(r6) V(r7) V(r8) | 58 V(r0) V(r1) V(r2) V(r3) V(r4) V(r5) V(r6) V(r7) V(r8) |
59 | 59 |
| 60 #define FLOAT_REGISTERS(V) \ |
| 61 V(s0) V(s1) V(s2) V(s3) V(s4) V(s5) V(s6) V(s7) \ |
| 62 V(s8) V(s9) V(s10) V(s11) V(s12) V(s13) V(s14) V(s15) \ |
| 63 V(s16) V(s17) V(s18) V(s19) V(s20) V(s21) V(s22) V(s23) \ |
| 64 V(s24) V(s25) V(s26) V(s27) V(s28) V(s29) V(s30) V(s31) |
| 65 |
60 #define DOUBLE_REGISTERS(V) \ | 66 #define DOUBLE_REGISTERS(V) \ |
61 V(d0) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) \ | 67 V(d0) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) \ |
62 V(d8) V(d9) V(d10) V(d11) V(d12) V(d13) V(d14) V(d15) \ | 68 V(d8) V(d9) V(d10) V(d11) V(d12) V(d13) V(d14) V(d15) \ |
63 V(d16) V(d17) V(d18) V(d19) V(d20) V(d21) V(d22) V(d23) \ | 69 V(d16) V(d17) V(d18) V(d19) V(d20) V(d21) V(d22) V(d23) \ |
64 V(d24) V(d25) V(d26) V(d27) V(d28) V(d29) V(d30) V(d31) | 70 V(d24) V(d25) V(d26) V(d27) V(d28) V(d29) V(d30) V(d31) |
65 | 71 |
66 #define ALLOCATABLE_DOUBLE_REGISTERS(V) \ | 72 #define ALLOCATABLE_DOUBLE_REGISTERS(V) \ |
67 V(d0) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) \ | 73 V(d0) V(d1) V(d2) V(d3) V(d4) V(d5) V(d6) V(d7) \ |
68 V(d8) V(d9) V(d10) V(d11) V(d12) V(d13) \ | 74 V(d8) V(d9) V(d10) V(d11) V(d12) V(d13) \ |
69 V(d16) V(d17) V(d18) V(d19) V(d20) V(d21) V(d22) V(d23) \ | 75 V(d16) V(d17) V(d18) V(d19) V(d20) V(d21) V(d22) V(d23) \ |
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147 bool is_valid() const { return 0 <= reg_code && reg_code < 32; } | 153 bool is_valid() const { return 0 <= reg_code && reg_code < 32; } |
148 bool is(SwVfpRegister reg) const { return reg_code == reg.reg_code; } | 154 bool is(SwVfpRegister reg) const { return reg_code == reg.reg_code; } |
149 int code() const { | 155 int code() const { |
150 DCHECK(is_valid()); | 156 DCHECK(is_valid()); |
151 return reg_code; | 157 return reg_code; |
152 } | 158 } |
153 int bit() const { | 159 int bit() const { |
154 DCHECK(is_valid()); | 160 DCHECK(is_valid()); |
155 return 1 << reg_code; | 161 return 1 << reg_code; |
156 } | 162 } |
| 163 static SwVfpRegister from_code(int code) { |
| 164 SwVfpRegister r = {code}; |
| 165 return r; |
| 166 } |
157 void split_code(int* vm, int* m) const { | 167 void split_code(int* vm, int* m) const { |
158 DCHECK(is_valid()); | 168 DCHECK(is_valid()); |
159 *m = reg_code & 0x1; | 169 *m = reg_code & 0x1; |
160 *vm = reg_code >> 1; | 170 *vm = reg_code >> 1; |
161 } | 171 } |
162 | 172 |
163 int reg_code; | 173 int reg_code; |
164 }; | 174 }; |
165 | 175 |
| 176 typedef SwVfpRegister FloatRegister; |
166 | 177 |
167 // Double word VFP register. | 178 // Double word VFP register. |
168 struct DoubleRegister { | 179 struct DwVfpRegister { |
169 enum Code { | 180 enum Code { |
170 #define REGISTER_CODE(R) kCode_##R, | 181 #define REGISTER_CODE(R) kCode_##R, |
171 DOUBLE_REGISTERS(REGISTER_CODE) | 182 DOUBLE_REGISTERS(REGISTER_CODE) |
172 #undef REGISTER_CODE | 183 #undef REGISTER_CODE |
173 kAfterLast, | 184 kAfterLast, |
174 kCode_no_reg = -1 | 185 kCode_no_reg = -1 |
175 }; | 186 }; |
176 | 187 |
177 static const int kMaxNumRegisters = Code::kAfterLast; | 188 static const int kMaxNumRegisters = Code::kAfterLast; |
178 | 189 |
179 inline static int NumRegisters(); | 190 inline static int NumRegisters(); |
180 | 191 |
181 // A few double registers are reserved: one as a scratch register and one to | 192 // A few double registers are reserved: one as a scratch register and one to |
182 // hold 0.0, that does not fit in the immediate field of vmov instructions. | 193 // hold 0.0, that does not fit in the immediate field of vmov instructions. |
183 // d14: 0.0 | 194 // d14: 0.0 |
184 // d15: scratch register. | 195 // d15: scratch register. |
185 static const int kSizeInBytes = 8; | 196 static const int kSizeInBytes = 8; |
186 | 197 |
187 const char* ToString(); | 198 const char* ToString(); |
188 bool IsAllocatable() const; | 199 bool IsAllocatable() const; |
189 bool is_valid() const { return 0 <= reg_code && reg_code < kMaxNumRegisters; } | 200 bool is_valid() const { return 0 <= reg_code && reg_code < kMaxNumRegisters; } |
190 bool is(DoubleRegister reg) const { return reg_code == reg.reg_code; } | 201 bool is(DwVfpRegister reg) const { return reg_code == reg.reg_code; } |
191 int code() const { | 202 int code() const { |
192 DCHECK(is_valid()); | 203 DCHECK(is_valid()); |
193 return reg_code; | 204 return reg_code; |
194 } | 205 } |
195 int bit() const { | 206 int bit() const { |
196 DCHECK(is_valid()); | 207 DCHECK(is_valid()); |
197 return 1 << reg_code; | 208 return 1 << reg_code; |
198 } | 209 } |
199 | 210 |
200 static DoubleRegister from_code(int code) { | 211 static DwVfpRegister from_code(int code) { |
201 DoubleRegister r = {code}; | 212 DwVfpRegister r = {code}; |
202 return r; | 213 return r; |
203 } | 214 } |
204 void split_code(int* vm, int* m) const { | 215 void split_code(int* vm, int* m) const { |
205 DCHECK(is_valid()); | 216 DCHECK(is_valid()); |
206 *m = (reg_code & 0x10) >> 4; | 217 *m = (reg_code & 0x10) >> 4; |
207 *vm = reg_code & 0x0F; | 218 *vm = reg_code & 0x0F; |
208 } | 219 } |
209 | 220 |
210 int reg_code; | 221 int reg_code; |
211 }; | 222 }; |
212 | 223 |
213 | 224 |
214 typedef DoubleRegister DwVfpRegister; | 225 typedef DwVfpRegister DoubleRegister; |
215 | 226 |
216 | 227 |
217 // Double word VFP register d0-15. | 228 // Double word VFP register d0-15. |
218 struct LowDwVfpRegister { | 229 struct LowDwVfpRegister { |
219 public: | 230 public: |
220 static const int kMaxNumLowRegisters = 16; | 231 static const int kMaxNumLowRegisters = 16; |
221 operator DwVfpRegister() const { | 232 operator DwVfpRegister() const { |
222 DwVfpRegister r = { reg_code }; | 233 DwVfpRegister r = { reg_code }; |
223 return r; | 234 return r; |
224 } | 235 } |
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1661 explicit EnsureSpace(Assembler* assembler) { | 1672 explicit EnsureSpace(Assembler* assembler) { |
1662 assembler->CheckBuffer(); | 1673 assembler->CheckBuffer(); |
1663 } | 1674 } |
1664 }; | 1675 }; |
1665 | 1676 |
1666 | 1677 |
1667 } // namespace internal | 1678 } // namespace internal |
1668 } // namespace v8 | 1679 } // namespace v8 |
1669 | 1680 |
1670 #endif // V8_ARM_ASSEMBLER_ARM_H_ | 1681 #endif // V8_ARM_ASSEMBLER_ARM_H_ |
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