Unboxed Float64x2 fields and some misc fixes

runtime/vm/intermediate_language_ia32.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_IA32.
 #if defined(TARGET_ARCH_IA32)
 
 #include "vm/intermediate_language.h"
 
 #include "vm/dart_entry.h"
@@ skipping 1659 matching lines @@
 
     if (is_initialization_) {
       const Class* cls = NULL;
       switch (cid) {
         case kDoubleCid:
           cls = &compiler->double_class();
           break;
         case kFloat32x4Cid:
           cls = &compiler->float32x4_class();
           break;
+        case kFloat64x2Cid:
+          cls = &compiler->float64x2_class();
+          break;
         default:
           UNREACHABLE();
       }
 
       StoreInstanceFieldSlowPath* slow_path =
           new StoreInstanceFieldSlowPath(this, *cls);
       compiler->AddSlowPathCode(slow_path);
 
       __ TryAllocate(*cls,
                      slow_path->entry_label(),
@@ skipping 10 matching lines @@
     }
     switch (cid) {
       case kDoubleCid:
         __ Comment("UnboxedDoubleStoreInstanceFieldInstr");
         __ movsd(FieldAddress(temp, Double::value_offset()), value);
       break;
       case kFloat32x4Cid:
         __ Comment("UnboxedFloat32x4StoreInstanceFieldInstr");
         __ movups(FieldAddress(temp, Float32x4::value_offset()), value);
       break;
+      case kFloat64x2Cid:
+        __ Comment("UnboxedFloat64x2StoreInstanceFieldInstr");
+        __ movups(FieldAddress(temp, Float64x2::value_offset()), value);
+      break;
       default:
         UNREACHABLE();
     }
     return;
   }
 
   if (IsPotentialUnboxedStore()) {
     Register value_reg = locs()->in(1).reg();
     Register temp = locs()->temp(0).reg();
     Register temp2 = locs()->temp(1).reg();
     FpuRegister fpu_temp = locs()->temp(2).fpu_reg();
 
     Label store_pointer;
     Label store_double;
     Label store_float32x4;
+    Label store_float64x2;
 
     __ LoadObject(temp, Field::ZoneHandle(field().raw()));
 
     __ cmpl(FieldAddress(temp, Field::is_nullable_offset()),
             Immediate(kNullCid));
     __ j(EQUAL, &store_pointer);
 
     __ movzxb(temp2, FieldAddress(temp, Field::kind_bits_offset()));
     __ testl(temp2, Immediate(1 << Field::kUnboxingCandidateBit));
     __ j(ZERO, &store_pointer);
 
     __ cmpl(FieldAddress(temp, Field::guarded_cid_offset()),
             Immediate(kDoubleCid));
     __ j(EQUAL, &store_double);
 
     __ cmpl(FieldAddress(temp, Field::guarded_cid_offset()),
             Immediate(kFloat32x4Cid));
     __ j(EQUAL, &store_float32x4);
 
+    __ cmpl(FieldAddress(temp, Field::guarded_cid_offset()),
+            Immediate(kFloat64x2Cid));
+    __ j(EQUAL, &store_float64x2);
+
     // Fall through.
     __ jmp(&store_pointer);
 
 
     if (!compiler->is_optimizing()) {
       locs()->live_registers()->Add(locs()->in(0));
       locs()->live_registers()->Add(locs()->in(1));
     }
 
     {
@@ skipping 50 matching lines @@
       __ movl(temp2, temp);
       __ StoreIntoObject(instance_reg,
                          FieldAddress(instance_reg, offset_in_bytes_),
                          temp2);
 
       __ Bind(&copy_float32x4);
       __ movups(fpu_temp, FieldAddress(value_reg, Float32x4::value_offset()));
       __ movups(FieldAddress(temp, Float32x4::value_offset()), fpu_temp);
       __ jmp(&skip_store);
     }
+
+    {
+      __ Bind(&store_float64x2);
+      Label copy_float64x2;
+
+      StoreInstanceFieldSlowPath* slow_path =
+          new StoreInstanceFieldSlowPath(this, compiler->float64x2_class());
+      compiler->AddSlowPathCode(slow_path);
+
+      const Immediate& raw_null =
+          Immediate(reinterpret_cast<intptr_t>(Object::null()));
+      __ movl(temp, FieldAddress(instance_reg, offset_in_bytes_));
+      __ cmpl(temp, raw_null);
+      __ j(NOT_EQUAL, &copy_float64x2);
+
+      __ TryAllocate(compiler->float64x2_class(),
+                     slow_path->entry_label(),
+                     Assembler::kFarJump,
+                     temp,
+                     temp2);
+      __ Bind(slow_path->exit_label());
+      __ movl(temp2, temp);
+      __ StoreIntoObject(instance_reg,
+                         FieldAddress(instance_reg, offset_in_bytes_),
+                         temp2);
+
+      __ Bind(&copy_float64x2);
+      __ movups(fpu_temp, FieldAddress(value_reg, Float64x2::value_offset()));
+      __ movups(FieldAddress(temp, Float64x2::value_offset()), fpu_temp);
+      __ jmp(&skip_store);
+    }
+
     __ Bind(&store_pointer);
   }
 
   if (ShouldEmitStoreBarrier()) {
     Register value_reg = locs()->in(1).reg();
     __ StoreIntoObject(instance_reg,
                        FieldAddress(instance_reg, offset_in_bytes_),
                        value_reg,
                        CanValueBeSmi());
   } else {
@@ skipping 241 matching lines @@
     const intptr_t cid = field()->UnboxedFieldCid();
     switch (cid) {
       case kDoubleCid:
         __ Comment("UnboxedDoubleLoadFieldInstr");
         __ movsd(result, FieldAddress(temp, Double::value_offset()));
         break;
       case kFloat32x4Cid:
         __ Comment("UnboxedFloat32x4LoadFieldInstr");
         __ movups(result, FieldAddress(temp, Float32x4::value_offset()));
         break;
+      case kFloat64x2Cid:
+        __ Comment("UnboxedFloat64x2LoadFieldInstr");
+        __ movups(result, FieldAddress(temp, Float64x2::value_offset()));
+        break;
       default:
         UNREACHABLE();
     }
     return;
   }
 
   Label done;
   Register result = locs()->out().reg();
   if (IsPotentialUnboxedLoad()) {
     Register temp = locs()->temp(1).reg();
     XmmRegister value = locs()->temp(0).fpu_reg();
 
 
     Label load_pointer;
     Label load_double;
     Label load_float32x4;
+    Label load_float64x2;
 
     __ LoadObject(result, Field::ZoneHandle(field()->raw()));
 
     FieldAddress field_cid_operand(result, Field::guarded_cid_offset());
     FieldAddress field_nullability_operand(result, Field::is_nullable_offset());
 
     __ cmpl(field_nullability_operand, Immediate(kNullCid));
     __ j(EQUAL, &load_pointer);
 
     __ cmpl(field_cid_operand, Immediate(kDoubleCid));
     __ j(EQUAL, &load_double);
 
     __ cmpl(field_cid_operand, Immediate(kFloat32x4Cid));
     __ j(EQUAL, &load_float32x4);
 
+    __ cmpl(field_cid_operand, Immediate(kFloat64x2Cid));
+    __ j(EQUAL, &load_float64x2);
+
     // Fall through.
     __ jmp(&load_pointer);
 
     if (!compiler->is_optimizing()) {
       locs()->live_registers()->Add(locs()->in(0));
     }
 
     {
       __ Bind(&load_double);
       BoxDoubleSlowPath* slow_path = new BoxDoubleSlowPath(this);
@@ skipping 22 matching lines @@
                      Assembler::kFarJump,
                      result,
                      temp);
       __ Bind(slow_path->exit_label());
       __ movl(temp, FieldAddress(instance_reg, offset_in_bytes()));
       __ movups(value, FieldAddress(temp, Float32x4::value_offset()));
       __ movups(FieldAddress(result, Float32x4::value_offset()), value);
       __ jmp(&done);
     }
 
+    {
+      __ Bind(&load_float64x2);
+
+      BoxFloat64x2SlowPath* slow_path = new BoxFloat64x2SlowPath(this);
+      compiler->AddSlowPathCode(slow_path);
+
+      __ TryAllocate(compiler->float64x2_class(),
+                     slow_path->entry_label(),
+                     Assembler::kFarJump,
+                     result,
+                     temp);
+      __ Bind(slow_path->exit_label());
+      __ movl(temp, FieldAddress(instance_reg, offset_in_bytes()));
+      __ movups(value, FieldAddress(temp, Float64x2::value_offset()));
+      __ movups(FieldAddress(result, Float64x2::value_offset()), value);
+      __ jmp(&done);
+    }
+
     __ Bind(&load_pointer);
   }
   __ movl(result, FieldAddress(instance_reg, offset_in_bytes()));
   __ Bind(&done);
 }
 
 
 LocationSummary* InstantiateTypeInstr::MakeLocationSummary(bool opt) const {
   const intptr_t kNumInputs = 1;
   const intptr_t kNumTemps = 0;
@@ skipping 1285 matching lines @@
 }
 
 
 void Simd32x4ShuffleInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   XmmRegister value = locs()->in(0).fpu_reg();
 
   ASSERT(locs()->out().fpu_reg() == value);
 
   switch (op_kind()) {
     case MethodRecognizer::kFloat32x4ShuffleX:
-      __ shufps(value, value, Immediate(0x00));
+      // Shuffle not necessary.
       __ cvtss2sd(value, value);
       break;
     case MethodRecognizer::kFloat32x4ShuffleY:
       __ shufps(value, value, Immediate(0x55));
       __ cvtss2sd(value, value);
       break;
     case MethodRecognizer::kFloat32x4ShuffleZ:
       __ shufps(value, value, Immediate(0xAA));
       __ cvtss2sd(value, value);
       break;
@@ skipping 410 matching lines @@
 }
 
 
 void Simd64x2ShuffleInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   XmmRegister value = locs()->in(0).fpu_reg();
 
   ASSERT(locs()->out().fpu_reg() == value);
 
   switch (op_kind()) {
     case MethodRecognizer::kFloat64x2GetX:
-      __ shufpd(value, value, Immediate(0x00));
+      // nop.
       break;
     case MethodRecognizer::kFloat64x2GetY:
       __ shufpd(value, value, Immediate(0x33));
       break;
     default: UNREACHABLE();
   }
 }
 
 
 
@@ skipping 1838 matching lines @@
                          PcDescriptors::kOther,
                          locs());
   __ Drop(ArgumentCount());  // Discard arguments.
 }
 
 }  // namespace dart
 
 #undef __
 
 #endif  // defined TARGET_ARCH_IA32