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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 | 4 |
| 5 #include <math.h> // for isnan. | 5 #include <math.h> // for isnan. |
| 6 #include <setjmp.h> | 6 #include <setjmp.h> |
| 7 #include <stdlib.h> | 7 #include <stdlib.h> |
| 8 | 8 |
| 9 #include "vm/globals.h" | 9 #include "vm/globals.h" |
| 10 #if defined(TARGET_ARCH_ARM) | 10 #if defined(TARGET_ARCH_ARM) |
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| 927 void Simulator::set_qregister(QRegister reg, const simd_value_t& value) { | 927 void Simulator::set_qregister(QRegister reg, const simd_value_t& value) { |
| 928 ASSERT((reg >= 0) && (reg < kNumberOfQRegisters)); | 928 ASSERT((reg >= 0) && (reg < kNumberOfQRegisters)); |
| 929 qregisters_[reg].data_[0] = value.data_[0]; | 929 qregisters_[reg].data_[0] = value.data_[0]; |
| 930 qregisters_[reg].data_[1] = value.data_[1]; | 930 qregisters_[reg].data_[1] = value.data_[1]; |
| 931 qregisters_[reg].data_[2] = value.data_[2]; | 931 qregisters_[reg].data_[2] = value.data_[2]; |
| 932 qregisters_[reg].data_[3] = value.data_[3]; | 932 qregisters_[reg].data_[3] = value.data_[3]; |
| 933 } | 933 } |
| 934 | 934 |
| 935 | 935 |
| 936 void Simulator::get_qregister(QRegister reg, simd_value_t* value) const { | 936 void Simulator::get_qregister(QRegister reg, simd_value_t* value) const { |
| 937 ASSERT((reg >= 0) && (reg < kNumberOfQRegisters)); | 937 if ((reg >= 0) && (reg < kNumberOfQRegisters)) { |
|
regis
2013/07/22 22:47:11
Add a todo to replace the test by an assert after
zra
2013/07/22 23:20:09
Done.
| |
| 938 *value = qregisters_[reg]; | 938 *value = qregisters_[reg]; |
| 939 } | |
| 939 } | 940 } |
| 940 | 941 |
| 941 | 942 |
| 942 void Simulator::set_sregister_bits(SRegister reg, int32_t value) { | 943 void Simulator::set_sregister_bits(SRegister reg, int32_t value) { |
| 943 ASSERT((reg >= 0) && (reg < kNumberOfSRegisters)); | 944 ASSERT((reg >= 0) && (reg < kNumberOfSRegisters)); |
| 944 sregisters_[reg] = value; | 945 sregisters_[reg] = value; |
| 945 } | 946 } |
| 946 | 947 |
| 947 | 948 |
| 948 int32_t Simulator::get_sregister_bits(SRegister reg) const { | 949 int32_t Simulator::get_sregister_bits(SRegister reg) const { |
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| 3119 // Format(instr, "vmovq 'qd, 'qm"); | 3120 // Format(instr, "vmovq 'qd, 'qm"); |
| 3120 for (int i = 0; i < 4; i++) { | 3121 for (int i = 0; i < 4; i++) { |
| 3121 s8d.data_[i].u = s8m.data_[i].u; | 3122 s8d.data_[i].u = s8m.data_[i].u; |
| 3122 } | 3123 } |
| 3123 } else { | 3124 } else { |
| 3124 // Format(instr, "vorrq 'qd, 'qm"); | 3125 // Format(instr, "vorrq 'qd, 'qm"); |
| 3125 for (int i = 0; i < 4; i++) { | 3126 for (int i = 0; i < 4; i++) { |
| 3126 s8d.data_[i].u = s8n.data_[i].u | s8m.data_[i].u; | 3127 s8d.data_[i].u = s8n.data_[i].u | s8m.data_[i].u; |
| 3127 } | 3128 } |
| 3128 } | 3129 } |
| 3130 } else if ((instr->Bits(8, 4) == 1) && (instr->Bit(4) == 1) && | |
| 3131 (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 0)) { | |
| 3132 // Format(instr, "vandq 'qd, 'qn, 'qm"); | |
| 3133 for (int i = 0; i < 4; i++) { | |
| 3134 s8d.data_[i].u = s8n.data_[i].u & s8m.data_[i].u; | |
| 3135 } | |
| 3129 } else if ((instr->Bits(8, 4) == 15) && (instr->Bit(4) == 0) && | 3136 } else if ((instr->Bits(8, 4) == 15) && (instr->Bit(4) == 0) && |
| 3130 (instr->Bits(20, 2) == 2) && (instr->Bits(23, 2) == 0)) { | 3137 (instr->Bits(20, 2) == 2) && (instr->Bits(23, 2) == 0)) { |
| 3131 // Format(instr, "vminqs 'qd, 'qn, 'qm"); | 3138 // Format(instr, "vminqs 'qd, 'qn, 'qm"); |
| 3132 for (int i = 0; i < 4; i++) { | 3139 for (int i = 0; i < 4; i++) { |
| 3133 s8d.data_[i].f = | 3140 s8d.data_[i].f = |
| 3134 s8n.data_[i].f <= s8m.data_[i].f ? s8n.data_[i].f : s8m.data_[i].f; | 3141 s8n.data_[i].f <= s8m.data_[i].f ? s8n.data_[i].f : s8m.data_[i].f; |
| 3135 } | 3142 } |
| 3136 } else if ((instr->Bits(8, 4) == 15) && (instr->Bit(4) == 0) && | 3143 } else if ((instr->Bits(8, 4) == 15) && (instr->Bit(4) == 0) && |
| 3137 (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 0)) { | 3144 (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 0)) { |
| 3138 // Format(instr, "vmaxqs 'qd, 'qn, 'qm"); | 3145 // Format(instr, "vmaxqs 'qd, 'qn, 'qm"); |
| 3139 for (int i = 0; i < 4; i++) { | 3146 for (int i = 0; i < 4; i++) { |
| 3140 s8d.data_[i].f = | 3147 s8d.data_[i].f = |
| 3141 s8n.data_[i].f >= s8m.data_[i].f ? s8n.data_[i].f : s8m.data_[i].f; | 3148 s8n.data_[i].f >= s8m.data_[i].f ? s8n.data_[i].f : s8m.data_[i].f; |
| 3142 } | 3149 } |
| 3150 } else if ((instr->Bits(8, 4) == 7) && (instr->Bit(4) == 0) && | |
| 3151 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) && | |
| 3152 (instr->Bit(7) == 0) && (instr->Bits(16, 4) == 9)) { | |
| 3153 // Format(instr, "vabsqs 'qd, 'qm"); | |
| 3154 for (int i = 0; i < 4; i++) { | |
| 3155 s8d.data_[i].f = abs(s8m.data_[i].f); | |
| 3156 } | |
| 3157 } else if ((instr->Bits(8, 4) == 7) && (instr->Bit(4) == 0) && | |
| 3158 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) && | |
| 3159 (instr->Bit(7) == 1) && (instr->Bits(16, 4) == 9)) { | |
| 3160 // Format(instr, "vnegqs 'qd, 'qm"); | |
| 3161 for (int i = 0; i < 4; i++) { | |
| 3162 s8d.data_[i].f = -s8m.data_[i].f; | |
| 3163 } | |
| 3143 } else if ((instr->Bits(7, 5) == 10) && (instr->Bit(4) == 0) && | 3164 } else if ((instr->Bits(7, 5) == 10) && (instr->Bit(4) == 0) && |
| 3144 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) && | 3165 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) && |
| 3145 (instr->Bits(16, 4) == 11)) { | 3166 (instr->Bits(16, 4) == 11)) { |
| 3146 // Format(instr, "vrecpeq 'qd, 'qm"); | 3167 // Format(instr, "vrecpeq 'qd, 'qm"); |
| 3147 for (int i = 0; i < 4; i++) { | 3168 for (int i = 0; i < 4; i++) { |
| 3148 s8d.data_[i].f = arm_recip_estimate(s8m.data_[i].f); | 3169 s8d.data_[i].f = arm_recip_estimate(s8m.data_[i].f); |
| 3149 } | 3170 } |
| 3150 } else if ((instr->Bits(8, 4) == 15) && (instr->Bit(4) == 1) && | 3171 } else if ((instr->Bits(8, 4) == 15) && (instr->Bit(4) == 1) && |
| 3151 (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 0)) { | 3172 (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 0)) { |
| 3152 // Format(instr, "vrecpsq 'qd, 'qn, 'qm"); | 3173 // Format(instr, "vrecpsq 'qd, 'qn, 'qm"); |
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| 3603 set_register(kExceptionObjectReg, bit_cast<int32_t>(raw_exception)); | 3624 set_register(kExceptionObjectReg, bit_cast<int32_t>(raw_exception)); |
| 3604 set_register(kStackTraceObjectReg, bit_cast<int32_t>(raw_stacktrace)); | 3625 set_register(kStackTraceObjectReg, bit_cast<int32_t>(raw_stacktrace)); |
| 3605 buf->Longjmp(); | 3626 buf->Longjmp(); |
| 3606 } | 3627 } |
| 3607 | 3628 |
| 3608 } // namespace dart | 3629 } // namespace dart |
| 3609 | 3630 |
| 3610 #endif // !defined(HOST_ARCH_ARM) | 3631 #endif // !defined(HOST_ARCH_ARM) |
| 3611 | 3632 |
| 3612 #endif // defined TARGET_ARCH_ARM | 3633 #endif // defined TARGET_ARCH_ARM |
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