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Side by Side Diff: runtime/vm/disassembler_arm.cc

Issue 19493004: Adds more SIMD instructions for ARM. (Closed) Base URL: http://dart.googlecode.com/svn/branches/bleeding_edge/dart/
Patch Set: Created 7 years, 5 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #include "vm/disassembler.h" 5 #include "vm/disassembler.h"
6 6
7 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM. 7 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM.
8 #if defined(TARGET_ARCH_ARM) 8 #if defined(TARGET_ARCH_ARM)
9 #include "platform/assert.h" 9 #include "platform/assert.h"
10 10
(...skipping 1317 matching lines...) Expand 10 before | Expand all | Expand 10 after
1328 } else if ((instr->Bits(8, 4) == 1) && (instr->Bit(4) == 1) && 1328 } else if ((instr->Bits(8, 4) == 1) && (instr->Bit(4) == 1) &&
1329 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 0)) { 1329 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 0)) {
1330 Format(instr, "vornq 'qd, 'qn, 'qm"); 1330 Format(instr, "vornq 'qd, 'qn, 'qm");
1331 } else if ((instr->Bits(8, 4) == 1) && (instr->Bit(4) == 1) && 1331 } else if ((instr->Bits(8, 4) == 1) && (instr->Bit(4) == 1) &&
1332 (instr->Bits(20, 2) == 2) && (instr->Bits(23, 2) == 0)) { 1332 (instr->Bits(20, 2) == 2) && (instr->Bits(23, 2) == 0)) {
1333 if (instr->QmField() == instr->QnField()) { 1333 if (instr->QmField() == instr->QnField()) {
1334 Format(instr, "vmovq 'qd, 'qm"); 1334 Format(instr, "vmovq 'qd, 'qm");
1335 } else { 1335 } else {
1336 Format(instr, "vorrq 'qd, 'qm"); 1336 Format(instr, "vorrq 'qd, 'qm");
1337 } 1337 }
1338 } else if ((instr->Bits(8, 4) == 1) && (instr->Bit(4) == 1) &&
1339 (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 0)) {
1340 Format(instr, "vandq 'qd, 'qn, 'qm");
1338 } else if ((instr->Bits(8, 4) == 15) && (instr->Bit(4) == 0) && 1341 } else if ((instr->Bits(8, 4) == 15) && (instr->Bit(4) == 0) &&
1339 (instr->Bits(20, 2) == 2) && (instr->Bits(23, 2) == 0)) { 1342 (instr->Bits(20, 2) == 2) && (instr->Bits(23, 2) == 0)) {
1340 Format(instr, "vminqs 'qd, 'qn, 'qm"); 1343 Format(instr, "vminqs 'qd, 'qn, 'qm");
1341 } else if ((instr->Bits(8, 4) == 15) && (instr->Bit(4) == 0) && 1344 } else if ((instr->Bits(8, 4) == 15) && (instr->Bit(4) == 0) &&
1342 (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 0)) { 1345 (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 0)) {
1343 Format(instr, "vmaxqs 'qd, 'qn, 'qm"); 1346 Format(instr, "vmaxqs 'qd, 'qn, 'qm");
1347 } else if ((instr->Bits(8, 4) == 7) && (instr->Bit(4) == 0) &&
1348 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) &&
1349 (instr->Bit(7) == 0) && (instr->Bits(16, 4) == 9)) {
1350 Format(instr, "vabsqs 'qd, 'qm");
1351 } else if ((instr->Bits(8, 4) == 7) && (instr->Bit(4) == 0) &&
1352 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) &&
1353 (instr->Bit(7) == 1) && (instr->Bits(16, 4) == 9)) {
1354 Format(instr, "vnegqs 'qd, 'qm");
1344 } else if ((instr->Bits(7, 5) == 10) && (instr->Bit(4) == 0) && 1355 } else if ((instr->Bits(7, 5) == 10) && (instr->Bit(4) == 0) &&
1345 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) && 1356 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) &&
1346 (instr->Bits(16, 4) == 11)) { 1357 (instr->Bits(16, 4) == 11)) {
1347 Format(instr, "vrecpeqs 'qd, 'qm"); 1358 Format(instr, "vrecpeqs 'qd, 'qm");
1348 } else if ((instr->Bits(8, 4) == 15) && (instr->Bit(4) == 1) && 1359 } else if ((instr->Bits(8, 4) == 15) && (instr->Bit(4) == 1) &&
1349 (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 0)) { 1360 (instr->Bits(20, 2) == 0) && (instr->Bits(23, 2) == 0)) {
1350 Format(instr, "vrecpsqs 'qd, 'qn, 'qm"); 1361 Format(instr, "vrecpsqs 'qd, 'qn, 'qm");
1351 } else if ((instr->Bits(8, 4) == 5) && (instr->Bit(4) == 0) && 1362 } else if ((instr->Bits(8, 4) == 5) && (instr->Bit(4) == 0) &&
1352 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) && 1363 (instr->Bits(20, 2) == 3) && (instr->Bits(23, 2) == 3) &&
1353 (instr->Bit(7) == 1) && (instr->Bits(16, 4) == 11)) { 1364 (instr->Bit(7) == 1) && (instr->Bits(16, 4) == 11)) {
(...skipping 147 matching lines...) Expand 10 before | Expand all | Expand 10 after
1501 human_buffer, 1512 human_buffer,
1502 sizeof(human_buffer), 1513 sizeof(human_buffer),
1503 pc); 1514 pc);
1504 pc += instruction_length; 1515 pc += instruction_length;
1505 } 1516 }
1506 } 1517 }
1507 1518
1508 } // namespace dart 1519 } // namespace dart
1509 1520
1510 #endif // defined TARGET_ARCH_ARM 1521 #endif // defined TARGET_ARCH_ARM
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