[Subzero][MIPS32] Implement sext, zext and trunc

src/IceInstMIPS32.h

Index: src/IceInstMIPS32.h
diff --git a/src/IceInstMIPS32.h b/src/IceInstMIPS32.h
index e364f7f2ea8b5850761e2eb84b69bd0509a35d09..83a8decd200c76f560a099cc866ce82ff2d8f88d 100644
--- a/src/IceInstMIPS32.h
+++ b/src/IceInstMIPS32.h
@@ -121,6 +121,7 @@ public:
     Addiu,
     Addu,
     And,
+    Andi,
     Br,
     Call,
     La,
@@ -137,10 +138,12 @@ public:
     Or,
     Ori,
     Ret,
+    Sll,
     Slt,
     Slti,
     Sltiu,
     Sltu,
+    Sra,
     Sub,
     Subu,
     Xor,
@@ -404,6 +407,12 @@ public:
         InstMIPS32Imm16(Func, Dest, Imm);
   }
 
+  static InstMIPS32Imm16 *create(Cfg *Func, Variable *Dest, Operand *Source,
+                                 ConstantInteger32 *Imm) {
+    return new (Func->allocate<InstMIPS32Imm16>())
+        InstMIPS32Imm16(Func, Dest, Source, Imm);
+  }
+
   void emit(const Cfg *Func) const override {
     if (!BuildDefs::dump())
       return;
@@ -453,6 +462,12 @@ private:
   InstMIPS32Imm16(Cfg *Func, Variable *Dest, uint32_t Imm)
       : InstMIPS32(Func, K, 0, Dest), Imm(Imm) {}
 
+  InstMIPS32Imm16(Cfg *Func, Variable *Dest, Operand *Source,

[Jim Stichnoth, 2016/05/06 19:55:09]

Why is this new form needed?

It seems to me that if the specific MIPS instruction requires an Imm16 operand,
you might as well keep it simple and just use the uint32_t form?

It's really up to the TargetLowering implementation (e.g. MIPS32) to decide how
to handle these things, so I just wanted to understand the assumptions/direction
here.

[sagar.thakur, 2016/05/09 11:03:40]

I was following arm and x86 implementation of TargetLowering. Yes, this is
actually not needed here. I'll just use the uint32_t form.

+                  ConstantInteger32 *Imm)
+      : InstMIPS32(Func, K, 1, Dest), Imm(Imm->getValue()) {
+    addSource(Source);
+  }
+
   static const char *Opcode;
 
   const uint32_t Imm;
@@ -462,6 +477,7 @@ using InstMIPS32Add = InstMIPS32ThreeAddrGPR<InstMIPS32::Add>;
 using InstMIPS32Addu = InstMIPS32ThreeAddrGPR<InstMIPS32::Addu>;
 using InstMIPS32Addiu = InstMIPS32Imm16<InstMIPS32::Addiu, true>;
 using InstMIPS32And = InstMIPS32ThreeAddrGPR<InstMIPS32::And>;
+using InstMIPS32Andi = InstMIPS32Imm16<InstMIPS32::Andi>;
 using InstMIPS32Lui = InstMIPS32Imm16<InstMIPS32::Lui>;
 using InstMIPS32La = InstMIPS32UnaryopGPR<InstMIPS32::La>;
 using InstMIPS32Mfhi = InstMIPS32UnaryopGPR<InstMIPS32::Mfhi>;
@@ -473,10 +489,12 @@ using InstMIPS32Mult = InstMIPS32ThreeAddrGPR<InstMIPS32::Mult>;
 using InstMIPS32Multu = InstMIPS32ThreeAddrGPR<InstMIPS32::Multu>;
 using InstMIPS32Or = InstMIPS32ThreeAddrGPR<InstMIPS32::Or>;
 using InstMIPS32Ori = InstMIPS32Imm16<InstMIPS32::Ori>;
+using InstMIPS32Sll = InstMIPS32Imm16<InstMIPS32::Sll>;
 using InstMIPS32Slt = InstMIPS32ThreeAddrGPR<InstMIPS32::Slt>;
 using InstMIPS32Slti = InstMIPS32Imm16<InstMIPS32::Slti>;
 using InstMIPS32Sltiu = InstMIPS32Imm16<InstMIPS32::Sltiu>;
 using InstMIPS32Sltu = InstMIPS32ThreeAddrGPR<InstMIPS32::Sltu>;
+using InstMIPS32Sra = InstMIPS32Imm16<InstMIPS32::Sra>;
 using InstMIPS32Sub = InstMIPS32ThreeAddrGPR<InstMIPS32::Sub>;
 using InstMIPS32Subu = InstMIPS32ThreeAddrGPR<InstMIPS32::Subu>;
 using InstMIPS32Ori = InstMIPS32Imm16<InstMIPS32::Ori>;