[Subzero][MIPS32] Implement sext, zext and trunc

tests_lit/llvm2ice_tests/64bit.pnacl.ll

 ; This tries to be a comprehensive test of i64 operations, in
 ; particular the patterns for lowering i64 operations into constituent
 ; i32 operations on x86-32.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
@@ skipping 781 matching lines @@
 }
 ; CHECK-LABEL: trunc64To32Signed
 ; CHECK: mov     eax,DWORD PTR [esp+0xc]
 ;
 ; OPTM1-LABEL: trunc64To32Signed
 ; OPTM1: mov     eax,DWORD PTR [esp+
 
 ; ARM32-LABEL: trunc64To32Signed
 ; ARM32: mov r0, r2
 
+; MIPS32-LABEL: trunc64To32Signed
+; MIPS32: move v0,a2 
+
 define internal i32 @trunc64To16Signed(i64 %a) {
 entry:
   %conv = trunc i64 %a to i16
   %conv.ret_ext = sext i16 %conv to i32
   ret i32 %conv.ret_ext
 }
 ; CHECK-LABEL: trunc64To16Signed
 ; CHECK:      mov     eax,DWORD PTR [esp+0x4]
 ; CHECK-NEXT: movsx  eax,ax
 ;
 ; OPTM1-LABEL: trunc64To16Signed
 ; OPTM1:      mov     ax,WORD PTR [esp+
 ; OPTM1: movsx  eax,
 
 ; ARM32-LABEL: trunc64To16Signed
 ; ARM32: sxth r0, r0
 
+; MIPS32-LABEL: trunc64To16Signed
+; MIPS32: sll a0,a0,0x10 
+; MIPS32: sra a0,a0,0x10 
+; MIPS32: move v0,a0
+
 define internal i32 @trunc64To8Signed(i64 %a) {
 entry:
   %conv = trunc i64 %a to i8
   %conv.ret_ext = sext i8 %conv to i32
   ret i32 %conv.ret_ext
 }
 ; CHECK-LABEL: trunc64To8Signed
 ; CHECK:      mov     eax,DWORD PTR [esp+0x4]
 ; CHECK-NEXT: movsx  eax,al
 ;
 ; OPTM1-LABEL: trunc64To8Signed
 ; OPTM1:      mov     eax,DWORD PTR [esp+
 ; OPTM1: movsx  eax,
 
 ; ARM32-LABEL: trunc64To8Signed
 ; ARM32: sxtb r0, r0
 
+; MIPS32-LABEL: trunc64To8Signed
+; MIPS32: sll a0,a0,0x18
+; MIPS32: sra a0,a0,0x18
+; MIPS32: move v0,a0
+
 define internal i32 @trunc64To32SignedConst() {
 entry:
   %conv = trunc i64 12345678901234 to i32
   ret i32 %conv
 }
 ; CHECK-LABEL: trunc64To32SignedConst
 ; CHECK: mov eax,0x73ce2ff2
 ;
 ; OPTM1-LABEL: trunc64To32SignedConst
 ; OPTM1: mov eax,0x73ce2ff2
 
 ; ARM32-LABEL: trunc64To32SignedConst
 ; ARM32: movw r0, #12274 ; 0x2ff2
 ; ARM32: movt r0, #29646 ; 0x73ce
 
+; MIPS32-LABEL: trunc64To32SignedConst
+; MIPS32: lui v0,0x73ce 
+; MIPS32: ori v0,v0,0x2ff2
+
 define internal i32 @trunc64To16SignedConst() {
 entry:
   %conv = trunc i64 12345678901234 to i16
   %conv.ret_ext = sext i16 %conv to i32
   ret i32 %conv.ret_ext
 }
 ; CHECK-LABEL: trunc64To16SignedConst
 ; CHECK: mov eax,0x73ce2ff2
 ; CHECK: movsx eax,ax
 ;
 ; OPTM1-LABEL: trunc64To16SignedConst
 ; OPTM1: mov eax,0x73ce2ff2
 ; OPTM1: movsx eax,
 
 ; ARM32-LABEL: trunc64To16SignedConst
 ; ARM32: movw r0, #12274 ; 0x2ff2
 ; ARM32: movt r0, #29646 ; 0x73ce
 ; ARM32: sxth r0, r0
 
+; MIPS32-LABEL: trunc64To16SignedConst
+; MIPS32: lui v0,0x73ce 
+; MIPS32: ori v0,v0,0x2ff2
+; MIPS32: sll v0,v0,0x10
+; MIPS32: sra v0,v0,0x10
+
 define internal i32 @trunc64To32Unsigned(i64 %padding, i64 %a) {
 entry:
   %conv = trunc i64 %a to i32
   ret i32 %conv
 }
 ; CHECK-LABEL: trunc64To32Unsigned
 ; CHECK: mov     eax,DWORD PTR [esp+0xc]
 ;
 ; OPTM1-LABEL: trunc64To32Unsigned
 ; OPTM1: mov     eax,DWORD PTR [esp+
 
 ; ARM32-LABEL: trunc64To32Unsigned
 ; ARM32: mov r0, r2
 
+; MIPS32-LABEL: trunc64To32Unsigned
+; MIPS32: move v0,a2
+
 define internal i32 @trunc64To16Unsigned(i64 %a) {
 entry:
   %conv = trunc i64 %a to i16
   %conv.ret_ext = zext i16 %conv to i32
   ret i32 %conv.ret_ext
 }
 ; CHECK-LABEL: trunc64To16Unsigned
 ; CHECK:      mov     eax,DWORD PTR [esp+0x4]
 ; CHECK-NEXT: movzx  eax,ax
 ;
 ; OPTM1-LABEL: trunc64To16Unsigned
 ; OPTM1:      mov     ax,WORD PTR [esp+
 ; OPTM1: movzx  eax,
 
 ; ARM32-LABEL: trunc64To16Unsigned
 ; ARM32: uxth
 
+; MIPS32-LABEL: trunc64To16Unsigned
+; MIPS32: andi a0,a0,0xffff
+; MIPS32: move v0,a0
+
 define internal i32 @trunc64To8Unsigned(i64 %a) {
 entry:
   %conv = trunc i64 %a to i8
   %conv.ret_ext = zext i8 %conv to i32
   ret i32 %conv.ret_ext
 }
 ; CHECK-LABEL: trunc64To8Unsigned
 ; CHECK:      mov     eax,DWORD PTR [esp+0x4]
 ; CHECK-NEXT: movzx  eax,al
 ;
 ; OPTM1-LABEL: trunc64To8Unsigned
 ; OPTM1: mov    eax,DWORD PTR [esp+
 ; OPTM1: movzx  eax,
 
 ; ARM32-LABEL: trunc64To8Unsigned
 ; ARM32: uxtb
 
+; MIPS32-LABEL: trunc64To8Unsigned
+; MIPS32: andi a0,a0,0xff
+; MIPS32: move v0,a0
+
 define internal i32 @trunc64To1(i64 %a) {
 entry:
 ;  %tobool = icmp ne i64 %a, 0
   %tobool = trunc i64 %a to i1
   %tobool.ret_ext = zext i1 %tobool to i32
   ret i32 %tobool.ret_ext
 }
 ; CHECK-LABEL: trunc64To1
 ; CHECK:      mov     eax,DWORD PTR [esp+0x4]
 ; CHECK:      and     al,0x1
@@ skipping 17 matching lines @@
 ; CHECK: mov
 ; CHECK: sar {{.*}},0x1f
 ;
 ; OPTM1-LABEL: sext32To64
 ; OPTM1: mov
 ; OPTM1: sar {{.*}},0x1f
 
 ; ARM32-LABEL: sext32To64
 ; ARM32: asr {{.*}}, #31
 
+; MIPS32-LABEL: sext32To64
+; MIPS32-LABEL: sra v1,a0,0x1f
+; MIPS32-LABEL: move v0,a0
+
 define internal i64 @sext16To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i16
   %conv = sext i16 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: sext16To64
 ; CHECK: movsx
 ; CHECK: sar {{.*}},0x1f
 ;
 ; OPTM1-LABEL: sext16To64
 ; OPTM1: movsx
 ; OPTM1: sar {{.*}},0x1f
 
 ; ARM32-LABEL: sext16To64
 ; ARM32: sxth
 ; ARM32: asr {{.*}}, #31
 
+; MIPS32-LABEL: sext16To64
+; MIPS32: sll a0,a0,0x10
+; MIPS32: sra a0,a0,0x10 
+; MIPS32: sra v1,a0,0x1f
+; MIPS32: move v0,a0
+
 define internal i64 @sext8To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i8
   %conv = sext i8 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: sext8To64
 ; CHECK: movsx
 ; CHECK: sar {{.*}},0x1f
 ;
 ; OPTM1-LABEL: sext8To64
 ; OPTM1: movsx
 ; OPTM1: sar {{.*}},0x1f
 
 ; ARM32-LABEL: sext8To64
 ; ARM32: sxtb
 ; ARM32: asr {{.*}}, #31
 
+; MIPS32-LABEL: sext8To64
+; MIPS32: sll a0,a0,0x18
+; MIPS32: sra a0,a0,0x18
+; MIPS32: sra v1,a0,0x1f
+; MIPS32: move v0,a0
+
 define internal i64 @sext1To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i1
   %conv = sext i1 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: sext1To64
 ; CHECK: mov
 ; CHECK: shl {{.*}},0x1f
 ; CHECK: sar {{.*}},0x1f
@@ skipping 18 matching lines @@
 ; CHECK: mov
 ; CHECK: mov {{.*}},0x0
 ;
 ; OPTM1-LABEL: zext32To64
 ; OPTM1: mov
 ; OPTM1: mov {{.*}},0x0
 
 ; ARM32-LABEL: zext32To64
 ; ARM32: mov {{.*}}, #0
 
+; MIPS32-LABEL: zext32To64
+; MIPS32: li v1,0
+; MIPS32: move v0,a0
+
 define internal i64 @zext16To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i16
   %conv = zext i16 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: zext16To64
 ; CHECK: movzx
 ; CHECK: mov {{.*}},0x0
 ;
 ; OPTM1-LABEL: zext16To64
 ; OPTM1: movzx
 ; OPTM1: mov {{.*}},0x0
 
 ; ARM32-LABEL: zext16To64
 ; ARM32: uxth
 ; ARM32: mov {{.*}}, #0
 
+; MIPS32-LABEL: zext16To64
+; MIPS32: andi a0,a0,0xffff
+; MIPS32: li v1,0
+; MIPS32: move v0,a0
+
 define internal i64 @zext8To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i8
   %conv = zext i8 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: zext8To64
 ; CHECK: movzx
 ; CHECK: mov {{.*}},0x0
 ;
 ; OPTM1-LABEL: zext8To64
 ; OPTM1: movzx
 ; OPTM1: mov {{.*}},0x0
 
 ; ARM32-LABEL: zext8To64
 ; ARM32: uxtb
 ; ARM32: mov {{.*}}, #0
 
+; MIPS32-LABEL: zext8To64
+; MIPS32: andi a0,a0,0xff
+; MIPS32: li v1,0
+; MIPS32: move v0,a0
+
 define internal i64 @zext1To64(i32 %a) {
 entry:
   %a.arg_trunc = trunc i32 %a to i1
   %conv = zext i1 %a.arg_trunc to i64
   ret i64 %conv
 }
 ; CHECK-LABEL: zext1To64
 ; CHECK: and {{.*}},0x1
 ; CHECK: mov {{.*}},0x0
 ;
@@ skipping 898 matching lines @@
   %s = lshr i64 %a, 40
   %t = trunc i64 %s to i32
   %r = sub i32 %t, 1
   ret i32 %r
 ; ARM32-LABEL: subOneToUpperAfterShift
 ; ARM32: subs
 ; ARM32: sbc
 ; ARM32: lsr
 ; ARM32: sub
 }