[Subzero][MIPS32] Implement sext, zext and trunc

src/IceTargetLoweringMIPS32.h

 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 132 matching lines @@
   }
 
   void _addu(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32Addu>(Dest, Src0, Src1);
   }
 
   void _and(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32And>(Dest, Src0, Src1);
   }
 
+  void _andi(Variable *Dest, Variable *Src, uint32_t Imm) {
+    Context.insert<InstMIPS32Andi>(Dest, Src, Imm);
+  }
+
   void _br(CfgNode *Target) { Context.insert<InstMIPS32Br>(Target); }
 
   void _ret(Variable *RA, Variable *Src0 = nullptr) {
     Context.insert<InstMIPS32Ret>(RA, Src0);
   }
 
   void _addiu(Variable *Dest, Variable *Src, uint32_t Imm) {
     Context.insert<InstMIPS32Addiu>(Dest, Src, Imm);
   }
 
@@ skipping 46 matching lines @@
   }
 
   void _or(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32Or>(Dest, Src0, Src1);
   }
 
   void _ori(Variable *Dest, Variable *Src, uint32_t Imm) {
     Context.insert<InstMIPS32Ori>(Dest, Src, Imm);
   }
 
+  void _sll(Variable *Dest, Variable *Src, uint32_t Imm) {
+    Context.insert<InstMIPS32Sll>(Dest, Src, Imm);
+  }
+
   void _slt(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32Slt>(Dest, Src0, Src1);
   }
 
   void _slti(Variable *Dest, Variable *Src, uint32_t Imm) {
     Context.insert<InstMIPS32Slti>(Dest, Src, Imm);
   }
 
   void _sltiu(Variable *Dest, Variable *Src, uint32_t Imm) {
     Context.insert<InstMIPS32Sltiu>(Dest, Src, Imm);
   }
 
   void _sltu(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32Sltu>(Dest, Src0, Src1);
   }
 
+  void _sra(Variable *Dest, Variable *Src, uint32_t Imm) {
+    Context.insert<InstMIPS32Sra>(Dest, Src, Imm);
+  }
+
   void _sub(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32Sub>(Dest, Src0, Src1);
   }
 
   void _subu(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32Subu>(Dest, Src0, Src1);
   }
 
   void _xor(Variable *Dest, Variable *Src0, Variable *Src1) {
     Context.insert<InstMIPS32Xor>(Dest, Src0, Src1);
@@ skipping 94 matching lines @@
                                 const SmallBitVector &ExcludeRegisters,
                                 uint64_t Salt) const override;
 
   bool UsesFramePointer = false;
   bool NeedsStackAlignment = false;
   static SmallBitVector TypeToRegisterSet[RCMIPS32_NUM];
   static SmallBitVector TypeToRegisterSetUnfiltered[RCMIPS32_NUM];
   static SmallBitVector RegisterAliases[RegMIPS32::Reg_NUM];
   SmallBitVector RegsUsed;
   VarList PhysicalRegisters[IceType_NUM];
+  static constexpr uint32_t CHAR_BITS = 8;
+  static constexpr uint32_t INT32_BITS = 32;
 
 private:
   ENABLE_MAKE_UNIQUE;
 };
 
 class TargetDataMIPS32 final : public TargetDataLowering {
   TargetDataMIPS32() = delete;
   TargetDataMIPS32(const TargetDataMIPS32 &) = delete;
   TargetDataMIPS32 &operator=(const TargetDataMIPS32 &) = delete;
 
@@ skipping 31 matching lines @@
   explicit TargetHeaderMIPS32(GlobalContext *Ctx);
 
 private:
   ~TargetHeaderMIPS32() = default;
 };
 
 } // end of namespace MIPS32
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H